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1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef __DT_BINDINGS_Q6_AUDIO_PORTS_H__3#define __DT_BINDINGS_Q6_AUDIO_PORTS_H__4 5/* LPASS Audio virtual ports IDs */6#define HDMI_RX 17#define SLIMBUS_0_RX 28#define SLIMBUS_0_TX 39#define SLIMBUS_1_RX 410#define SLIMBUS_1_TX 511#define SLIMBUS_2_RX 612#define SLIMBUS_2_TX 713#define SLIMBUS_3_RX 814#define SLIMBUS_3_TX 915#define SLIMBUS_4_RX 1016#define SLIMBUS_4_TX 1117#define SLIMBUS_5_RX 1218#define SLIMBUS_5_TX 1319#define SLIMBUS_6_RX 1420#define SLIMBUS_6_TX 1521#define PRIMARY_MI2S_RX 1622#define PRIMARY_MI2S_TX 1723#define SECONDARY_MI2S_RX 1824#define SECONDARY_MI2S_TX 1925#define TERTIARY_MI2S_RX 2026#define TERTIARY_MI2S_TX 2127#define QUATERNARY_MI2S_RX 2228#define QUATERNARY_MI2S_TX 2329#define PRIMARY_TDM_RX_0 2430#define PRIMARY_TDM_TX_0 2531#define PRIMARY_TDM_RX_1 2632#define PRIMARY_TDM_TX_1 2733#define PRIMARY_TDM_RX_2 2834#define PRIMARY_TDM_TX_2 2935#define PRIMARY_TDM_RX_3 3036#define PRIMARY_TDM_TX_3 3137#define PRIMARY_TDM_RX_4 3238#define PRIMARY_TDM_TX_4 3339#define PRIMARY_TDM_RX_5 3440#define PRIMARY_TDM_TX_5 3541#define PRIMARY_TDM_RX_6 3642#define PRIMARY_TDM_TX_6 3743#define PRIMARY_TDM_RX_7 3844#define PRIMARY_TDM_TX_7 3945#define SECONDARY_TDM_RX_0 4046#define SECONDARY_TDM_TX_0 4147#define SECONDARY_TDM_RX_1 4248#define SECONDARY_TDM_TX_1 4349#define SECONDARY_TDM_RX_2 4450#define SECONDARY_TDM_TX_2 4551#define SECONDARY_TDM_RX_3 4652#define SECONDARY_TDM_TX_3 4753#define SECONDARY_TDM_RX_4 4854#define SECONDARY_TDM_TX_4 4955#define SECONDARY_TDM_RX_5 5056#define SECONDARY_TDM_TX_5 5157#define SECONDARY_TDM_RX_6 5258#define SECONDARY_TDM_TX_6 5359#define SECONDARY_TDM_RX_7 5460#define SECONDARY_TDM_TX_7 5561#define TERTIARY_TDM_RX_0 5662#define TERTIARY_TDM_TX_0 5763#define TERTIARY_TDM_RX_1 5864#define TERTIARY_TDM_TX_1 5965#define TERTIARY_TDM_RX_2 6066#define TERTIARY_TDM_TX_2 6167#define TERTIARY_TDM_RX_3 6268#define TERTIARY_TDM_TX_3 6369#define TERTIARY_TDM_RX_4 6470#define TERTIARY_TDM_TX_4 6571#define TERTIARY_TDM_RX_5 6672#define TERTIARY_TDM_TX_5 6773#define TERTIARY_TDM_RX_6 6874#define TERTIARY_TDM_TX_6 6975#define TERTIARY_TDM_RX_7 7076#define TERTIARY_TDM_TX_7 7177#define QUATERNARY_TDM_RX_0 7278#define QUATERNARY_TDM_TX_0 7379#define QUATERNARY_TDM_RX_1 7480#define QUATERNARY_TDM_TX_1 7581#define QUATERNARY_TDM_RX_2 7682#define QUATERNARY_TDM_TX_2 7783#define QUATERNARY_TDM_RX_3 7884#define QUATERNARY_TDM_TX_3 7985#define QUATERNARY_TDM_RX_4 8086#define QUATERNARY_TDM_TX_4 8187#define QUATERNARY_TDM_RX_5 8288#define QUATERNARY_TDM_TX_5 8389#define QUATERNARY_TDM_RX_6 8490#define QUATERNARY_TDM_TX_6 8591#define QUATERNARY_TDM_RX_7 8692#define QUATERNARY_TDM_TX_7 8793#define QUINARY_TDM_RX_0 8894#define QUINARY_TDM_TX_0 8995#define QUINARY_TDM_RX_1 9096#define QUINARY_TDM_TX_1 9197#define QUINARY_TDM_RX_2 9298#define QUINARY_TDM_TX_2 9399#define QUINARY_TDM_RX_3 94100#define QUINARY_TDM_TX_3 95101#define QUINARY_TDM_RX_4 96102#define QUINARY_TDM_TX_4 97103#define QUINARY_TDM_RX_5 98104#define QUINARY_TDM_TX_5 99105#define QUINARY_TDM_RX_6 100106#define QUINARY_TDM_TX_6 101107#define QUINARY_TDM_RX_7 102108#define QUINARY_TDM_TX_7 103109#define DISPLAY_PORT_RX 104110#define WSA_CODEC_DMA_RX_0 105111#define WSA_CODEC_DMA_TX_0 106112#define WSA_CODEC_DMA_RX_1 107113#define WSA_CODEC_DMA_TX_1 108114#define WSA_CODEC_DMA_TX_2 109115#define VA_CODEC_DMA_TX_0 110116#define VA_CODEC_DMA_TX_1 111117#define VA_CODEC_DMA_TX_2 112118#define RX_CODEC_DMA_RX_0 113119#define TX_CODEC_DMA_TX_0 114120#define RX_CODEC_DMA_RX_1 115121#define TX_CODEC_DMA_TX_1 116122#define RX_CODEC_DMA_RX_2 117123#define TX_CODEC_DMA_TX_2 118124#define RX_CODEC_DMA_RX_3 119125#define TX_CODEC_DMA_TX_3 120126#define RX_CODEC_DMA_RX_4 121127#define TX_CODEC_DMA_TX_4 122128#define RX_CODEC_DMA_RX_5 123129#define TX_CODEC_DMA_TX_5 124130#define RX_CODEC_DMA_RX_6 125131#define RX_CODEC_DMA_RX_7 126132#define QUINARY_MI2S_RX 127133#define QUINARY_MI2S_TX 128134#define DISPLAY_PORT_RX_0 DISPLAY_PORT_RX135#define DISPLAY_PORT_RX_1 129136#define DISPLAY_PORT_RX_2 130137#define DISPLAY_PORT_RX_3 131138#define DISPLAY_PORT_RX_4 132139#define DISPLAY_PORT_RX_5 133140#define DISPLAY_PORT_RX_6 134141#define DISPLAY_PORT_RX_7 135142 143#define LPASS_CLK_ID_PRI_MI2S_IBIT 1144#define LPASS_CLK_ID_PRI_MI2S_EBIT 2145#define LPASS_CLK_ID_SEC_MI2S_IBIT 3146#define LPASS_CLK_ID_SEC_MI2S_EBIT 4147#define LPASS_CLK_ID_TER_MI2S_IBIT 5148#define LPASS_CLK_ID_TER_MI2S_EBIT 6149#define LPASS_CLK_ID_QUAD_MI2S_IBIT 7150#define LPASS_CLK_ID_QUAD_MI2S_EBIT 8151#define LPASS_CLK_ID_SPEAKER_I2S_IBIT 9152#define LPASS_CLK_ID_SPEAKER_I2S_EBIT 10153#define LPASS_CLK_ID_SPEAKER_I2S_OSR 11154#define LPASS_CLK_ID_QUI_MI2S_IBIT 12155#define LPASS_CLK_ID_QUI_MI2S_EBIT 13156#define LPASS_CLK_ID_SEN_MI2S_IBIT 14157#define LPASS_CLK_ID_SEN_MI2S_EBIT 15158#define LPASS_CLK_ID_INT0_MI2S_IBIT 16159#define LPASS_CLK_ID_INT1_MI2S_IBIT 17160#define LPASS_CLK_ID_INT2_MI2S_IBIT 18161#define LPASS_CLK_ID_INT3_MI2S_IBIT 19162#define LPASS_CLK_ID_INT4_MI2S_IBIT 20163#define LPASS_CLK_ID_INT5_MI2S_IBIT 21164#define LPASS_CLK_ID_INT6_MI2S_IBIT 22165#define LPASS_CLK_ID_QUI_MI2S_OSR 23166#define LPASS_CLK_ID_PRI_PCM_IBIT 24167#define LPASS_CLK_ID_PRI_PCM_EBIT 25168#define LPASS_CLK_ID_SEC_PCM_IBIT 26169#define LPASS_CLK_ID_SEC_PCM_EBIT 27170#define LPASS_CLK_ID_TER_PCM_IBIT 28171#define LPASS_CLK_ID_TER_PCM_EBIT 29172#define LPASS_CLK_ID_QUAD_PCM_IBIT 30173#define LPASS_CLK_ID_QUAD_PCM_EBIT 31174#define LPASS_CLK_ID_QUIN_PCM_IBIT 32175#define LPASS_CLK_ID_QUIN_PCM_EBIT 33176#define LPASS_CLK_ID_QUI_PCM_OSR 34177#define LPASS_CLK_ID_PRI_TDM_IBIT 35178#define LPASS_CLK_ID_PRI_TDM_EBIT 36179#define LPASS_CLK_ID_SEC_TDM_IBIT 37180#define LPASS_CLK_ID_SEC_TDM_EBIT 38181#define LPASS_CLK_ID_TER_TDM_IBIT 39182#define LPASS_CLK_ID_TER_TDM_EBIT 40183#define LPASS_CLK_ID_QUAD_TDM_IBIT 41184#define LPASS_CLK_ID_QUAD_TDM_EBIT 42185#define LPASS_CLK_ID_QUIN_TDM_IBIT 43186#define LPASS_CLK_ID_QUIN_TDM_EBIT 44187#define LPASS_CLK_ID_QUIN_TDM_OSR 45188#define LPASS_CLK_ID_MCLK_1 46189#define LPASS_CLK_ID_MCLK_2 47190#define LPASS_CLK_ID_MCLK_3 48191#define LPASS_CLK_ID_MCLK_4 49192#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 50193#define LPASS_CLK_ID_INT_MCLK_0 51194#define LPASS_CLK_ID_INT_MCLK_1 52195#define LPASS_CLK_ID_MCLK_5 53196#define LPASS_CLK_ID_WSA_CORE_MCLK 54197#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55198#define LPASS_CLK_ID_VA_CORE_MCLK 56199#define LPASS_CLK_ID_TX_CORE_MCLK 57200#define LPASS_CLK_ID_TX_CORE_NPL_MCLK 58201#define LPASS_CLK_ID_RX_CORE_MCLK 59202#define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60203#define LPASS_CLK_ID_VA_CORE_2X_MCLK 61204/* Clock ID for MCLK for WSA2 core */205#define LPASS_CLK_ID_WSA2_CORE_MCLK 62206/* Clock ID for NPL MCLK for WSA2 core */207#define LPASS_CLK_ID_WSA2_CORE_2X_MCLK 63208/* Clock ID for RX Core TX MCLK */209#define LPASS_CLK_ID_RX_CORE_TX_MCLK 64210/* Clock ID for RX CORE TX 2X MCLK */211#define LPASS_CLK_ID_RX_CORE_TX_2X_MCLK 65212/* Clock ID for WSA core TX MCLK */213#define LPASS_CLK_ID_WSA_CORE_TX_MCLK 66214/* Clock ID for WSA core TX 2X MCLK */215#define LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK 67216/* Clock ID for WSA2 core TX MCLK */217#define LPASS_CLK_ID_WSA2_CORE_TX_MCLK 68218/* Clock ID for WSA2 core TX 2X MCLK */219#define LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK 69220/* Clock ID for RX CORE MCLK2 2X MCLK */221#define LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK 70222 223#define LPASS_HW_AVTIMER_VOTE 101224#define LPASS_HW_MACRO_VOTE 102225#define LPASS_HW_DCODEC_VOTE 103226 227#define Q6AFE_MAX_CLK_ID 104228 229#define LPASS_CLK_ATTRIBUTE_INVALID 0x0230#define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1231#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2232#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3233 234#endif /* __DT_BINDINGS_Q6_AUDIO_PORTS_H__ */235