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1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * Copyright (C) 2018 Oleksij Rempel <linux@rempel-privat.de>4 *5 * Driver for Alcor Micro AU6601 and AU6621 controllers6 */7 8#ifndef __ALCOR_PCI_H9#define __ALCOR_PCI_H10 11#define ALCOR_SD_CARD 012#define ALCOR_MS_CARD 113 14#define DRV_NAME_ALCOR_PCI_SDMMC "alcor_sdmmc"15#define DRV_NAME_ALCOR_PCI_MS "alcor_ms"16 17#define PCI_ID_ALCOR_MICRO 0x1AEA18#define PCI_ID_AU6601 0x660119#define PCI_ID_AU6621 0x662120#define PCI_ID_AU6625 0x662521 22#define MHZ_TO_HZ(freq) ((freq) * 1000 * 1000)23 24#define AU6601_BASE_CLOCK 3100000025#define AU6601_MIN_CLOCK 15000026#define AU6601_MAX_CLOCK 20800000027#define AU6601_MAX_DMA_SEGMENTS 6428#define AU6601_MAX_PIO_SEGMENTS 129#define AU6601_MAX_DMA_BLOCK_SIZE 0x100030#define AU6601_MAX_PIO_BLOCK_SIZE 0x20031#define AU6601_MAX_DMA_BLOCKS 132#define AU6601_DMA_LOCAL_SEGMENTS 133 34/* registers spotter by reverse engineering but still35 * with unknown functionality:36 * 0x10 - ADMA phy address. AU6621 only?37 * 0x51 - LED ctrl?38 * 0x52 - unknown39 * 0x61 - LED related? Always toggled BIT040 * 0x63 - Same as 0x61?41 * 0x77 - unknown42 */43 44/* SDMA phy address. Higher then 0x0800.0000?45 * The au6601 and au6621 have different DMA engines with different issues. One46 * For example au6621 engine is triggered by addr change. No other interaction47 * is needed. This means, if we get two buffers with same address, then engine48 * will stall.49 */50#define AU6601_REG_SDMA_ADDR 0x0051#define AU6601_SDMA_MASK 0xffffffff52 53#define AU6601_DMA_BOUNDARY 0x0554#define AU6621_DMA_PAGE_CNT 0x0555/* PIO */56#define AU6601_REG_BUFFER 0x0857/* ADMA ctrl? AU6621 only. */58#define AU6621_DMA_CTRL 0x0c59#define AU6621_DMA_ENABLE BIT(0)60/* CMD index */61#define AU6601_REG_CMD_OPCODE 0x2362/* CMD parametr */63#define AU6601_REG_CMD_ARG 0x2464/* CMD response 4x4 Bytes */65#define AU6601_REG_CMD_RSP0 0x3066#define AU6601_REG_CMD_RSP1 0x3467#define AU6601_REG_CMD_RSP2 0x3868#define AU6601_REG_CMD_RSP3 0x3C69/* default timeout set to 125: 125 * 40ms = 5 sec70 * how exactly it is calculated?71 */72#define AU6601_TIME_OUT_CTRL 0x6973/* Block size for SDMA or PIO */74#define AU6601_REG_BLOCK_SIZE 0x6c75/* Some power related reg, used together with AU6601_OUTPUT_ENABLE */76#define AU6601_POWER_CONTROL 0x7077 78/* PLL ctrl */79#define AU6601_CLK_SELECT 0x7280#define AU6601_CLK_OVER_CLK 0x8081#define AU6601_CLK_384_MHZ 0x3082#define AU6601_CLK_125_MHZ 0x2083#define AU6601_CLK_48_MHZ 0x1084#define AU6601_CLK_EXT_PLL 0x0485#define AU6601_CLK_X2_MODE 0x0286#define AU6601_CLK_ENABLE 0x0187#define AU6601_CLK_31_25_MHZ 0x0088 89#define AU6601_CLK_DIVIDER 0x7390 91#define AU6601_INTERFACE_MODE_CTRL 0x7492#define AU6601_DLINK_MODE 0x8093#define AU6601_INTERRUPT_DELAY_TIME 0x4094#define AU6601_SIGNAL_REQ_CTRL 0x3095#define AU6601_MS_CARD_WP BIT(3)96#define AU6601_SD_CARD_WP BIT(0)97 98/* same register values are used for:99 * - AU6601_OUTPUT_ENABLE100 * - AU6601_POWER_CONTROL101 */102#define AU6601_ACTIVE_CTRL 0x75103#define AU6601_XD_CARD BIT(4)104/* AU6601_MS_CARD_ACTIVE - will cativate MS card section? */105#define AU6601_MS_CARD BIT(3)106#define AU6601_SD_CARD BIT(0)107 108/* card slot state. It should automatically detect type of109 * the card110 */111#define AU6601_DETECT_STATUS 0x76112#define AU6601_DETECT_EN BIT(7)113#define AU6601_MS_DETECTED BIT(3)114#define AU6601_SD_DETECTED BIT(0)115#define AU6601_DETECT_STATUS_M 0xf116 117#define AU6601_REG_SW_RESET 0x79118#define AU6601_BUF_CTRL_RESET BIT(7)119#define AU6601_RESET_DATA BIT(3)120#define AU6601_RESET_CMD BIT(0)121 122#define AU6601_OUTPUT_ENABLE 0x7a123 124#define AU6601_PAD_DRIVE0 0x7b125#define AU6601_PAD_DRIVE1 0x7c126#define AU6601_PAD_DRIVE2 0x7d127/* read EEPROM? */128#define AU6601_FUNCTION 0x7f129 130#define AU6601_CMD_XFER_CTRL 0x81131#define AU6601_CMD_17_BYTE_CRC 0xc0132#define AU6601_CMD_6_BYTE_WO_CRC 0x80133#define AU6601_CMD_6_BYTE_CRC 0x40134#define AU6601_CMD_START_XFER 0x20135#define AU6601_CMD_STOP_WAIT_RDY 0x10136#define AU6601_CMD_NO_RESP 0x00137 138#define AU6601_REG_BUS_CTRL 0x82139#define AU6601_BUS_WIDTH_4BIT 0x20140#define AU6601_BUS_WIDTH_8BIT 0x10141#define AU6601_BUS_WIDTH_1BIT 0x00142 143#define AU6601_DATA_XFER_CTRL 0x83144#define AU6601_DATA_WRITE BIT(7)145#define AU6601_DATA_DMA_MODE BIT(6)146#define AU6601_DATA_START_XFER BIT(0)147 148#define AU6601_DATA_PIN_STATE 0x84149#define AU6601_BUS_STAT_CMD BIT(15)150/* BIT(4) - BIT(7) are permanently 1.151 * May be reserved or not attached DAT4-DAT7152 */153#define AU6601_BUS_STAT_DAT3 BIT(3)154#define AU6601_BUS_STAT_DAT2 BIT(2)155#define AU6601_BUS_STAT_DAT1 BIT(1)156#define AU6601_BUS_STAT_DAT0 BIT(0)157#define AU6601_BUS_STAT_DAT_MASK 0xf158 159#define AU6601_OPT 0x85160#define AU6601_OPT_CMD_LINE_LEVEL 0x80161#define AU6601_OPT_NCRC_16_CLK BIT(4)162#define AU6601_OPT_CMD_NWT BIT(3)163#define AU6601_OPT_STOP_CLK BIT(2)164#define AU6601_OPT_DDR_MODE BIT(1)165#define AU6601_OPT_SD_18V BIT(0)166 167#define AU6601_CLK_DELAY 0x86168#define AU6601_CLK_DATA_POSITIVE_EDGE 0x80169#define AU6601_CLK_CMD_POSITIVE_EDGE 0x40170#define AU6601_CLK_POSITIVE_EDGE_ALL (AU6601_CLK_CMD_POSITIVE_EDGE \171 | AU6601_CLK_DATA_POSITIVE_EDGE)172 173 174#define AU6601_REG_INT_STATUS 0x90175#define AU6601_REG_INT_ENABLE 0x94176#define AU6601_INT_DATA_END_BIT_ERR BIT(22)177#define AU6601_INT_DATA_CRC_ERR BIT(21)178#define AU6601_INT_DATA_TIMEOUT_ERR BIT(20)179#define AU6601_INT_CMD_INDEX_ERR BIT(19)180#define AU6601_INT_CMD_END_BIT_ERR BIT(18)181#define AU6601_INT_CMD_CRC_ERR BIT(17)182#define AU6601_INT_CMD_TIMEOUT_ERR BIT(16)183#define AU6601_INT_ERROR BIT(15)184#define AU6601_INT_OVER_CURRENT_ERR BIT(8)185#define AU6601_INT_CARD_INSERT BIT(7)186#define AU6601_INT_CARD_REMOVE BIT(6)187#define AU6601_INT_READ_BUF_RDY BIT(5)188#define AU6601_INT_WRITE_BUF_RDY BIT(4)189#define AU6601_INT_DMA_END BIT(3)190#define AU6601_INT_DATA_END BIT(1)191#define AU6601_INT_CMD_END BIT(0)192 193#define AU6601_INT_NORMAL_MASK 0x00007FFF194#define AU6601_INT_ERROR_MASK 0xFFFF8000195 196#define AU6601_INT_CMD_MASK (AU6601_INT_CMD_END | \197 AU6601_INT_CMD_TIMEOUT_ERR | AU6601_INT_CMD_CRC_ERR | \198 AU6601_INT_CMD_END_BIT_ERR | AU6601_INT_CMD_INDEX_ERR)199#define AU6601_INT_DATA_MASK (AU6601_INT_DATA_END | AU6601_INT_DMA_END | \200 AU6601_INT_READ_BUF_RDY | AU6601_INT_WRITE_BUF_RDY | \201 AU6601_INT_DATA_TIMEOUT_ERR | AU6601_INT_DATA_CRC_ERR | \202 AU6601_INT_DATA_END_BIT_ERR)203#define AU6601_INT_ALL_MASK ((u32)-1)204 205/* MS_CARD mode registers */206 207#define AU6601_MS_STATUS 0xa0208 209#define AU6601_MS_BUS_MODE_CTRL 0xa1210#define AU6601_MS_BUS_8BIT_MODE 0x03211#define AU6601_MS_BUS_4BIT_MODE 0x01212#define AU6601_MS_BUS_1BIT_MODE 0x00213 214#define AU6601_MS_TPC_CMD 0xa2215#define AU6601_MS_TPC_READ_PAGE_DATA 0x02216#define AU6601_MS_TPC_READ_REG 0x04217#define AU6601_MS_TPC_GET_INT 0x07218#define AU6601_MS_TPC_WRITE_PAGE_DATA 0x0D219#define AU6601_MS_TPC_WRITE_REG 0x0B220#define AU6601_MS_TPC_SET_RW_REG_ADRS 0x08221#define AU6601_MS_TPC_SET_CMD 0x0E222#define AU6601_MS_TPC_EX_SET_CMD 0x09223#define AU6601_MS_TPC_READ_SHORT_DATA 0x03224#define AU6601_MS_TPC_WRITE_SHORT_DATA 0x0C225 226#define AU6601_MS_TRANSFER_MODE 0xa3227#define AU6601_MS_XFER_INT_TIMEOUT_CHK BIT(2)228#define AU6601_MS_XFER_DMA_ENABLE BIT(1)229#define AU6601_MS_XFER_START BIT(0)230 231#define AU6601_MS_DATA_PIN_STATE 0xa4232 233#define AU6601_MS_INT_STATUS 0xb0234#define AU6601_MS_INT_ENABLE 0xb4235#define AU6601_MS_INT_OVER_CURRENT_ERROR BIT(23)236#define AU6601_MS_INT_DATA_CRC_ERROR BIT(21)237#define AU6601_MS_INT_INT_TIMEOUT BIT(20)238#define AU6601_MS_INT_INT_RESP_ERROR BIT(19)239#define AU6601_MS_INT_CED_ERROR BIT(18)240#define AU6601_MS_INT_TPC_TIMEOUT BIT(16)241#define AU6601_MS_INT_ERROR BIT(15)242#define AU6601_MS_INT_CARD_INSERT BIT(7)243#define AU6601_MS_INT_CARD_REMOVE BIT(6)244#define AU6601_MS_INT_BUF_READ_RDY BIT(5)245#define AU6601_MS_INT_BUF_WRITE_RDY BIT(4)246#define AU6601_MS_INT_DMA_END BIT(3)247#define AU6601_MS_INT_TPC_END BIT(1)248 249#define AU6601_MS_INT_DATA_MASK 0x00000038250#define AU6601_MS_INT_TPC_MASK 0x003d8002251#define AU6601_MS_INT_TPC_ERROR 0x003d0000252 253#define ALCOR_PCIE_LINK_CTRL_OFFSET 0x10254#define ALCOR_PCIE_LINK_CAP_OFFSET 0x0c255#define ALCOR_CAP_START_OFFSET 0x34256 257struct alcor_dev_cfg {258 u8 dma;259};260 261struct alcor_pci_priv {262 struct pci_dev *pdev;263 struct pci_dev *parent_pdev;264 struct device *dev;265 void __iomem *iobase;266 unsigned int irq;267 268 unsigned long id; /* idr id */269 270 struct alcor_dev_cfg *cfg;271};272 273void alcor_write8(struct alcor_pci_priv *priv, u8 val, unsigned int addr);274void alcor_write16(struct alcor_pci_priv *priv, u16 val, unsigned int addr);275void alcor_write32(struct alcor_pci_priv *priv, u32 val, unsigned int addr);276void alcor_write32be(struct alcor_pci_priv *priv, u32 val, unsigned int addr);277u8 alcor_read8(struct alcor_pci_priv *priv, unsigned int addr);278u32 alcor_read32(struct alcor_pci_priv *priv, unsigned int addr);279u32 alcor_read32be(struct alcor_pci_priv *priv, unsigned int addr);280#endif281