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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * CCI cache coherent interconnect support4 *5 * Copyright (C) 2013 ARM Ltd.6 */7 8#ifndef __LINUX_ARM_CCI_H9#define __LINUX_ARM_CCI_H10 11#include <linux/errno.h>12#include <linux/types.h>13 14#include <asm/arm-cci.h>15 16struct device_node;17 18#ifdef CONFIG_ARM_CCI19extern bool cci_probed(void);20#else21static inline bool cci_probed(void) { return false; }22#endif23 24#ifdef CONFIG_ARM_CCI400_PORT_CTRL25extern int cci_ace_get_port(struct device_node *dn);26extern int cci_disable_port_by_cpu(u64 mpidr);27extern int __cci_control_port_by_device(struct device_node *dn, bool enable);28extern int __cci_control_port_by_index(u32 port, bool enable);29#else30static inline int cci_ace_get_port(struct device_node *dn)31{32 return -ENODEV;33}34static inline int cci_disable_port_by_cpu(u64 mpidr) { return -ENODEV; }35static inline int __cci_control_port_by_device(struct device_node *dn,36 bool enable)37{38 return -ENODEV;39}40static inline int __cci_control_port_by_index(u32 port, bool enable)41{42 return -ENODEV;43}44#endif45 46void cci_enable_port_for_self(void);47 48#define cci_disable_port_by_device(dev) \49 __cci_control_port_by_device(dev, false)50#define cci_enable_port_by_device(dev) \51 __cci_control_port_by_device(dev, true)52#define cci_disable_port_by_index(dev) \53 __cci_control_port_by_index(dev, false)54#define cci_enable_port_by_index(dev) \55 __cci_control_port_by_index(dev, true)56 57#endif58