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1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef __INCLUDE_ATMEL_SSC_H3#define __INCLUDE_ATMEL_SSC_H4 5#include <linux/platform_device.h>6#include <linux/list.h>7#include <linux/io.h>8 9struct atmel_ssc_platform_data {10 int use_dma;11 int has_fslen_ext;12};13 14struct ssc_device {15 struct list_head list;16 dma_addr_t phybase;17 void __iomem *regs;18 struct platform_device *pdev;19 struct atmel_ssc_platform_data *pdata;20 struct clk *clk;21 int user;22 int irq;23 bool clk_from_rk_pin;24 bool sound_dai;25};26 27struct ssc_device * __must_check ssc_request(unsigned int ssc_num);28void ssc_free(struct ssc_device *ssc);29 30/* SSC register offsets */31 32/* SSC Control Register */33#define SSC_CR 0x0000000034#define SSC_CR_RXDIS_SIZE 135#define SSC_CR_RXDIS_OFFSET 136#define SSC_CR_RXEN_SIZE 137#define SSC_CR_RXEN_OFFSET 038#define SSC_CR_SWRST_SIZE 139#define SSC_CR_SWRST_OFFSET 1540#define SSC_CR_TXDIS_SIZE 141#define SSC_CR_TXDIS_OFFSET 942#define SSC_CR_TXEN_SIZE 143#define SSC_CR_TXEN_OFFSET 844 45/* SSC Clock Mode Register */46#define SSC_CMR 0x0000000447#define SSC_CMR_DIV_SIZE 1248#define SSC_CMR_DIV_OFFSET 049 50/* SSC Receive Clock Mode Register */51#define SSC_RCMR 0x0000001052#define SSC_RCMR_CKG_SIZE 253#define SSC_RCMR_CKG_OFFSET 654#define SSC_RCMR_CKI_SIZE 155#define SSC_RCMR_CKI_OFFSET 556#define SSC_RCMR_CKO_SIZE 357#define SSC_RCMR_CKO_OFFSET 258#define SSC_RCMR_CKS_SIZE 259#define SSC_RCMR_CKS_OFFSET 060#define SSC_RCMR_PERIOD_SIZE 861#define SSC_RCMR_PERIOD_OFFSET 2462#define SSC_RCMR_START_SIZE 463#define SSC_RCMR_START_OFFSET 864#define SSC_RCMR_STOP_SIZE 165#define SSC_RCMR_STOP_OFFSET 1266#define SSC_RCMR_STTDLY_SIZE 867#define SSC_RCMR_STTDLY_OFFSET 1668 69/* SSC Receive Frame Mode Register */70#define SSC_RFMR 0x0000001471#define SSC_RFMR_DATLEN_SIZE 572#define SSC_RFMR_DATLEN_OFFSET 073#define SSC_RFMR_DATNB_SIZE 474#define SSC_RFMR_DATNB_OFFSET 875#define SSC_RFMR_FSEDGE_SIZE 176#define SSC_RFMR_FSEDGE_OFFSET 2477/*78 * The FSLEN_EXT exist on at91sam9rl, at91sam9g10,79 * at91sam9g20, and at91sam9g45 and newer SoCs80 */81#define SSC_RFMR_FSLEN_EXT_SIZE 482#define SSC_RFMR_FSLEN_EXT_OFFSET 2883#define SSC_RFMR_FSLEN_SIZE 484#define SSC_RFMR_FSLEN_OFFSET 1685#define SSC_RFMR_FSOS_SIZE 486#define SSC_RFMR_FSOS_OFFSET 2087#define SSC_RFMR_LOOP_SIZE 188#define SSC_RFMR_LOOP_OFFSET 589#define SSC_RFMR_MSBF_SIZE 190#define SSC_RFMR_MSBF_OFFSET 791 92/* SSC Transmit Clock Mode Register */93#define SSC_TCMR 0x0000001894#define SSC_TCMR_CKG_SIZE 295#define SSC_TCMR_CKG_OFFSET 696#define SSC_TCMR_CKI_SIZE 197#define SSC_TCMR_CKI_OFFSET 598#define SSC_TCMR_CKO_SIZE 399#define SSC_TCMR_CKO_OFFSET 2100#define SSC_TCMR_CKS_SIZE 2101#define SSC_TCMR_CKS_OFFSET 0102#define SSC_TCMR_PERIOD_SIZE 8103#define SSC_TCMR_PERIOD_OFFSET 24104#define SSC_TCMR_START_SIZE 4105#define SSC_TCMR_START_OFFSET 8106#define SSC_TCMR_STTDLY_SIZE 8107#define SSC_TCMR_STTDLY_OFFSET 16108 109/* SSC Transmit Frame Mode Register */110#define SSC_TFMR 0x0000001c111#define SSC_TFMR_DATDEF_SIZE 1112#define SSC_TFMR_DATDEF_OFFSET 5113#define SSC_TFMR_DATLEN_SIZE 5114#define SSC_TFMR_DATLEN_OFFSET 0115#define SSC_TFMR_DATNB_SIZE 4116#define SSC_TFMR_DATNB_OFFSET 8117#define SSC_TFMR_FSDEN_SIZE 1118#define SSC_TFMR_FSDEN_OFFSET 23119#define SSC_TFMR_FSEDGE_SIZE 1120#define SSC_TFMR_FSEDGE_OFFSET 24121/*122 * The FSLEN_EXT exist on at91sam9rl, at91sam9g10,123 * at91sam9g20, and at91sam9g45 and newer SoCs124 */125#define SSC_TFMR_FSLEN_EXT_SIZE 4126#define SSC_TFMR_FSLEN_EXT_OFFSET 28127#define SSC_TFMR_FSLEN_SIZE 4128#define SSC_TFMR_FSLEN_OFFSET 16129#define SSC_TFMR_FSOS_SIZE 3130#define SSC_TFMR_FSOS_OFFSET 20131#define SSC_TFMR_MSBF_SIZE 1132#define SSC_TFMR_MSBF_OFFSET 7133 134/* SSC Receive Hold Register */135#define SSC_RHR 0x00000020136#define SSC_RHR_RDAT_SIZE 32137#define SSC_RHR_RDAT_OFFSET 0138 139/* SSC Transmit Hold Register */140#define SSC_THR 0x00000024141#define SSC_THR_TDAT_SIZE 32142#define SSC_THR_TDAT_OFFSET 0143 144/* SSC Receive Sync. Holding Register */145#define SSC_RSHR 0x00000030146#define SSC_RSHR_RSDAT_SIZE 16147#define SSC_RSHR_RSDAT_OFFSET 0148 149/* SSC Transmit Sync. Holding Register */150#define SSC_TSHR 0x00000034151#define SSC_TSHR_TSDAT_SIZE 16152#define SSC_TSHR_RSDAT_OFFSET 0153 154/* SSC Receive Compare 0 Register */155#define SSC_RC0R 0x00000038156#define SSC_RC0R_CP0_SIZE 16157#define SSC_RC0R_CP0_OFFSET 0158 159/* SSC Receive Compare 1 Register */160#define SSC_RC1R 0x0000003c161#define SSC_RC1R_CP1_SIZE 16162#define SSC_RC1R_CP1_OFFSET 0163 164/* SSC Status Register */165#define SSC_SR 0x00000040166#define SSC_SR_CP0_SIZE 1167#define SSC_SR_CP0_OFFSET 8168#define SSC_SR_CP1_SIZE 1169#define SSC_SR_CP1_OFFSET 9170#define SSC_SR_ENDRX_SIZE 1171#define SSC_SR_ENDRX_OFFSET 6172#define SSC_SR_ENDTX_SIZE 1173#define SSC_SR_ENDTX_OFFSET 2174#define SSC_SR_OVRUN_SIZE 1175#define SSC_SR_OVRUN_OFFSET 5176#define SSC_SR_RXBUFF_SIZE 1177#define SSC_SR_RXBUFF_OFFSET 7178#define SSC_SR_RXEN_SIZE 1179#define SSC_SR_RXEN_OFFSET 17180#define SSC_SR_RXRDY_SIZE 1181#define SSC_SR_RXRDY_OFFSET 4182#define SSC_SR_RXSYN_SIZE 1183#define SSC_SR_RXSYN_OFFSET 11184#define SSC_SR_TXBUFE_SIZE 1185#define SSC_SR_TXBUFE_OFFSET 3186#define SSC_SR_TXEMPTY_SIZE 1187#define SSC_SR_TXEMPTY_OFFSET 1188#define SSC_SR_TXEN_SIZE 1189#define SSC_SR_TXEN_OFFSET 16190#define SSC_SR_TXRDY_SIZE 1191#define SSC_SR_TXRDY_OFFSET 0192#define SSC_SR_TXSYN_SIZE 1193#define SSC_SR_TXSYN_OFFSET 10194 195/* SSC Interrupt Enable Register */196#define SSC_IER 0x00000044197#define SSC_IER_CP0_SIZE 1198#define SSC_IER_CP0_OFFSET 8199#define SSC_IER_CP1_SIZE 1200#define SSC_IER_CP1_OFFSET 9201#define SSC_IER_ENDRX_SIZE 1202#define SSC_IER_ENDRX_OFFSET 6203#define SSC_IER_ENDTX_SIZE 1204#define SSC_IER_ENDTX_OFFSET 2205#define SSC_IER_OVRUN_SIZE 1206#define SSC_IER_OVRUN_OFFSET 5207#define SSC_IER_RXBUFF_SIZE 1208#define SSC_IER_RXBUFF_OFFSET 7209#define SSC_IER_RXRDY_SIZE 1210#define SSC_IER_RXRDY_OFFSET 4211#define SSC_IER_RXSYN_SIZE 1212#define SSC_IER_RXSYN_OFFSET 11213#define SSC_IER_TXBUFE_SIZE 1214#define SSC_IER_TXBUFE_OFFSET 3215#define SSC_IER_TXEMPTY_SIZE 1216#define SSC_IER_TXEMPTY_OFFSET 1217#define SSC_IER_TXRDY_SIZE 1218#define SSC_IER_TXRDY_OFFSET 0219#define SSC_IER_TXSYN_SIZE 1220#define SSC_IER_TXSYN_OFFSET 10221 222/* SSC Interrupt Disable Register */223#define SSC_IDR 0x00000048224#define SSC_IDR_CP0_SIZE 1225#define SSC_IDR_CP0_OFFSET 8226#define SSC_IDR_CP1_SIZE 1227#define SSC_IDR_CP1_OFFSET 9228#define SSC_IDR_ENDRX_SIZE 1229#define SSC_IDR_ENDRX_OFFSET 6230#define SSC_IDR_ENDTX_SIZE 1231#define SSC_IDR_ENDTX_OFFSET 2232#define SSC_IDR_OVRUN_SIZE 1233#define SSC_IDR_OVRUN_OFFSET 5234#define SSC_IDR_RXBUFF_SIZE 1235#define SSC_IDR_RXBUFF_OFFSET 7236#define SSC_IDR_RXRDY_SIZE 1237#define SSC_IDR_RXRDY_OFFSET 4238#define SSC_IDR_RXSYN_SIZE 1239#define SSC_IDR_RXSYN_OFFSET 11240#define SSC_IDR_TXBUFE_SIZE 1241#define SSC_IDR_TXBUFE_OFFSET 3242#define SSC_IDR_TXEMPTY_SIZE 1243#define SSC_IDR_TXEMPTY_OFFSET 1244#define SSC_IDR_TXRDY_SIZE 1245#define SSC_IDR_TXRDY_OFFSET 0246#define SSC_IDR_TXSYN_SIZE 1247#define SSC_IDR_TXSYN_OFFSET 10248 249/* SSC Interrupt Mask Register */250#define SSC_IMR 0x0000004c251#define SSC_IMR_CP0_SIZE 1252#define SSC_IMR_CP0_OFFSET 8253#define SSC_IMR_CP1_SIZE 1254#define SSC_IMR_CP1_OFFSET 9255#define SSC_IMR_ENDRX_SIZE 1256#define SSC_IMR_ENDRX_OFFSET 6257#define SSC_IMR_ENDTX_SIZE 1258#define SSC_IMR_ENDTX_OFFSET 2259#define SSC_IMR_OVRUN_SIZE 1260#define SSC_IMR_OVRUN_OFFSET 5261#define SSC_IMR_RXBUFF_SIZE 1262#define SSC_IMR_RXBUFF_OFFSET 7263#define SSC_IMR_RXRDY_SIZE 1264#define SSC_IMR_RXRDY_OFFSET 4265#define SSC_IMR_RXSYN_SIZE 1266#define SSC_IMR_RXSYN_OFFSET 11267#define SSC_IMR_TXBUFE_SIZE 1268#define SSC_IMR_TXBUFE_OFFSET 3269#define SSC_IMR_TXEMPTY_SIZE 1270#define SSC_IMR_TXEMPTY_OFFSET 1271#define SSC_IMR_TXRDY_SIZE 1272#define SSC_IMR_TXRDY_OFFSET 0273#define SSC_IMR_TXSYN_SIZE 1274#define SSC_IMR_TXSYN_OFFSET 10275 276/* SSC PDC Receive Pointer Register */277#define SSC_PDC_RPR 0x00000100278 279/* SSC PDC Receive Counter Register */280#define SSC_PDC_RCR 0x00000104281 282/* SSC PDC Transmit Pointer Register */283#define SSC_PDC_TPR 0x00000108284 285/* SSC PDC Receive Next Pointer Register */286#define SSC_PDC_RNPR 0x00000110287 288/* SSC PDC Receive Next Counter Register */289#define SSC_PDC_RNCR 0x00000114290 291/* SSC PDC Transmit Counter Register */292#define SSC_PDC_TCR 0x0000010c293 294/* SSC PDC Transmit Next Pointer Register */295#define SSC_PDC_TNPR 0x00000118296 297/* SSC PDC Transmit Next Counter Register */298#define SSC_PDC_TNCR 0x0000011c299 300/* SSC PDC Transfer Control Register */301#define SSC_PDC_PTCR 0x00000120302#define SSC_PDC_PTCR_RXTDIS_SIZE 1303#define SSC_PDC_PTCR_RXTDIS_OFFSET 1304#define SSC_PDC_PTCR_RXTEN_SIZE 1305#define SSC_PDC_PTCR_RXTEN_OFFSET 0306#define SSC_PDC_PTCR_TXTDIS_SIZE 1307#define SSC_PDC_PTCR_TXTDIS_OFFSET 9308#define SSC_PDC_PTCR_TXTEN_SIZE 1309#define SSC_PDC_PTCR_TXTEN_OFFSET 8310 311/* SSC PDC Transfer Status Register */312#define SSC_PDC_PTSR 0x00000124313#define SSC_PDC_PTSR_RXTEN_SIZE 1314#define SSC_PDC_PTSR_RXTEN_OFFSET 0315#define SSC_PDC_PTSR_TXTEN_SIZE 1316#define SSC_PDC_PTSR_TXTEN_OFFSET 8317 318/* Bit manipulation macros */319#define SSC_BIT(name) \320 (1 << SSC_##name##_OFFSET)321#define SSC_BF(name, value) \322 (((value) & ((1 << SSC_##name##_SIZE) - 1)) \323 << SSC_##name##_OFFSET)324#define SSC_BFEXT(name, value) \325 (((value) >> SSC_##name##_OFFSET) \326 & ((1 << SSC_##name##_SIZE) - 1))327#define SSC_BFINS(name, value, old) \328 (((old) & ~(((1 << SSC_##name##_SIZE) - 1) \329 << SSC_##name##_OFFSET)) | SSC_BF(name, value))330 331/* Register access macros */332#define ssc_readl(base, reg) __raw_readl(base + SSC_##reg)333#define ssc_writel(base, reg, value) __raw_writel((value), base + SSC_##reg)334 335#endif /* __INCLUDE_ATMEL_SSC_H */336