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1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef LINUX_BCMA_DRIVER_PCI_H_3#define LINUX_BCMA_DRIVER_PCI_H_4 5#include <linux/types.h>6 7struct pci_dev;8 9/** PCI core registers. **/10#define BCMA_CORE_PCI_CTL 0x0000 /* PCI Control */11#define BCMA_CORE_PCI_CTL_RST_OE 0x00000001 /* PCI_RESET Output Enable */12#define BCMA_CORE_PCI_CTL_RST 0x00000002 /* PCI_RESET driven out to pin */13#define BCMA_CORE_PCI_CTL_CLK_OE 0x00000004 /* Clock gate Output Enable */14#define BCMA_CORE_PCI_CTL_CLK 0x00000008 /* Gate for clock driven out to pin */15#define BCMA_CORE_PCI_ARBCTL 0x0010 /* PCI Arbiter Control */16#define BCMA_CORE_PCI_ARBCTL_INTERN 0x00000001 /* Use internal arbiter */17#define BCMA_CORE_PCI_ARBCTL_EXTERN 0x00000002 /* Use external arbiter */18#define BCMA_CORE_PCI_ARBCTL_PARKID 0x00000006 /* Mask, selects which agent is parked on an idle bus */19#define BCMA_CORE_PCI_ARBCTL_PARKID_LAST 0x00000000 /* Last requestor */20#define BCMA_CORE_PCI_ARBCTL_PARKID_4710 0x00000002 /* 4710 */21#define BCMA_CORE_PCI_ARBCTL_PARKID_EXT0 0x00000004 /* External requestor 0 */22#define BCMA_CORE_PCI_ARBCTL_PARKID_EXT1 0x00000006 /* External requestor 1 */23#define BCMA_CORE_PCI_ISTAT 0x0020 /* Interrupt status */24#define BCMA_CORE_PCI_ISTAT_INTA 0x00000001 /* PCI INTA# */25#define BCMA_CORE_PCI_ISTAT_INTB 0x00000002 /* PCI INTB# */26#define BCMA_CORE_PCI_ISTAT_SERR 0x00000004 /* PCI SERR# (write to clear) */27#define BCMA_CORE_PCI_ISTAT_PERR 0x00000008 /* PCI PERR# (write to clear) */28#define BCMA_CORE_PCI_ISTAT_PME 0x00000010 /* PCI PME# */29#define BCMA_CORE_PCI_IMASK 0x0024 /* Interrupt mask */30#define BCMA_CORE_PCI_IMASK_INTA 0x00000001 /* PCI INTA# */31#define BCMA_CORE_PCI_IMASK_INTB 0x00000002 /* PCI INTB# */32#define BCMA_CORE_PCI_IMASK_SERR 0x00000004 /* PCI SERR# */33#define BCMA_CORE_PCI_IMASK_PERR 0x00000008 /* PCI PERR# */34#define BCMA_CORE_PCI_IMASK_PME 0x00000010 /* PCI PME# */35#define BCMA_CORE_PCI_MBOX 0x0028 /* Backplane to PCI Mailbox */36#define BCMA_CORE_PCI_MBOX_F0_0 0x00000100 /* PCI function 0, INT 0 */37#define BCMA_CORE_PCI_MBOX_F0_1 0x00000200 /* PCI function 0, INT 1 */38#define BCMA_CORE_PCI_MBOX_F1_0 0x00000400 /* PCI function 1, INT 0 */39#define BCMA_CORE_PCI_MBOX_F1_1 0x00000800 /* PCI function 1, INT 1 */40#define BCMA_CORE_PCI_MBOX_F2_0 0x00001000 /* PCI function 2, INT 0 */41#define BCMA_CORE_PCI_MBOX_F2_1 0x00002000 /* PCI function 2, INT 1 */42#define BCMA_CORE_PCI_MBOX_F3_0 0x00004000 /* PCI function 3, INT 0 */43#define BCMA_CORE_PCI_MBOX_F3_1 0x00008000 /* PCI function 3, INT 1 */44#define BCMA_CORE_PCI_BCAST_ADDR 0x0050 /* Backplane Broadcast Address */45#define BCMA_CORE_PCI_BCAST_ADDR_MASK 0x000000FF46#define BCMA_CORE_PCI_BCAST_DATA 0x0054 /* Backplane Broadcast Data */47#define BCMA_CORE_PCI_GPIO_IN 0x0060 /* rev >= 2 only */48#define BCMA_CORE_PCI_GPIO_OUT 0x0064 /* rev >= 2 only */49#define BCMA_CORE_PCI_GPIO_ENABLE 0x0068 /* rev >= 2 only */50#define BCMA_CORE_PCI_GPIO_CTL 0x006C /* rev >= 2 only */51#define BCMA_CORE_PCI_SBTOPCI0 0x0100 /* Backplane to PCI translation 0 (sbtopci0) */52#define BCMA_CORE_PCI_SBTOPCI0_MASK 0xFC00000053#define BCMA_CORE_PCI_SBTOPCI1 0x0104 /* Backplane to PCI translation 1 (sbtopci1) */54#define BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC00000055#define BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */56#define BCMA_CORE_PCI_SBTOPCI2_MASK 0xC000000057#define BCMA_CORE_PCI_CONFIG_ADDR 0x0120 /* pcie config space access */58#define BCMA_CORE_PCI_CONFIG_DATA 0x0124 /* pcie config space access */59#define BCMA_CORE_PCI_MDIO_CONTROL 0x0128 /* controls the mdio access */60#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */61#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL 0x262#define BCMA_CORE_PCI_MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */63#define BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */64#define BCMA_CORE_PCI_MDIO_DATA 0x012c /* Data to the mdio access */65#define BCMA_CORE_PCI_MDIODATA_MASK 0x0000ffff /* data 2 bytes */66#define BCMA_CORE_PCI_MDIODATA_TA 0x00020000 /* Turnaround */67#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */68#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */69#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */70#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */71#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF 18 /* Regaddr shift */72#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */73#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */74#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */75#define BCMA_CORE_PCI_MDIODATA_WRITE 0x10000000 /* write Transaction */76#define BCMA_CORE_PCI_MDIODATA_READ 0x20000000 /* Read Transaction */77#define BCMA_CORE_PCI_MDIODATA_START 0x40000000 /* start of Transaction */78#define BCMA_CORE_PCI_MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */79#define BCMA_CORE_PCI_MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */80#define BCMA_CORE_PCI_MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */81#define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */82#define BCMA_CORE_PCI_MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */83#define BCMA_CORE_PCI_PCIEIND_ADDR 0x0130 /* indirect access to the internal register */84#define BCMA_CORE_PCI_PCIEIND_DATA 0x0134 /* Data to/from the internal register */85#define BCMA_CORE_PCI_CLKREQENCTRL 0x0138 /* >= rev 6, Clkreq rdma control */86#define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */87#define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */88#define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */89#define BCMA_CORE_PCI_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */90#define BCMA_CORE_PCI_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */91#define BCMA_CORE_PCI_SPROM_PI_OFFSET 0 /* first word */92#define BCMA_CORE_PCI_SPROM_PI_MASK 0xf000 /* bit 15:12 */93#define BCMA_CORE_PCI_SPROM_PI_SHIFT 12 /* bit 15:12 */94#define BCMA_CORE_PCI_SPROM_MISC_CONFIG 5 /* word 5 */95#define BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST 0x8000 /* bit 15 */96#define BCMA_CORE_PCI_SPROM_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */97#define BCMA_CORE_PCI_SPROM_CLKREQ_ENB 0x0800 /* bit 11 */98 99/* SBtoPCIx */100#define BCMA_CORE_PCI_SBTOPCI_MEM 0x00000000101#define BCMA_CORE_PCI_SBTOPCI_IO 0x00000001102#define BCMA_CORE_PCI_SBTOPCI_CFG0 0x00000002103#define BCMA_CORE_PCI_SBTOPCI_CFG1 0x00000003104#define BCMA_CORE_PCI_SBTOPCI_PREF 0x00000004 /* Prefetch enable */105#define BCMA_CORE_PCI_SBTOPCI_BURST 0x00000008 /* Burst enable */106#define BCMA_CORE_PCI_SBTOPCI_MRM 0x00000020 /* Memory Read Multiple */107#define BCMA_CORE_PCI_SBTOPCI_RC 0x00000030 /* Read Command mask (rev >= 11) */108#define BCMA_CORE_PCI_SBTOPCI_RC_READ 0x00000000 /* Memory read */109#define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */110#define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */111 112/* PCIE protocol PHY diagnostic registers */113#define BCMA_CORE_PCI_PLP_MODEREG 0x200 /* Mode */114#define BCMA_CORE_PCI_PLP_STATUSREG 0x204 /* Status */115#define BCMA_CORE_PCI_PLP_POLARITYINV_STAT 0x10 /* Status reg PCIE_PLP_STATUSREG */116#define BCMA_CORE_PCI_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */117#define BCMA_CORE_PCI_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */118#define BCMA_CORE_PCI_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */119#define BCMA_CORE_PCI_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */120#define BCMA_CORE_PCI_PLP_ATTNREG 0x218 /* Attention */121#define BCMA_CORE_PCI_PLP_ATTNMASKREG 0x21C /* Attention Mask */122#define BCMA_CORE_PCI_PLP_RXERRCTR 0x220 /* Rx Error */123#define BCMA_CORE_PCI_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */124#define BCMA_CORE_PCI_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */125#define BCMA_CORE_PCI_PLP_TESTCTRLREG 0x22C /* Test Control reg */126#define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */127#define BCMA_CORE_PCI_PLP_TIMINGOVRDREG 0x234 /* Timing param override */128#define BCMA_CORE_PCI_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */129#define BCMA_CORE_PCI_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */130 131/* PCIE protocol DLLP diagnostic registers */132#define BCMA_CORE_PCI_DLLP_LCREG 0x100 /* Link Control */133#define BCMA_CORE_PCI_DLLP_LSREG 0x104 /* Link Status */134#define BCMA_CORE_PCI_DLLP_LAREG 0x108 /* Link Attention */135#define BCMA_CORE_PCI_DLLP_LSREG_LINKUP (1 << 16)136#define BCMA_CORE_PCI_DLLP_LAMASKREG 0x10C /* Link Attention Mask */137#define BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */138#define BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */139#define BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */140#define BCMA_CORE_PCI_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */141#define BCMA_CORE_PCI_DLLP_LRREG 0x120 /* Link Replay */142#define BCMA_CORE_PCI_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */143#define BCMA_CORE_PCI_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */144#define BCMA_CORE_PCI_ASPMTIMER_EXTEND 0x01000000 /* > rev7: enable extend ASPM timer */145#define BCMA_CORE_PCI_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */146#define BCMA_CORE_PCI_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */147#define BCMA_CORE_PCI_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */148#define BCMA_CORE_PCI_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */149#define BCMA_CORE_PCI_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */150#define BCMA_CORE_PCI_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */151#define BCMA_CORE_PCI_DLLP_ERRCTRREG 0x144 /* Error Counter */152#define BCMA_CORE_PCI_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */153#define BCMA_CORE_PCI_DLLP_TESTREG 0x14C /* Test */154#define BCMA_CORE_PCI_DLLP_PKTBIST 0x150 /* Packet BIST */155#define BCMA_CORE_PCI_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */156 157/* SERDES RX registers */158#define BCMA_CORE_PCI_SERDES_RX_CTRL 1 /* Rx cntrl */159#define BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */160#define BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */161#define BCMA_CORE_PCI_SERDES_RX_TIMER1 2 /* Rx Timer1 */162#define BCMA_CORE_PCI_SERDES_RX_CDR 6 /* CDR */163#define BCMA_CORE_PCI_SERDES_RX_CDRBW 7 /* CDR BW */164 165/* SERDES PLL registers */166#define BCMA_CORE_PCI_SERDES_PLL_CTRL 1 /* PLL control reg */167#define BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */168 169/* PCIcore specific boardflags */170#define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */171 172/* PCIE Config space accessing MACROS */173#define BCMA_CORE_PCI_CFG_BUS_SHIFT 24 /* Bus shift */174#define BCMA_CORE_PCI_CFG_SLOT_SHIFT 19 /* Slot/Device shift */175#define BCMA_CORE_PCI_CFG_FUN_SHIFT 16 /* Function shift */176#define BCMA_CORE_PCI_CFG_OFF_SHIFT 0 /* Register shift */177 178#define BCMA_CORE_PCI_CFG_BUS_MASK 0xff /* Bus mask */179#define BCMA_CORE_PCI_CFG_SLOT_MASK 0x1f /* Slot/Device mask */180#define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */181#define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */182 183#define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8184 185#define BCMA_CORE_PCI_186 187/* MDIO devices (SERDES modules) */188#define BCMA_CORE_PCI_MDIO_IEEE0 0x000189#define BCMA_CORE_PCI_MDIO_IEEE1 0x001190#define BCMA_CORE_PCI_MDIO_BLK0 0x800191#define BCMA_CORE_PCI_MDIO_BLK1 0x801192#define BCMA_CORE_PCI_MDIO_BLK1_MGMT0 0x16193#define BCMA_CORE_PCI_MDIO_BLK1_MGMT1 0x17194#define BCMA_CORE_PCI_MDIO_BLK1_MGMT2 0x18195#define BCMA_CORE_PCI_MDIO_BLK1_MGMT3 0x19196#define BCMA_CORE_PCI_MDIO_BLK1_MGMT4 0x1A197#define BCMA_CORE_PCI_MDIO_BLK2 0x802198#define BCMA_CORE_PCI_MDIO_BLK3 0x803199#define BCMA_CORE_PCI_MDIO_BLK4 0x804200#define BCMA_CORE_PCI_MDIO_TXPLL 0x808 /* TXPLL register block idx */201#define BCMA_CORE_PCI_MDIO_TXCTRL0 0x820202#define BCMA_CORE_PCI_MDIO_SERDESID 0x831203#define BCMA_CORE_PCI_MDIO_RXCTRL0 0x840204 205/* PCIE Root Capability Register bits (Host mode only) */206#define BCMA_CORE_PCI_RC_RRS_VISIBILITY 0x0001207 208struct bcma_drv_pci;209struct bcma_bus;210 211#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE212struct bcma_drv_pci_host {213 struct bcma_drv_pci *pdev;214 215 u32 host_cfg_addr;216 spinlock_t cfgspace_lock;217 218 struct pci_controller pci_controller;219 struct pci_ops pci_ops;220 struct resource mem_resource;221 struct resource io_resource;222};223#endif224 225struct bcma_drv_pci {226 struct bcma_device *core;227 u8 early_setup_done:1;228 u8 setup_done:1;229 u8 hostmode:1;230 231#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE232 struct bcma_drv_pci_host *host_controller;233#endif234};235 236/* Register access */237#define pcicore_read16(pc, offset) bcma_read16((pc)->core, offset)238#define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset)239#define pcicore_write16(pc, offset, val) bcma_write16((pc)->core, offset, val)240#define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val)241 242#ifdef CONFIG_BCMA_DRIVER_PCI243extern void bcma_core_pci_power_save(struct bcma_bus *bus, bool up);244#else245static inline void bcma_core_pci_power_save(struct bcma_bus *bus, bool up)246{247}248#endif249 250#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE251extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);252extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);253#else254static inline int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev)255{256 return -ENOTSUPP;257}258static inline int bcma_core_pci_plat_dev_init(struct pci_dev *dev)259{260 return -ENOTSUPP;261}262#endif263 264#endif /* LINUX_BCMA_DRIVER_PCI_H_ */265