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1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef LINUX_BCMA_DRIVER_PCIE2_H_3#define LINUX_BCMA_DRIVER_PCIE2_H_4 5#define BCMA_CORE_PCIE2_CLK_CONTROL 0x00006#define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */7#define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */8#define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */9#define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x001010#define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */11#define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */12#define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */13#define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x000414#define BCMA_CORE_PCIE2_RC_PM_STATUS 0x000815#define BCMA_CORE_PCIE2_EP_PM_CONTROL 0x000C16#define BCMA_CORE_PCIE2_EP_PM_STATUS 0x001017#define BCMA_CORE_PCIE2_EP_LTR_CONTROL 0x001418#define BCMA_CORE_PCIE2_EP_LTR_STATUS 0x001819#define BCMA_CORE_PCIE2_EP_OBFF_STATUS 0x001C20#define BCMA_CORE_PCIE2_PCIE_ERR_STATUS 0x002021#define BCMA_CORE_PCIE2_RC_AXI_CONFIG 0x010022#define BCMA_CORE_PCIE2_EP_AXI_CONFIG 0x010423#define BCMA_CORE_PCIE2_RXDEBUG_STATUS0 0x010824#define BCMA_CORE_PCIE2_RXDEBUG_CONTROL0 0x010C25#define BCMA_CORE_PCIE2_CONFIGINDADDR 0x012026#define BCMA_CORE_PCIE2_CONFIGINDDATA 0x012427#define BCMA_CORE_PCIE2_MDIOCONTROL 0x012828#define BCMA_CORE_PCIE2_MDIOWRDATA 0x012C29#define BCMA_CORE_PCIE2_MDIORDDATA 0x013030#define BCMA_CORE_PCIE2_DATAINTF 0x018031#define BCMA_CORE_PCIE2_D2H_INTRLAZY_0 0x018832#define BCMA_CORE_PCIE2_H2D_INTRLAZY_0 0x018c33#define BCMA_CORE_PCIE2_H2D_INTSTAT_0 0x019034#define BCMA_CORE_PCIE2_H2D_INTMASK_0 0x019435#define BCMA_CORE_PCIE2_D2H_INTSTAT_0 0x019836#define BCMA_CORE_PCIE2_D2H_INTMASK_0 0x019c37#define BCMA_CORE_PCIE2_LTR_STATE 0x01A0 /* Latency Tolerance Reporting */38#define PCIE2_LTR_ACTIVE 239#define PCIE2_LTR_ACTIVE_IDLE 140#define PCIE2_LTR_SLEEP 041#define PCIE2_LTR_FINAL_MASK 0x30042#define PCIE2_LTR_FINAL_SHIFT 843#define BCMA_CORE_PCIE2_PWR_INT_STATUS 0x01A444#define BCMA_CORE_PCIE2_PWR_INT_MASK 0x01A845#define BCMA_CORE_PCIE2_CFG_ADDR 0x01F846#define BCMA_CORE_PCIE2_CFG_DATA 0x01FC47#define BCMA_CORE_PCIE2_SYS_EQ_PAGE 0x020048#define BCMA_CORE_PCIE2_SYS_MSI_PAGE 0x020449#define BCMA_CORE_PCIE2_SYS_MSI_INTREN 0x020850#define BCMA_CORE_PCIE2_SYS_MSI_CTRL0 0x021051#define BCMA_CORE_PCIE2_SYS_MSI_CTRL1 0x021452#define BCMA_CORE_PCIE2_SYS_MSI_CTRL2 0x021853#define BCMA_CORE_PCIE2_SYS_MSI_CTRL3 0x021C54#define BCMA_CORE_PCIE2_SYS_MSI_CTRL4 0x022055#define BCMA_CORE_PCIE2_SYS_MSI_CTRL5 0x022456#define BCMA_CORE_PCIE2_SYS_EQ_HEAD0 0x025057#define BCMA_CORE_PCIE2_SYS_EQ_TAIL0 0x025458#define BCMA_CORE_PCIE2_SYS_EQ_HEAD1 0x025859#define BCMA_CORE_PCIE2_SYS_EQ_TAIL1 0x025C60#define BCMA_CORE_PCIE2_SYS_EQ_HEAD2 0x026061#define BCMA_CORE_PCIE2_SYS_EQ_TAIL2 0x026462#define BCMA_CORE_PCIE2_SYS_EQ_HEAD3 0x026863#define BCMA_CORE_PCIE2_SYS_EQ_TAIL3 0x026C64#define BCMA_CORE_PCIE2_SYS_EQ_HEAD4 0x027065#define BCMA_CORE_PCIE2_SYS_EQ_TAIL4 0x027466#define BCMA_CORE_PCIE2_SYS_EQ_HEAD5 0x027867#define BCMA_CORE_PCIE2_SYS_EQ_TAIL5 0x027C68#define BCMA_CORE_PCIE2_SYS_RC_INTX_EN 0x033069#define BCMA_CORE_PCIE2_SYS_RC_INTX_CSR 0x033470#define BCMA_CORE_PCIE2_SYS_MSI_REQ 0x034071#define BCMA_CORE_PCIE2_SYS_HOST_INTR_EN 0x034472#define BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR 0x034873#define BCMA_CORE_PCIE2_SYS_HOST_INTR0 0x035074#define BCMA_CORE_PCIE2_SYS_HOST_INTR1 0x035475#define BCMA_CORE_PCIE2_SYS_HOST_INTR2 0x035876#define BCMA_CORE_PCIE2_SYS_HOST_INTR3 0x035C77#define BCMA_CORE_PCIE2_SYS_EP_INT_EN0 0x036078#define BCMA_CORE_PCIE2_SYS_EP_INT_EN1 0x036479#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR0 0x037080#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR1 0x037481#define BCMA_CORE_PCIE2_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2))82#define BCMA_CORE_PCIE2_FUNC0_IMAP0_0 0x0C0083#define BCMA_CORE_PCIE2_FUNC0_IMAP0_1 0x0C0484#define BCMA_CORE_PCIE2_FUNC0_IMAP0_2 0x0C0885#define BCMA_CORE_PCIE2_FUNC0_IMAP0_3 0x0C0C86#define BCMA_CORE_PCIE2_FUNC0_IMAP0_4 0x0C1087#define BCMA_CORE_PCIE2_FUNC0_IMAP0_5 0x0C1488#define BCMA_CORE_PCIE2_FUNC0_IMAP0_6 0x0C1889#define BCMA_CORE_PCIE2_FUNC0_IMAP0_7 0x0C1C90#define BCMA_CORE_PCIE2_FUNC1_IMAP0_0 0x0C2091#define BCMA_CORE_PCIE2_FUNC1_IMAP0_1 0x0C2492#define BCMA_CORE_PCIE2_FUNC1_IMAP0_2 0x0C2893#define BCMA_CORE_PCIE2_FUNC1_IMAP0_3 0x0C2C94#define BCMA_CORE_PCIE2_FUNC1_IMAP0_4 0x0C3095#define BCMA_CORE_PCIE2_FUNC1_IMAP0_5 0x0C3496#define BCMA_CORE_PCIE2_FUNC1_IMAP0_6 0x0C3897#define BCMA_CORE_PCIE2_FUNC1_IMAP0_7 0x0C3C98#define BCMA_CORE_PCIE2_FUNC0_IMAP1 0x0C8099#define BCMA_CORE_PCIE2_FUNC1_IMAP1 0x0C88100#define BCMA_CORE_PCIE2_FUNC0_IMAP2 0x0CC0101#define BCMA_CORE_PCIE2_FUNC1_IMAP2 0x0CC8102#define BCMA_CORE_PCIE2_IARR0_LOWER 0x0D00103#define BCMA_CORE_PCIE2_IARR0_UPPER 0x0D04104#define BCMA_CORE_PCIE2_IARR1_LOWER 0x0D08105#define BCMA_CORE_PCIE2_IARR1_UPPER 0x0D0C106#define BCMA_CORE_PCIE2_IARR2_LOWER 0x0D10107#define BCMA_CORE_PCIE2_IARR2_UPPER 0x0D14108#define BCMA_CORE_PCIE2_OARR0 0x0D20109#define BCMA_CORE_PCIE2_OARR1 0x0D28110#define BCMA_CORE_PCIE2_OARR2 0x0D30111#define BCMA_CORE_PCIE2_OMAP0_LOWER 0x0D40112#define BCMA_CORE_PCIE2_OMAP0_UPPER 0x0D44113#define BCMA_CORE_PCIE2_OMAP1_LOWER 0x0D48114#define BCMA_CORE_PCIE2_OMAP1_UPPER 0x0D4C115#define BCMA_CORE_PCIE2_OMAP2_LOWER 0x0D50116#define BCMA_CORE_PCIE2_OMAP2_UPPER 0x0D54117#define BCMA_CORE_PCIE2_FUNC1_IARR1_SIZE 0x0D58118#define BCMA_CORE_PCIE2_FUNC1_IARR2_SIZE 0x0D5C119#define BCMA_CORE_PCIE2_MEM_CONTROL 0x0F00120#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG0 0x0F04121#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG1 0x0F08122#define BCMA_CORE_PCIE2_LINK_STATUS 0x0F0C123#define BCMA_CORE_PCIE2_STRAP_STATUS 0x0F10124#define BCMA_CORE_PCIE2_RESET_STATUS 0x0F14125#define BCMA_CORE_PCIE2_RESETEN_IN_LINKDOWN 0x0F18126#define BCMA_CORE_PCIE2_MISC_INTR_EN 0x0F1C127#define BCMA_CORE_PCIE2_TX_DEBUG_CFG 0x0F20128#define BCMA_CORE_PCIE2_MISC_CONFIG 0x0F24129#define BCMA_CORE_PCIE2_MISC_STATUS 0x0F28130#define BCMA_CORE_PCIE2_INTR_EN 0x0F30131#define BCMA_CORE_PCIE2_INTR_CLEAR 0x0F34132#define BCMA_CORE_PCIE2_INTR_STATUS 0x0F38133 134/* PCIE gen2 config regs */135#define PCIE2_INTSTATUS 0x090136#define PCIE2_INTMASK 0x094137#define PCIE2_SBMBX 0x098138 139#define PCIE2_PMCR_REFUP 0x1814 /* Trefup time */140 141#define PCIE2_CAP_DEVSTSCTRL2_OFFSET 0xD4142#define PCIE2_CAP_DEVSTSCTRL2_LTRENAB 0x400143#define PCIE2_PVT_REG_PM_CLK_PERIOD 0x184c144 145struct bcma_drv_pcie2 {146 struct bcma_device *core;147 148 u16 reqsize;149};150 151#define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset)152#define pcie2_read32(pcie2, offset) bcma_read32((pcie2)->core, offset)153#define pcie2_write16(pcie2, offset, val) bcma_write16((pcie2)->core, offset, val)154#define pcie2_write32(pcie2, offset, val) bcma_write32((pcie2)->core, offset, val)155 156#define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set)157#define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask)158 159#endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */160