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1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef _LINUX_BRCMPHY_H3#define _LINUX_BRCMPHY_H4 5#include <linux/phy.h>6 7/* All Broadcom Ethernet switches have a pseudo-PHY at address 30 which is used8 * to configure the switch internal registers via MDIO accesses.9 */10#define BRCM_PSEUDO_PHY_ADDR 3011 12#define PHY_ID_BCM50610 0x0143bd6013#define PHY_ID_BCM50610M 0x0143bd7014#define PHY_ID_BCM5221 0x004061e015#define PHY_ID_BCM5241 0x0143bc3016#define PHY_ID_BCMAC131 0x0143bc7017#define PHY_ID_BCM5481 0x0143bca018#define PHY_ID_BCM5395 0x0143bcf019#define PHY_ID_BCM53125 0x03625f2020#define PHY_ID_BCM53128 0x03625e1021#define PHY_ID_BCM54810 0x03625d0022#define PHY_ID_BCM54811 0x03625cc023#define PHY_ID_BCM5482 0x0143bcb024#define PHY_ID_BCM5411 0x0020607025#define PHY_ID_BCM5421 0x002060e026#define PHY_ID_BCM54210E 0x600d84a027#define PHY_ID_BCM5464 0x002060b028#define PHY_ID_BCM5461 0x002060c029#define PHY_ID_BCM54612E 0x03625e6030#define PHY_ID_BCM54616S 0x03625d1031#define PHY_ID_BCM54140 0xae02500932#define PHY_ID_BCM57780 0x03625d9033#define PHY_ID_BCM89610 0x03625cd034 35#define PHY_ID_BCM72113 0x3590531036#define PHY_ID_BCM72116 0x3590535037#define PHY_ID_BCM72165 0x3590534038#define PHY_ID_BCM7250 0xae02528039#define PHY_ID_BCM7255 0xae02512040#define PHY_ID_BCM7260 0xae02519041#define PHY_ID_BCM7268 0xae02509042#define PHY_ID_BCM7271 0xae0253b043#define PHY_ID_BCM7278 0xae0251a044#define PHY_ID_BCM7364 0xae02526045#define PHY_ID_BCM7366 0x600d849046#define PHY_ID_BCM7346 0x600d865047#define PHY_ID_BCM7362 0x600d84b048#define PHY_ID_BCM74165 0x359052c049#define PHY_ID_BCM7425 0x600d86b050#define PHY_ID_BCM7429 0x600d873051#define PHY_ID_BCM7435 0x600d875052#define PHY_ID_BCM74371 0xae0252e053#define PHY_ID_BCM7439 0x600d848054#define PHY_ID_BCM7439_2 0xae02508055#define PHY_ID_BCM7445 0x600d851056#define PHY_ID_BCM7712 0x3590533057 58#define PHY_ID_BCM_CYGNUS 0xae02520059#define PHY_ID_BCM_OMEGA 0xae02510060 61#define PHY_BCM_OUI_MASK 0xfffffc0062#define PHY_BCM_OUI_1 0x0020600063#define PHY_BCM_OUI_2 0x0143bc0064#define PHY_BCM_OUI_3 0x03625c0065#define PHY_BCM_OUI_4 0x600d840066#define PHY_BCM_OUI_5 0x03625e0067#define PHY_BCM_OUI_6 0xae02500068 69#define PHY_BRCM_AUTO_PWRDWN_ENABLE 0x0000000170#define PHY_BRCM_RX_REFCLK_UNUSED 0x0000000271#define PHY_BRCM_CLEAR_RGMII_MODE 0x0000000472#define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x0000000873#define PHY_BRCM_EN_MASTER_MODE 0x0000001074#define PHY_BRCM_IDDQ_SUSPEND 0x0000002075 76/* Broadcom BCM7xxx specific workarounds */77#define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff)78#define PHY_BRCM_7XXX_PATCH(x) ((x) & 0xff)79#define PHY_BCM_FLAGS_VALID 0x8000000080 81/* Broadcom BCM54XX register definitions, common to most Broadcom PHYs */82#define MII_BCM54XX_ECR 0x10 /* BCM54xx extended control register */83#define MII_BCM54XX_ECR_IM 0x1000 /* Interrupt mask */84#define MII_BCM54XX_ECR_IF 0x0800 /* Interrupt force */85#define MII_BCM54XX_ECR_FIFOE 0x0001 /* FIFO elasticity */86 87#define MII_BCM54XX_ESR 0x11 /* BCM54xx extended status register */88#define MII_BCM54XX_ESR_IS 0x1000 /* Interrupt status */89 90#define MII_BCM54XX_EXP_DATA 0x15 /* Expansion register data */91#define MII_BCM54XX_EXP_SEL 0x17 /* Expansion register select */92#define MII_BCM54XX_EXP_SEL_TOP 0x0d00 /* TOP_MISC expansion register select */93#define MII_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */94#define MII_BCM54XX_EXP_SEL_WOL 0x0e00 /* Wake-on-LAN expansion select register */95#define MII_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */96#define MII_BCM54XX_EXP_SEL_ETC 0x0d00 /* Expansion register spare + 2k mem */97 98#define MII_BCM54XX_AUX_CTL 0x18 /* Auxiliary control register */99#define MII_BCM54XX_ISR 0x1a /* BCM54xx interrupt status register */100#define MII_BCM54XX_IMR 0x1b /* BCM54xx interrupt mask register */101#define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC error */102#define MII_BCM54XX_INT_LINK 0x0002 /* Link status changed */103#define MII_BCM54XX_INT_SPEED 0x0004 /* Link speed change */104#define MII_BCM54XX_INT_DUPLEX 0x0008 /* Duplex mode changed */105#define MII_BCM54XX_INT_LRS 0x0010 /* Local receiver status changed */106#define MII_BCM54XX_INT_RRS 0x0020 /* Remote receiver status changed */107#define MII_BCM54XX_INT_SSERR 0x0040 /* Scrambler synchronization error */108#define MII_BCM54XX_INT_UHCD 0x0080 /* Unsupported HCD negotiated */109#define MII_BCM54XX_INT_NHCD 0x0100 /* No HCD */110#define MII_BCM54XX_INT_NHCDL 0x0200 /* No HCD link */111#define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */112#define MII_BCM54XX_INT_LC 0x0800 /* All counters below 128 */113#define MII_BCM54XX_INT_HC 0x1000 /* Counter above 32768 */114#define MII_BCM54XX_INT_MDIX 0x2000 /* MDIX status change */115#define MII_BCM54XX_INT_PSERR 0x4000 /* Pair swap error */116 117#define MII_BCM54XX_SHD 0x1c /* 0x1c shadow registers */118#define MII_BCM54XX_SHD_WRITE 0x8000119#define MII_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10)120#define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)121 122#define MII_BCM54XX_RDB_ADDR 0x1e123#define MII_BCM54XX_RDB_DATA 0x1f124 125/* legacy access control via rdb/expansion register */126#define BCM54XX_RDB_REG0087 0x0087127#define BCM54XX_EXP_REG7E (MII_BCM54XX_EXP_SEL_ER + 0x7E)128#define BCM54XX_ACCESS_MODE_LEGACY_EN BIT(15)129 130/*131 * AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18)132 */133#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x00134#define MII_BCM54XX_AUXCTL_ACTL_TX_6DB 0x0400135#define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800136#define MII_BCM54XX_AUXCTL_ACTL_EXT_PKT_LEN 0x4000137 138#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x07139#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN 0x0010140#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN 0x0080141#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN 0x0100142#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200143#define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000144 145#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12146#define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007147 148/*149 * Broadcom LED source encodings. These are used in BCM5461, BCM5481,150 * BCM5482, and possibly some others.151 */152#define BCM_LED_SRC_LINKSPD1 0x0153#define BCM_LED_SRC_LINKSPD2 0x1154#define BCM_LED_SRC_XMITLED 0x2155#define BCM_LED_SRC_ACTIVITYLED 0x3156#define BCM_LED_SRC_FDXLED 0x4157#define BCM_LED_SRC_SLAVE 0x5158#define BCM_LED_SRC_INTR 0x6159#define BCM_LED_SRC_QUALITY 0x7160#define BCM_LED_SRC_RCVLED 0x8161#define BCM_LED_SRC_WIRESPEED 0x9162#define BCM_LED_SRC_MULTICOLOR1 0xa163#define BCM_LED_SRC_OPENSHORT 0xb164#define BCM_LED_SRC_OFF 0xe /* Tied high */165#define BCM_LED_SRC_ON 0xf /* Tied low */166#define BCM_LED_SRC_MASK GENMASK(3, 0)167 168/*169 * Broadcom Multicolor LED configurations (expansion register 4)170 */171#define BCM_EXP_MULTICOLOR (MII_BCM54XX_EXP_SEL_ER + 0x04)172#define BCM_LED_MULTICOLOR_IN_PHASE BIT(8)173#define BCM_LED_MULTICOLOR_LINK_ACT 0x0174#define BCM_LED_MULTICOLOR_SPEED 0x1175#define BCM_LED_MULTICOLOR_ACT_FLASH 0x2176#define BCM_LED_MULTICOLOR_FDX 0x3177#define BCM_LED_MULTICOLOR_OFF 0x4178#define BCM_LED_MULTICOLOR_ON 0x5179#define BCM_LED_MULTICOLOR_ALT 0x6180#define BCM_LED_MULTICOLOR_FLASH 0x7181#define BCM_LED_MULTICOLOR_LINK 0x8182#define BCM_LED_MULTICOLOR_ACT 0x9183#define BCM_LED_MULTICOLOR_PROGRAM 0xa184 185/*186 * BCM5482: Shadow registers187 * Shadow values go into bits [14:10] of register 0x1c to select a shadow188 * register to access.189 */190 191/* 00100: Reserved control register 2 */192#define BCM54XX_SHD_SCR2 0x04193#define BCM54XX_SHD_SCR2_WSPD_RTRY_DIS 0x100194#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT 2195#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET 2196#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK 0x7197 198/* 00101: Spare Control Register 3 */199#define BCM54XX_SHD_SCR3 0x05200#define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001201#define BCM54XX_SHD_SCR3_DLLAPD_DIS 0x0002202#define BCM54XX_SHD_SCR3_TRDDAPD 0x0004203#define BCM54XX_SHD_SCR3_RXCTXC_DIS 0x0100204 205/* 01010: Auto Power-Down */206#define BCM54XX_SHD_APD 0x0a207#define BCM_APD_CLR_MASK 0xFE9F /* clear bits 5, 6 & 8 */208#define BCM54XX_SHD_APD_EN 0x0020209#define BCM_NO_ANEG_APD_EN 0x0060 /* bits 5 & 6 */210#define BCM_APD_SINGLELP_EN 0x0100 /* Bit 8 */211 212#define BCM54XX_SHD_LEDS1 0x0d /* 01101: LED Selector 1 */213 /* LED3 / ~LINKSPD[2] selector */214#define BCM54XX_SHD_LEDS_SHIFT(led) (4 * (led))215#define BCM54XX_SHD_LEDS1_LED3(src) ((src & 0xf) << 4)216 /* LED1 / ~LINKSPD[1] selector */217#define BCM54XX_SHD_LEDS1_LED1(src) ((src & 0xf) << 0)218#define BCM54XX_SHD_LEDS2 0x0e /* 01110: LED Selector 2 */219#define BCM54XX_SHD_RGMII_MODE 0x0b /* 01011: RGMII Mode Selector */220#define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */221#define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */222#define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */223 224/* 10011: SerDes 100-FX Control Register */225#define BCM54616S_SHD_100FX_CTRL 0x13226#define BCM54616S_100FX_MODE BIT(0) /* 100-FX SerDes Enable */227 228/* 11111: Mode Control Register */229#define BCM54XX_SHD_MODE 0x1f230#define BCM54XX_SHD_INTF_SEL_MASK GENMASK(2, 1) /* INTERF_SEL[1:0] */231#define BCM54XX_SHD_INTF_SEL_RGMII 0x02232#define BCM54XX_SHD_INTF_SEL_SGMII 0x04233#define BCM54XX_SHD_INTF_SEL_GBIC 0x06234#define BCM54XX_SHD_MODE_1000BX BIT(0) /* Enable 1000-X registers */235 236/*237 * EXPANSION SHADOW ACCESS REGISTERS. (PHY REG 0x15, 0x16, and 0x17)238 */239#define MII_BCM54XX_EXP_AADJ1CH0 0x001f240#define MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN 0x0200241#define MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF 0x0100242#define MII_BCM54XX_EXP_AADJ1CH3 0x601f243#define MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ 0x0002244#define MII_BCM54XX_EXP_EXP08 0x0F08245#define MII_BCM54XX_EXP_EXP08_RJCT_2MHZ 0x0001246#define MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE 0x0200247#define MII_BCM54XX_EXP_EXP08_FORCE_DAC_WAKE 0x0100248#define MII_BCM54XX_EXP_EXP75 0x0f75249#define MII_BCM54XX_EXP_EXP75_VDACCTRL 0x003c250#define MII_BCM54XX_EXP_EXP75_CM_OSC 0x0001251#define MII_BCM54XX_EXP_EXP96 0x0f96252#define MII_BCM54XX_EXP_EXP96_MYST 0x0010253#define MII_BCM54XX_EXP_EXP97 0x0f97254#define MII_BCM54XX_EXP_EXP97_MYST 0x0c0c255 256/* Top-MISC expansion registers */257#define BCM54XX_TOP_MISC_IDDQ_CTRL (MII_BCM54XX_EXP_SEL_TOP + 0x06)258#define BCM54XX_TOP_MISC_IDDQ_LP (1 << 0)259#define BCM54XX_TOP_MISC_IDDQ_SD (1 << 2)260#define BCM54XX_TOP_MISC_IDDQ_SR (1 << 3)261 262#define BCM54XX_TOP_MISC_LED_CTL (MII_BCM54XX_EXP_SEL_TOP + 0x0C)263#define BCM54XX_LED4_SEL_INTR BIT(1)264 265/*266 * BCM5482: Secondary SerDes registers267 */268#define BCM5482_SSD_1000BX_CTL 0x00 /* 1000BASE-X Control */269#define BCM5482_SSD_1000BX_CTL_PWRDOWN 0x0800 /* Power-down SSD */270#define BCM5482_SSD_SGMII_SLAVE 0x15 /* SGMII Slave Register */271#define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */272#define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */273 274/* BroadR-Reach LRE Registers. */275#define MII_BCM54XX_LRECR 0x00 /* LRE Control Register */276#define MII_BCM54XX_LRESR 0x01 /* LRE Status Register */277#define MII_BCM54XX_LREPHYSID1 0x02 /* LRE PHYS ID 1 */278#define MII_BCM54XX_LREPHYSID2 0x03 /* LRE PHYS ID 2 */279#define MII_BCM54XX_LREANAA 0x04 /* LDS Auto-Negotiation Advertised Ability */280#define MII_BCM54XX_LREANAC 0x05 /* LDS Auto-Negotiation Advertised Control */281#define MII_BCM54XX_LREANPT 0x06 /* LDS Ability Next Page Transmit */282#define MII_BCM54XX_LRELPA 0x07 /* LDS Link Partner Ability */283#define MII_BCM54XX_LRELPNPM 0x08 /* LDS Link Partner Next Page Message */284#define MII_BCM54XX_LRELPNPC 0x09 /* LDS Link Partner Next Page Control */285#define MII_BCM54XX_LRELDSE 0x0a /* LDS Expansion Register */286#define MII_BCM54XX_LREES 0x0f /* LRE Extended Status */287 288/* LRE control register. */289#define LRECR_RESET 0x8000 /* Reset to default state */290#define LRECR_LOOPBACK 0x4000 /* Internal Loopback */291#define LRECR_LDSRES 0x2000 /* Restart LDS Process */292#define LRECR_LDSEN 0x1000 /* LDS Enable */293#define LRECR_PDOWN 0x0800 /* Enable low power state */294#define LRECR_ISOLATE 0x0400 /* Isolate data paths from MII */295#define LRECR_SPEED100 0x0200 /* Select 100 Mbps */296#define LRECR_SPEED10 0x0000 /* Select 10 Mbps */297#define LRECR_4PAIRS 0x0020 /* Select 4 Pairs */298#define LRECR_2PAIRS 0x0010 /* Select 2 Pairs */299#define LRECR_1PAIR 0x0000 /* Select 1 Pair */300#define LRECR_MASTER 0x0008 /* Force Master when LDS disabled */301#define LRECR_SLAVE 0x0000 /* Force Slave when LDS disabled */302 303/* LRE status register. */304#define LRESR_100_1PAIR 0x2000 /* Can do 100Mbps 1 Pair */305#define LRESR_100_4PAIR 0x1000 /* Can do 100Mbps 4 Pairs */306#define LRESR_100_2PAIR 0x0800 /* Can do 100Mbps 2 Pairs */307#define LRESR_10_2PAIR 0x0400 /* Can do 10Mbps 2 Pairs */308#define LRESR_10_1PAIR 0x0200 /* Can do 10Mbps 1 Pair */309#define LRESR_ESTATEN 0x0100 /* Extended Status in R15 */310#define LRESR_RESV 0x0080 /* Unused... */311#define LRESR_MFPS 0x0040 /* Can suppress Management Frames Preamble */312#define LRESR_LDSCOMPLETE 0x0020 /* LDS Auto-negotiation complete */313#define LRESR_8023 0x0010 /* Has IEEE 802.3 Support */314#define LRESR_LDSABILITY 0x0008 /* LDS auto-negotiation capable */315#define LRESR_LSTATUS 0x0004 /* Link status */316#define LRESR_JCD 0x0002 /* Jabber detected */317#define LRESR_ERCAP 0x0001 /* Ext-reg capability */318 319/* LDS Auto-Negotiation Advertised Ability. */320#define LREANAA_PAUSE_ASYM 0x8000 /* Can pause asymmetrically */321#define LREANAA_PAUSE 0x4000 /* Can pause */322#define LREANAA_100_1PAIR 0x0020 /* Can do 100Mbps 1 Pair */323#define LREANAA_100_4PAIR 0x0010 /* Can do 100Mbps 4 Pair */324#define LREANAA_100_2PAIR 0x0008 /* Can do 100Mbps 2 Pair */325#define LREANAA_10_2PAIR 0x0004 /* Can do 10Mbps 2 Pair */326#define LREANAA_10_1PAIR 0x0002 /* Can do 10Mbps 1 Pair */327 328#define LRE_ADVERTISE_FULL (LREANAA_100_1PAIR | LREANAA_100_4PAIR | \329 LREANAA_100_2PAIR | LREANAA_10_2PAIR | \330 LREANAA_10_1PAIR)331 332#define LRE_ADVERTISE_ALL LRE_ADVERTISE_FULL333 334/* LDS Link Partner Ability. */335#define LRELPA_PAUSE_ASYM 0x8000 /* Supports asymmetric pause */336#define LRELPA_PAUSE 0x4000 /* Supports pause capability */337#define LRELPA_100_1PAIR 0x0020 /* 100Mbps 1 Pair capable */338#define LRELPA_100_4PAIR 0x0010 /* 100Mbps 4 Pair capable */339#define LRELPA_100_2PAIR 0x0008 /* 100Mbps 2 Pair capable */340#define LRELPA_10_2PAIR 0x0004 /* 10Mbps 2 Pair capable */341#define LRELPA_10_1PAIR 0x0002 /* 10Mbps 1 Pair capable */342 343/* LDS Expansion register. */344#define LDSE_DOWNGRADE 0x8000 /* Can do LDS Speed Downgrade */345#define LDSE_MASTER 0x4000 /* Master / Slave */346#define LDSE_PAIRS_MASK 0x3000 /* Pair Count Mask */347#define LDSE_PAIRS_SHIFT 12348#define LDSE_4PAIRS (2 << LDSE_PAIRS_SHIFT) /* 4 Pairs Connection */349#define LDSE_2PAIRS (1 << LDSE_PAIRS_SHIFT) /* 2 Pairs Connection */350#define LDSE_1PAIR (0 << LDSE_PAIRS_SHIFT) /* 1 Pair Connection */351#define LDSE_CABLEN_MASK 0x0FFF /* Cable Length Mask */352 353/* BCM54810 Registers */354#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL (MII_BCM54XX_EXP_SEL_ER + 0x90)355#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN (1 << 0)356#define BCM54810_SHD_CLK_CTL 0x3357#define BCM54810_SHD_CLK_CTL_GTXCLK_EN (1 << 9)358 359/* BCM54811 Registers */360#define BCM54811_EXP_BROADREACH_LRE_OVERLAY_CTL (MII_BCM54XX_EXP_SEL_ER + 0x9A)361/* Access Control Override Enable */362#define BCM54811_EXP_BROADREACH_LRE_OVERLAY_CTL_EN BIT(15)363/* Access Control Override Value */364#define BCM54811_EXP_BROADREACH_LRE_OVERLAY_CTL_OVERRIDE_VAL BIT(14)365/* Access Control Value */366#define BCM54811_EXP_BROADREACH_LRE_OVERLAY_CTL_VAL BIT(13)367 368/* BCM54612E Registers */369#define BCM54612E_EXP_SPARE0 (MII_BCM54XX_EXP_SEL_ETC + 0x34)370#define BCM54612E_LED4_CLK125OUT_EN (1 << 1)371 372 373/* Wake-on-LAN registers */374#define BCM54XX_WOL_MAIN_CTL (MII_BCM54XX_EXP_SEL_WOL + 0x80)375#define BCM54XX_WOL_EN BIT(0)376#define BCM54XX_WOL_MODE_SINGLE_MPD 0377#define BCM54XX_WOL_MODE_SINGLE_MPDSEC 1378#define BCM54XX_WOL_MODE_DUAL 2379#define BCM54XX_WOL_MODE_SHIFT 1380#define BCM54XX_WOL_MODE_MASK 0x3381#define BCM54XX_WOL_MP_MSB_FF_EN BIT(3)382#define BCM54XX_WOL_SECKEY_OPT_4B 0383#define BCM54XX_WOL_SECKEY_OPT_6B 1384#define BCM54XX_WOL_SECKEY_OPT_8B 2385#define BCM54XX_WOL_SECKEY_OPT_SHIFT 4386#define BCM54XX_WOL_SECKEY_OPT_MASK 0x3387#define BCM54XX_WOL_L2_TYPE_CHK BIT(6)388#define BCM54XX_WOL_L4IPV4UDP_CHK BIT(7)389#define BCM54XX_WOL_L4IPV6UDP_CHK BIT(8)390#define BCM54XX_WOL_UDPPORT_CHK BIT(9)391#define BCM54XX_WOL_CRC_CHK BIT(10)392#define BCM54XX_WOL_SECKEY_MODE BIT(11)393#define BCM54XX_WOL_RST BIT(12)394#define BCM54XX_WOL_DIR_PKT_EN BIT(13)395#define BCM54XX_WOL_MASK_MODE_DA_FF 0396#define BCM54XX_WOL_MASK_MODE_DA_MPD 1397#define BCM54XX_WOL_MASK_MODE_DA_ONLY 2398#define BCM54XX_WOL_MASK_MODE_MPD 3399#define BCM54XX_WOL_MASK_MODE_SHIFT 14400#define BCM54XX_WOL_MASK_MODE_MASK 0x3401 402#define BCM54XX_WOL_INNER_PROTO (MII_BCM54XX_EXP_SEL_WOL + 0x81)403#define BCM54XX_WOL_OUTER_PROTO (MII_BCM54XX_EXP_SEL_WOL + 0x82)404#define BCM54XX_WOL_OUTER_PROTO2 (MII_BCM54XX_EXP_SEL_WOL + 0x83)405 406#define BCM54XX_WOL_MPD_DATA1(x) (MII_BCM54XX_EXP_SEL_WOL + 0x84 + (x))407#define BCM54XX_WOL_MPD_DATA2(x) (MII_BCM54XX_EXP_SEL_WOL + 0x87 + (x))408#define BCM54XX_WOL_SEC_KEY_8B (MII_BCM54XX_EXP_SEL_WOL + 0x8A)409#define BCM54XX_WOL_MASK(x) (MII_BCM54XX_EXP_SEL_WOL + 0x8B + (x))410#define BCM54XX_SEC_KEY_STORE(x) (MII_BCM54XX_EXP_SEL_WOL + 0x8E)411#define BCM54XX_WOL_SHARED_CNT (MII_BCM54XX_EXP_SEL_WOL + 0x92)412 413#define BCM54XX_WOL_INT_MASK (MII_BCM54XX_EXP_SEL_WOL + 0x93)414#define BCM54XX_WOL_PKT1 BIT(0)415#define BCM54XX_WOL_PKT2 BIT(1)416#define BCM54XX_WOL_DIR BIT(2)417#define BCM54XX_WOL_ALL_INTRS (BCM54XX_WOL_PKT1 | \418 BCM54XX_WOL_PKT2 | \419 BCM54XX_WOL_DIR)420 421#define BCM54XX_WOL_INT_STATUS (MII_BCM54XX_EXP_SEL_WOL + 0x94)422 423/* BCM5221 Registers */424#define BCM5221_AEGSR 0x1C425#define BCM5221_AEGSR_MDIX_STATUS BIT(13)426#define BCM5221_AEGSR_MDIX_MAN_SWAP BIT(12)427#define BCM5221_AEGSR_MDIX_DIS BIT(11)428 429#define BCM5221_SHDW_AM4_EN_CLK_LPM BIT(2)430#define BCM5221_SHDW_AM4_FORCE_LPM BIT(1)431 432/*****************************************************************************/433/* Fast Ethernet Transceiver definitions. */434/*****************************************************************************/435 436#define MII_BRCM_FET_INTREG 0x1a /* Interrupt register */437#define MII_BRCM_FET_IR_MASK 0x0100 /* Mask all interrupts */438#define MII_BRCM_FET_IR_LINK_EN 0x0200 /* Link status change enable */439#define MII_BRCM_FET_IR_SPEED_EN 0x0400 /* Link speed change enable */440#define MII_BRCM_FET_IR_DUPLEX_EN 0x0800 /* Duplex mode change enable */441#define MII_BRCM_FET_IR_ENABLE 0x4000 /* Interrupt enable */442 443#define MII_BRCM_FET_BRCMTEST 0x1f /* Brcm test register */444#define MII_BRCM_FET_BT_SRE 0x0080 /* Shadow register enable */445 446 447/*** Shadow register definitions ***/448 449#define MII_BRCM_FET_SHDW_MISCCTRL 0x10 /* Shadow misc ctrl */450#define MII_BRCM_FET_SHDW_MC_FAME 0x4000 /* Force Auto MDIX enable */451 452#define MII_BRCM_FET_SHDW_AUXMODE4 0x1a /* Auxiliary mode 4 */453#define MII_BRCM_FET_SHDW_AM4_STANDBY 0x0008 /* Standby enable */454#define MII_BRCM_FET_SHDW_AM4_LED_MASK 0x0003455#define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001456 457#define MII_BRCM_FET_SHDW_AUXSTAT2 0x1b /* Auxiliary status 2 */458#define MII_BRCM_FET_SHDW_AS2_APDE 0x0020 /* Auto power down enable */459 460#define BRCM_CL45VEN_EEE_CONTROL 0x803d461#define LPI_FEATURE_EN 0x8000462#define LPI_FEATURE_EN_DIG1000X 0x4000463 464#define BRCM_CL45VEN_EEE_LPI_CNT 0x803f465 466/* Core register definitions*/467#define MII_BRCM_CORE_BASE12 0x12468#define MII_BRCM_CORE_BASE13 0x13469#define MII_BRCM_CORE_BASE14 0x14470#define MII_BRCM_CORE_BASE1E 0x1E471#define MII_BRCM_CORE_EXPB0 0xB0472#define MII_BRCM_CORE_EXPB1 0xB1473 474/* Enhanced Cable Diagnostics */475#define BCM54XX_RDB_ECD_CTRL 0x2a0476#define BCM54XX_EXP_ECD_CTRL (MII_BCM54XX_EXP_SEL_ER + 0xc0)477 478#define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT3 1 /* CAT3 or worse */479#define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT5 0 /* CAT5 or better */480#define BCM54XX_ECD_CTRL_CABLE_TYPE_MASK BIT(0) /* cable type */481#define BCM54XX_ECD_CTRL_INVALID BIT(3) /* invalid result */482#define BCM54XX_ECD_CTRL_UNIT_CM 0 /* centimeters */483#define BCM54XX_ECD_CTRL_UNIT_M 1 /* meters */484#define BCM54XX_ECD_CTRL_UNIT_MASK BIT(10) /* cable length unit */485#define BCM54XX_ECD_CTRL_IN_PROGRESS BIT(11) /* test in progress */486#define BCM54XX_ECD_CTRL_BREAK_LINK BIT(12) /* unconnect link487 * during test488 */489#define BCM54XX_ECD_CTRL_CROSS_SHORT_DIS BIT(13) /* disable inter-pair490 * short check491 */492#define BCM54XX_ECD_CTRL_RUN BIT(15) /* run immediate */493 494#define BCM54XX_RDB_ECD_FAULT_TYPE 0x2a1495#define BCM54XX_EXP_ECD_FAULT_TYPE (MII_BCM54XX_EXP_SEL_ER + 0xc1)496#define BCM54XX_ECD_FAULT_TYPE_INVALID 0x0497#define BCM54XX_ECD_FAULT_TYPE_OK 0x1498#define BCM54XX_ECD_FAULT_TYPE_OPEN 0x2499#define BCM54XX_ECD_FAULT_TYPE_SAME_SHORT 0x3 /* short same pair */500#define BCM54XX_ECD_FAULT_TYPE_CROSS_SHORT 0x4 /* short different pairs */501#define BCM54XX_ECD_FAULT_TYPE_BUSY 0x9502#define BCM54XX_ECD_FAULT_TYPE_PAIR_D_MASK GENMASK(3, 0)503#define BCM54XX_ECD_FAULT_TYPE_PAIR_C_MASK GENMASK(7, 4)504#define BCM54XX_ECD_FAULT_TYPE_PAIR_B_MASK GENMASK(11, 8)505#define BCM54XX_ECD_FAULT_TYPE_PAIR_A_MASK GENMASK(15, 12)506#define BCM54XX_ECD_PAIR_A_LENGTH_RESULTS 0x2a2507#define BCM54XX_ECD_PAIR_B_LENGTH_RESULTS 0x2a3508#define BCM54XX_ECD_PAIR_C_LENGTH_RESULTS 0x2a4509#define BCM54XX_ECD_PAIR_D_LENGTH_RESULTS 0x2a5510 511#define BCM54XX_RDB_ECD_PAIR_A_LENGTH_RESULTS 0x2a2512#define BCM54XX_EXP_ECD_PAIR_A_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc2)513#define BCM54XX_RDB_ECD_PAIR_B_LENGTH_RESULTS 0x2a3514#define BCM54XX_EXP_ECD_PAIR_B_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc3)515#define BCM54XX_RDB_ECD_PAIR_C_LENGTH_RESULTS 0x2a4516#define BCM54XX_EXP_ECD_PAIR_C_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc4)517#define BCM54XX_RDB_ECD_PAIR_D_LENGTH_RESULTS 0x2a5518#define BCM54XX_EXP_ECD_PAIR_D_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc5)519#define BCM54XX_ECD_LENGTH_RESULTS_INVALID 0xffff520 521#endif /* _LINUX_BRCMPHY_H */522