37 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef _CAN_PLATFORM_SJA1000_H3#define _CAN_PLATFORM_SJA1000_H4 5/* clock divider register */6#define CDR_CLKOUT_MASK 0x077#define CDR_CLK_OFF 0x08 /* Clock off (CLKOUT pin) */8#define CDR_RXINPEN 0x20 /* TX1 output is RX irq output */9#define CDR_CBP 0x40 /* CAN input comparator bypass */10#define CDR_PELICAN 0x80 /* PeliCAN mode */11 12/* output control register */13#define OCR_MODE_BIPHASE 0x0014#define OCR_MODE_TEST 0x0115#define OCR_MODE_NORMAL 0x0216#define OCR_MODE_CLOCK 0x0317#define OCR_MODE_MASK 0x0318#define OCR_TX0_INVERT 0x0419#define OCR_TX0_PULLDOWN 0x0820#define OCR_TX0_PULLUP 0x1021#define OCR_TX0_PUSHPULL 0x1822#define OCR_TX1_INVERT 0x2023#define OCR_TX1_PULLDOWN 0x4024#define OCR_TX1_PULLUP 0x8025#define OCR_TX1_PUSHPULL 0xc026#define OCR_TX_MASK 0xfc27#define OCR_TX_SHIFT 228 29struct sja1000_platform_data {30 u32 osc_freq; /* CAN bus oscillator frequency in Hz */31 32 u8 ocr; /* output control register */33 u8 cdr; /* clock divider register */34};35 36#endif /* !_CAN_PLATFORM_SJA1000_H */37