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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>5 */6#ifndef __LINUX_CLK_PROVIDER_H7#define __LINUX_CLK_PROVIDER_H8 9#include <linux/of.h>10#include <linux/of_clk.h>11 12/*13 * flags used across common struct clk. these flags should only affect the14 * top-level framework. custom flags for dealing with hardware specifics15 * belong in struct clk_foo16 *17 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!18 */19#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */20#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */21#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */22#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */23 /* unused */24 /* unused */25#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */26#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */27#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */28#define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */29#define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */30#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */31/* parents need enable during gate/ungate, set rate and re-parent */32#define CLK_OPS_PARENT_ENABLE BIT(12)33/* duty cycle call may be forwarded to the parent clock */34#define CLK_DUTY_CYCLE_PARENT BIT(13)35 36struct clk;37struct clk_hw;38struct clk_core;39struct dentry;40 41/**42 * struct clk_rate_request - Structure encoding the clk constraints that43 * a clock user might require.44 *45 * Should be initialized by calling clk_hw_init_rate_request().46 *47 * @core: Pointer to the struct clk_core affected by this request48 * @rate: Requested clock rate. This field will be adjusted by49 * clock drivers according to hardware capabilities.50 * @min_rate: Minimum rate imposed by clk users.51 * @max_rate: Maximum rate imposed by clk users.52 * @best_parent_rate: The best parent rate a parent can provide to fulfill the53 * requested constraints.54 * @best_parent_hw: The most appropriate parent clock that fulfills the55 * requested constraints.56 *57 */58struct clk_rate_request {59 struct clk_core *core;60 unsigned long rate;61 unsigned long min_rate;62 unsigned long max_rate;63 unsigned long best_parent_rate;64 struct clk_hw *best_parent_hw;65};66 67void clk_hw_init_rate_request(const struct clk_hw *hw,68 struct clk_rate_request *req,69 unsigned long rate);70void clk_hw_forward_rate_request(const struct clk_hw *core,71 const struct clk_rate_request *old_req,72 const struct clk_hw *parent,73 struct clk_rate_request *req,74 unsigned long parent_rate);75 76/**77 * struct clk_duty - Structure encoding the duty cycle ratio of a clock78 *79 * @num: Numerator of the duty cycle ratio80 * @den: Denominator of the duty cycle ratio81 */82struct clk_duty {83 unsigned int num;84 unsigned int den;85};86 87/**88 * struct clk_ops - Callback operations for hardware clocks; these are to89 * be provided by the clock implementation, and will be called by drivers90 * through the clk_* api.91 *92 * @prepare: Prepare the clock for enabling. This must not return until93 * the clock is fully prepared, and it's safe to call clk_enable.94 * This callback is intended to allow clock implementations to95 * do any initialisation that may sleep. Called with96 * prepare_lock held.97 *98 * @unprepare: Release the clock from its prepared state. This will typically99 * undo any work done in the @prepare callback. Called with100 * prepare_lock held.101 *102 * @is_prepared: Queries the hardware to determine if the clock is prepared.103 * This function is allowed to sleep. Optional, if this op is not104 * set then the prepare count will be used.105 *106 * @unprepare_unused: Unprepare the clock atomically. Only called from107 * clk_disable_unused for prepare clocks with special needs.108 * Called with prepare mutex held. This function may sleep.109 *110 * @enable: Enable the clock atomically. This must not return until the111 * clock is generating a valid clock signal, usable by consumer112 * devices. Called with enable_lock held. This function must not113 * sleep.114 *115 * @disable: Disable the clock atomically. Called with enable_lock held.116 * This function must not sleep.117 *118 * @is_enabled: Queries the hardware to determine if the clock is enabled.119 * This function must not sleep. Optional, if this op is not120 * set then the enable count will be used.121 *122 * @disable_unused: Disable the clock atomically. Only called from123 * clk_disable_unused for gate clocks with special needs.124 * Called with enable_lock held. This function must not125 * sleep.126 *127 * @save_context: Save the context of the clock in prepration for poweroff.128 *129 * @restore_context: Restore the context of the clock after a restoration130 * of power.131 *132 * @recalc_rate: Recalculate the rate of this clock, by querying hardware. The133 * parent rate is an input parameter. It is up to the caller to134 * ensure that the prepare_mutex is held across this call. If the135 * driver cannot figure out a rate for this clock, it must return136 * 0. Returns the calculated rate. Optional, but recommended - if137 * this op is not set then clock rate will be initialized to 0.138 *139 * @round_rate: Given a target rate as input, returns the closest rate actually140 * supported by the clock. The parent rate is an input/output141 * parameter.142 *143 * @determine_rate: Given a target rate as input, returns the closest rate144 * actually supported by the clock, and optionally the parent clock145 * that should be used to provide the clock rate.146 *147 * @set_parent: Change the input source of this clock; for clocks with multiple148 * possible parents specify a new parent by passing in the index149 * as a u8 corresponding to the parent in either the .parent_names150 * or .parents arrays. This function in affect translates an151 * array index into the value programmed into the hardware.152 * Returns 0 on success, -EERROR otherwise.153 *154 * @get_parent: Queries the hardware to determine the parent of a clock. The155 * return value is a u8 which specifies the index corresponding to156 * the parent clock. This index can be applied to either the157 * .parent_names or .parents arrays. In short, this function158 * translates the parent value read from hardware into an array159 * index. Currently only called when the clock is initialized by160 * __clk_init. This callback is mandatory for clocks with161 * multiple parents. It is optional (and unnecessary) for clocks162 * with 0 or 1 parents.163 *164 * @set_rate: Change the rate of this clock. The requested rate is specified165 * by the second argument, which should typically be the return166 * of .round_rate call. The third argument gives the parent rate167 * which is likely helpful for most .set_rate implementation.168 * Returns 0 on success, -EERROR otherwise.169 *170 * @set_rate_and_parent: Change the rate and the parent of this clock. The171 * requested rate is specified by the second argument, which172 * should typically be the return of .round_rate call. The173 * third argument gives the parent rate which is likely helpful174 * for most .set_rate_and_parent implementation. The fourth175 * argument gives the parent index. This callback is optional (and176 * unnecessary) for clocks with 0 or 1 parents as well as177 * for clocks that can tolerate switching the rate and the parent178 * separately via calls to .set_parent and .set_rate.179 * Returns 0 on success, -EERROR otherwise.180 *181 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy182 * is expressed in ppb (parts per billion). The parent accuracy is183 * an input parameter.184 * Returns the calculated accuracy. Optional - if this op is not185 * set then clock accuracy will be initialized to parent accuracy186 * or 0 (perfect clock) if clock has no parent.187 *188 * @get_phase: Queries the hardware to get the current phase of a clock.189 * Returned values are 0-359 degrees on success, negative190 * error codes on failure.191 *192 * @set_phase: Shift the phase this clock signal in degrees specified193 * by the second argument. Valid values for degrees are194 * 0-359. Return 0 on success, otherwise -EERROR.195 *196 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio197 * of a clock. Returned values denominator cannot be 0 and must be198 * superior or equal to the numerator.199 *200 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by201 * the numerator (2nd argurment) and denominator (3rd argument).202 * Argument must be a valid ratio (denominator > 0203 * and >= numerator) Return 0 on success, otherwise -EERROR.204 *205 * @init: Perform platform-specific initialization magic.206 * This is not used by any of the basic clock types.207 * This callback exist for HW which needs to perform some208 * initialisation magic for CCF to get an accurate view of the209 * clock. It may also be used dynamic resource allocation is210 * required. It shall not used to deal with clock parameters,211 * such as rate or parents.212 * Returns 0 on success, -EERROR otherwise.213 *214 * @terminate: Free any resource allocated by init.215 *216 * @debug_init: Set up type-specific debugfs entries for this clock. This217 * is called once, after the debugfs directory entry for this218 * clock has been created. The dentry pointer representing that219 * directory is provided as an argument. Called with220 * prepare_lock held. Returns 0 on success, -EERROR otherwise.221 *222 *223 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow224 * implementations to split any work between atomic (enable) and sleepable225 * (prepare) contexts. If enabling a clock requires code that might sleep,226 * this must be done in clk_prepare. Clock enable code that will never be227 * called in a sleepable context may be implemented in clk_enable.228 *229 * Typically, drivers will call clk_prepare when a clock may be needed later230 * (eg. when a device is opened), and clk_enable when the clock is actually231 * required (eg. from an interrupt). Note that clk_prepare MUST have been232 * called before clk_enable.233 */234struct clk_ops {235 int (*prepare)(struct clk_hw *hw);236 void (*unprepare)(struct clk_hw *hw);237 int (*is_prepared)(struct clk_hw *hw);238 void (*unprepare_unused)(struct clk_hw *hw);239 int (*enable)(struct clk_hw *hw);240 void (*disable)(struct clk_hw *hw);241 int (*is_enabled)(struct clk_hw *hw);242 void (*disable_unused)(struct clk_hw *hw);243 int (*save_context)(struct clk_hw *hw);244 void (*restore_context)(struct clk_hw *hw);245 unsigned long (*recalc_rate)(struct clk_hw *hw,246 unsigned long parent_rate);247 long (*round_rate)(struct clk_hw *hw, unsigned long rate,248 unsigned long *parent_rate);249 int (*determine_rate)(struct clk_hw *hw,250 struct clk_rate_request *req);251 int (*set_parent)(struct clk_hw *hw, u8 index);252 u8 (*get_parent)(struct clk_hw *hw);253 int (*set_rate)(struct clk_hw *hw, unsigned long rate,254 unsigned long parent_rate);255 int (*set_rate_and_parent)(struct clk_hw *hw,256 unsigned long rate,257 unsigned long parent_rate, u8 index);258 unsigned long (*recalc_accuracy)(struct clk_hw *hw,259 unsigned long parent_accuracy);260 int (*get_phase)(struct clk_hw *hw);261 int (*set_phase)(struct clk_hw *hw, int degrees);262 int (*get_duty_cycle)(struct clk_hw *hw,263 struct clk_duty *duty);264 int (*set_duty_cycle)(struct clk_hw *hw,265 struct clk_duty *duty);266 int (*init)(struct clk_hw *hw);267 void (*terminate)(struct clk_hw *hw);268 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);269};270 271/**272 * struct clk_parent_data - clk parent information273 * @hw: parent clk_hw pointer (used for clk providers with internal clks)274 * @fw_name: parent name local to provider registering clk275 * @name: globally unique parent name (used as a fallback)276 * @index: parent index local to provider registering clk (if @fw_name absent)277 */278struct clk_parent_data {279 const struct clk_hw *hw;280 const char *fw_name;281 const char *name;282 int index;283};284 285/**286 * struct clk_init_data - holds init data that's common to all clocks and is287 * shared between the clock provider and the common clock framework.288 *289 * @name: clock name290 * @ops: operations this clock supports291 * @parent_names: array of string names for all possible parents292 * @parent_data: array of parent data for all possible parents (when some293 * parents are external to the clk controller)294 * @parent_hws: array of pointers to all possible parents (when all parents295 * are internal to the clk controller)296 * @num_parents: number of possible parents297 * @flags: framework-level hints and quirks298 */299struct clk_init_data {300 const char *name;301 const struct clk_ops *ops;302 /* Only one of the following three should be assigned */303 const char * const *parent_names;304 const struct clk_parent_data *parent_data;305 const struct clk_hw **parent_hws;306 u8 num_parents;307 unsigned long flags;308};309 310/**311 * struct clk_hw - handle for traversing from a struct clk to its corresponding312 * hardware-specific structure. struct clk_hw should be declared within struct313 * clk_foo and then referenced by the struct clk instance that uses struct314 * clk_foo's clk_ops315 *316 * @core: pointer to the struct clk_core instance that points back to this317 * struct clk_hw instance318 *319 * @clk: pointer to the per-user struct clk instance that can be used to call320 * into the clk API321 *322 * @init: pointer to struct clk_init_data that contains the init data shared323 * with the common clock framework. This pointer will be set to NULL once324 * a clk_register() variant is called on this clk_hw pointer.325 */326struct clk_hw {327 struct clk_core *core;328 struct clk *clk;329 const struct clk_init_data *init;330};331 332/*333 * DOC: Basic clock implementations common to many platforms334 *335 * Each basic clock hardware type is comprised of a structure describing the336 * clock hardware, implementations of the relevant callbacks in struct clk_ops,337 * unique flags for that hardware type, a registration function and an338 * alternative macro for static initialization339 */340 341/**342 * struct clk_fixed_rate - fixed-rate clock343 * @hw: handle between common and hardware-specific interfaces344 * @fixed_rate: constant frequency of clock345 * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)346 * @flags: hardware specific flags347 *348 * Flags:349 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk350 * instead of what's set in @fixed_accuracy.351 */352struct clk_fixed_rate {353 struct clk_hw hw;354 unsigned long fixed_rate;355 unsigned long fixed_accuracy;356 unsigned long flags;357};358 359#define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)360 361extern const struct clk_ops clk_fixed_rate_ops;362struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,363 struct device_node *np, const char *name,364 const char *parent_name, const struct clk_hw *parent_hw,365 const struct clk_parent_data *parent_data, unsigned long flags,366 unsigned long fixed_rate, unsigned long fixed_accuracy,367 unsigned long clk_fixed_flags, bool devm);368struct clk *clk_register_fixed_rate(struct device *dev, const char *name,369 const char *parent_name, unsigned long flags,370 unsigned long fixed_rate);371/**372 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock373 * framework374 * @dev: device that is registering this clock375 * @name: name of this clock376 * @parent_name: name of clock's parent377 * @flags: framework-specific flags378 * @fixed_rate: non-adjustable clock rate379 */380#define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \381 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \382 NULL, (flags), (fixed_rate), 0, 0, false)383 384/**385 * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock386 * framework387 * @dev: device that is registering this clock388 * @name: name of this clock389 * @parent_name: name of clock's parent390 * @flags: framework-specific flags391 * @fixed_rate: non-adjustable clock rate392 */393#define devm_clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \394 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \395 NULL, (flags), (fixed_rate), 0, 0, true)396/**397 * devm_clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with398 * the clock framework399 * @dev: device that is registering this clock400 * @name: name of this clock401 * @parent_data: parent clk data402 * @flags: framework-specific flags403 * @fixed_rate: non-adjustable clock rate404 */405#define devm_clk_hw_register_fixed_rate_parent_data(dev, name, parent_data, flags, \406 fixed_rate) \407 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \408 (parent_data), (flags), (fixed_rate), 0, \409 0, true)410/**411 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with412 * the clock framework413 * @dev: device that is registering this clock414 * @name: name of this clock415 * @parent_hw: pointer to parent clk416 * @flags: framework-specific flags417 * @fixed_rate: non-adjustable clock rate418 */419#define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \420 fixed_rate) \421 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \422 NULL, (flags), (fixed_rate), 0, 0, false)423/**424 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with425 * the clock framework426 * @dev: device that is registering this clock427 * @name: name of this clock428 * @parent_data: parent clk data429 * @flags: framework-specific flags430 * @fixed_rate: non-adjustable clock rate431 */432#define clk_hw_register_fixed_rate_parent_data(dev, name, parent_data, flags, \433 fixed_rate) \434 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \435 (parent_data), (flags), (fixed_rate), 0, \436 0, false)437/**438 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with439 * the clock framework440 * @dev: device that is registering this clock441 * @name: name of this clock442 * @parent_name: name of clock's parent443 * @flags: framework-specific flags444 * @fixed_rate: non-adjustable clock rate445 * @fixed_accuracy: non-adjustable clock accuracy446 */447#define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \448 flags, fixed_rate, \449 fixed_accuracy) \450 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \451 NULL, NULL, (flags), (fixed_rate), \452 (fixed_accuracy), 0, false)453/**454 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate455 * clock with the clock framework456 * @dev: device that is registering this clock457 * @name: name of this clock458 * @parent_hw: pointer to parent clk459 * @flags: framework-specific flags460 * @fixed_rate: non-adjustable clock rate461 * @fixed_accuracy: non-adjustable clock accuracy462 */463#define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \464 parent_hw, flags, fixed_rate, fixed_accuracy) \465 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \466 NULL, (flags), (fixed_rate), \467 (fixed_accuracy), 0, false)468/**469 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate470 * clock with the clock framework471 * @dev: device that is registering this clock472 * @name: name of this clock473 * @parent_data: name of clock's parent474 * @flags: framework-specific flags475 * @fixed_rate: non-adjustable clock rate476 * @fixed_accuracy: non-adjustable clock accuracy477 */478#define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \479 parent_data, flags, fixed_rate, fixed_accuracy) \480 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \481 (parent_data), NULL, (flags), \482 (fixed_rate), (fixed_accuracy), 0, false)483/**484 * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with485 * the clock framework486 * @dev: device that is registering this clock487 * @name: name of this clock488 * @parent_data: name of clock's parent489 * @flags: framework-specific flags490 * @fixed_rate: non-adjustable clock rate491 */492#define clk_hw_register_fixed_rate_parent_accuracy(dev, name, parent_data, \493 flags, fixed_rate) \494 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \495 (parent_data), (flags), (fixed_rate), 0, \496 CLK_FIXED_RATE_PARENT_ACCURACY, false)497 498void clk_unregister_fixed_rate(struct clk *clk);499void clk_hw_unregister_fixed_rate(struct clk_hw *hw);500 501void of_fixed_clk_setup(struct device_node *np);502 503/**504 * struct clk_gate - gating clock505 *506 * @hw: handle between common and hardware-specific interfaces507 * @reg: register controlling gate508 * @bit_idx: single bit controlling gate509 * @flags: hardware-specific flags510 * @lock: register lock511 *512 * Clock which can gate its output. Implements .enable & .disable513 *514 * Flags:515 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to516 * enable the clock. Setting this flag does the opposite: setting the bit517 * disable the clock and clearing it enables the clock518 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit519 * of this register, and mask of gate bits are in higher 16-bit of this520 * register. While setting the gate bits, higher 16-bit should also be521 * updated to indicate changing gate bits.522 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for523 * the gate register. Setting this flag makes the register accesses big524 * endian.525 */526struct clk_gate {527 struct clk_hw hw;528 void __iomem *reg;529 u8 bit_idx;530 u8 flags;531 spinlock_t *lock;532};533 534#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)535 536#define CLK_GATE_SET_TO_DISABLE BIT(0)537#define CLK_GATE_HIWORD_MASK BIT(1)538#define CLK_GATE_BIG_ENDIAN BIT(2)539 540extern const struct clk_ops clk_gate_ops;541struct clk_hw *__clk_hw_register_gate(struct device *dev,542 struct device_node *np, const char *name,543 const char *parent_name, const struct clk_hw *parent_hw,544 const struct clk_parent_data *parent_data,545 unsigned long flags,546 void __iomem *reg, u8 bit_idx,547 u8 clk_gate_flags, spinlock_t *lock);548struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,549 struct device_node *np, const char *name,550 const char *parent_name, const struct clk_hw *parent_hw,551 const struct clk_parent_data *parent_data,552 unsigned long flags,553 void __iomem *reg, u8 bit_idx,554 u8 clk_gate_flags, spinlock_t *lock);555struct clk *clk_register_gate(struct device *dev, const char *name,556 const char *parent_name, unsigned long flags,557 void __iomem *reg, u8 bit_idx,558 u8 clk_gate_flags, spinlock_t *lock);559/**560 * clk_hw_register_gate - register a gate clock with the clock framework561 * @dev: device that is registering this clock562 * @name: name of this clock563 * @parent_name: name of this clock's parent564 * @flags: framework-specific flags for this clock565 * @reg: register address to control gating of this clock566 * @bit_idx: which bit in the register controls gating of this clock567 * @clk_gate_flags: gate-specific flags for this clock568 * @lock: shared register lock for this clock569 */570#define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \571 clk_gate_flags, lock) \572 __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \573 NULL, (flags), (reg), (bit_idx), \574 (clk_gate_flags), (lock))575/**576 * clk_hw_register_gate_parent_hw - register a gate clock with the clock577 * framework578 * @dev: device that is registering this clock579 * @name: name of this clock580 * @parent_hw: pointer to parent clk581 * @flags: framework-specific flags for this clock582 * @reg: register address to control gating of this clock583 * @bit_idx: which bit in the register controls gating of this clock584 * @clk_gate_flags: gate-specific flags for this clock585 * @lock: shared register lock for this clock586 */587#define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \588 bit_idx, clk_gate_flags, lock) \589 __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \590 NULL, (flags), (reg), (bit_idx), \591 (clk_gate_flags), (lock))592/**593 * clk_hw_register_gate_parent_data - register a gate clock with the clock594 * framework595 * @dev: device that is registering this clock596 * @name: name of this clock597 * @parent_data: parent clk data598 * @flags: framework-specific flags for this clock599 * @reg: register address to control gating of this clock600 * @bit_idx: which bit in the register controls gating of this clock601 * @clk_gate_flags: gate-specific flags for this clock602 * @lock: shared register lock for this clock603 */604#define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \605 bit_idx, clk_gate_flags, lock) \606 __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \607 (flags), (reg), (bit_idx), \608 (clk_gate_flags), (lock))609/**610 * devm_clk_hw_register_gate - register a gate clock with the clock framework611 * @dev: device that is registering this clock612 * @name: name of this clock613 * @parent_name: name of this clock's parent614 * @flags: framework-specific flags for this clock615 * @reg: register address to control gating of this clock616 * @bit_idx: which bit in the register controls gating of this clock617 * @clk_gate_flags: gate-specific flags for this clock618 * @lock: shared register lock for this clock619 */620#define devm_clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,\621 clk_gate_flags, lock) \622 __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \623 NULL, (flags), (reg), (bit_idx), \624 (clk_gate_flags), (lock))625/**626 * devm_clk_hw_register_gate_parent_data - register a gate clock with the627 * clock framework628 * @dev: device that is registering this clock629 * @name: name of this clock630 * @parent_data: parent clk data631 * @flags: framework-specific flags for this clock632 * @reg: register address to control gating of this clock633 * @bit_idx: which bit in the register controls gating of this clock634 * @clk_gate_flags: gate-specific flags for this clock635 * @lock: shared register lock for this clock636 */637#define devm_clk_hw_register_gate_parent_data(dev, name, parent_data, flags, \638 reg, bit_idx, clk_gate_flags, \639 lock) \640 __devm_clk_hw_register_gate((dev), NULL, (name), NULL, NULL, \641 (parent_data), (flags), (reg), (bit_idx), \642 (clk_gate_flags), (lock))643 644void clk_unregister_gate(struct clk *clk);645void clk_hw_unregister_gate(struct clk_hw *hw);646int clk_gate_is_enabled(struct clk_hw *hw);647 648struct clk_div_table {649 unsigned int val;650 unsigned int div;651};652 653/**654 * struct clk_divider - adjustable divider clock655 *656 * @hw: handle between common and hardware-specific interfaces657 * @reg: register containing the divider658 * @shift: shift to the divider bit field659 * @width: width of the divider bit field660 * @table: array of value/divider pairs, last entry should have div = 0661 * @lock: register lock662 *663 * Clock with an adjustable divider affecting its output frequency. Implements664 * .recalc_rate, .set_rate and .round_rate665 *666 * @flags:667 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the668 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is669 * the raw value read from the register, with the value of zero considered670 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.671 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from672 * the hardware register673 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have674 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.675 * Some hardware implementations gracefully handle this case and allow a676 * zero divisor by not modifying their input clock677 * (divide by one / bypass).678 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit679 * of this register, and mask of divider bits are in higher 16-bit of this680 * register. While setting the divider bits, higher 16-bit should also be681 * updated to indicate changing divider bits.682 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded683 * to the closest integer instead of the up one.684 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should685 * not be changed by the clock framework.686 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED687 * except when the value read from the register is zero, the divisor is688 * 2^width of the field.689 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used690 * for the divider register. Setting this flag makes the register accesses691 * big endian.692 */693struct clk_divider {694 struct clk_hw hw;695 void __iomem *reg;696 u8 shift;697 u8 width;698 u8 flags;699 const struct clk_div_table *table;700 spinlock_t *lock;701};702 703#define clk_div_mask(width) ((1 << (width)) - 1)704#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)705 706#define CLK_DIVIDER_ONE_BASED BIT(0)707#define CLK_DIVIDER_POWER_OF_TWO BIT(1)708#define CLK_DIVIDER_ALLOW_ZERO BIT(2)709#define CLK_DIVIDER_HIWORD_MASK BIT(3)710#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)711#define CLK_DIVIDER_READ_ONLY BIT(5)712#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)713#define CLK_DIVIDER_BIG_ENDIAN BIT(7)714 715extern const struct clk_ops clk_divider_ops;716extern const struct clk_ops clk_divider_ro_ops;717 718unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,719 unsigned int val, const struct clk_div_table *table,720 unsigned long flags, unsigned long width);721long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,722 unsigned long rate, unsigned long *prate,723 const struct clk_div_table *table,724 u8 width, unsigned long flags);725long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,726 unsigned long rate, unsigned long *prate,727 const struct clk_div_table *table, u8 width,728 unsigned long flags, unsigned int val);729int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,730 const struct clk_div_table *table, u8 width,731 unsigned long flags);732int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,733 const struct clk_div_table *table, u8 width,734 unsigned long flags, unsigned int val);735int divider_get_val(unsigned long rate, unsigned long parent_rate,736 const struct clk_div_table *table, u8 width,737 unsigned long flags);738 739struct clk_hw *__clk_hw_register_divider(struct device *dev,740 struct device_node *np, const char *name,741 const char *parent_name, const struct clk_hw *parent_hw,742 const struct clk_parent_data *parent_data, unsigned long flags,743 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,744 const struct clk_div_table *table, spinlock_t *lock);745struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,746 struct device_node *np, const char *name,747 const char *parent_name, const struct clk_hw *parent_hw,748 const struct clk_parent_data *parent_data, unsigned long flags,749 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,750 const struct clk_div_table *table, spinlock_t *lock);751struct clk *clk_register_divider_table(struct device *dev, const char *name,752 const char *parent_name, unsigned long flags,753 void __iomem *reg, u8 shift, u8 width,754 u8 clk_divider_flags, const struct clk_div_table *table,755 spinlock_t *lock);756/**757 * clk_register_divider - register a divider clock with the clock framework758 * @dev: device registering this clock759 * @name: name of this clock760 * @parent_name: name of clock's parent761 * @flags: framework-specific flags762 * @reg: register address to adjust divider763 * @shift: number of bits to shift the bitfield764 * @width: width of the bitfield765 * @clk_divider_flags: divider-specific flags for this clock766 * @lock: shared register lock for this clock767 */768#define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \769 clk_divider_flags, lock) \770 clk_register_divider_table((dev), (name), (parent_name), (flags), \771 (reg), (shift), (width), \772 (clk_divider_flags), NULL, (lock))773/**774 * clk_hw_register_divider - register a divider clock with the clock framework775 * @dev: device registering this clock776 * @name: name of this clock777 * @parent_name: name of clock's parent778 * @flags: framework-specific flags779 * @reg: register address to adjust divider780 * @shift: number of bits to shift the bitfield781 * @width: width of the bitfield782 * @clk_divider_flags: divider-specific flags for this clock783 * @lock: shared register lock for this clock784 */785#define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \786 width, clk_divider_flags, lock) \787 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \788 NULL, (flags), (reg), (shift), (width), \789 (clk_divider_flags), NULL, (lock))790/**791 * clk_hw_register_divider_parent_hw - register a divider clock with the clock792 * framework793 * @dev: device registering this clock794 * @name: name of this clock795 * @parent_hw: pointer to parent clk796 * @flags: framework-specific flags797 * @reg: register address to adjust divider798 * @shift: number of bits to shift the bitfield799 * @width: width of the bitfield800 * @clk_divider_flags: divider-specific flags for this clock801 * @lock: shared register lock for this clock802 */803#define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \804 shift, width, clk_divider_flags, \805 lock) \806 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \807 NULL, (flags), (reg), (shift), (width), \808 (clk_divider_flags), NULL, (lock))809/**810 * clk_hw_register_divider_parent_data - register a divider clock with the clock811 * framework812 * @dev: device registering this clock813 * @name: name of this clock814 * @parent_data: parent clk data815 * @flags: framework-specific flags816 * @reg: register address to adjust divider817 * @shift: number of bits to shift the bitfield818 * @width: width of the bitfield819 * @clk_divider_flags: divider-specific flags for this clock820 * @lock: shared register lock for this clock821 */822#define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \823 reg, shift, width, \824 clk_divider_flags, lock) \825 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \826 (parent_data), (flags), (reg), (shift), \827 (width), (clk_divider_flags), NULL, (lock))828/**829 * clk_hw_register_divider_table - register a table based divider clock with830 * the clock framework831 * @dev: device registering this clock832 * @name: name of this clock833 * @parent_name: name of clock's parent834 * @flags: framework-specific flags835 * @reg: register address to adjust divider836 * @shift: number of bits to shift the bitfield837 * @width: width of the bitfield838 * @clk_divider_flags: divider-specific flags for this clock839 * @table: array of divider/value pairs ending with a div set to 0840 * @lock: shared register lock for this clock841 */842#define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \843 shift, width, clk_divider_flags, table, \844 lock) \845 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \846 NULL, (flags), (reg), (shift), (width), \847 (clk_divider_flags), (table), (lock))848/**849 * clk_hw_register_divider_table_parent_hw - register a table based divider850 * clock with the clock framework851 * @dev: device registering this clock852 * @name: name of this clock853 * @parent_hw: pointer to parent clk854 * @flags: framework-specific flags855 * @reg: register address to adjust divider856 * @shift: number of bits to shift the bitfield857 * @width: width of the bitfield858 * @clk_divider_flags: divider-specific flags for this clock859 * @table: array of divider/value pairs ending with a div set to 0860 * @lock: shared register lock for this clock861 */862#define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \863 reg, shift, width, \864 clk_divider_flags, table, \865 lock) \866 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \867 NULL, (flags), (reg), (shift), (width), \868 (clk_divider_flags), (table), (lock))869/**870 * clk_hw_register_divider_table_parent_data - register a table based divider871 * clock with the clock framework872 * @dev: device registering this clock873 * @name: name of this clock874 * @parent_data: parent clk data875 * @flags: framework-specific flags876 * @reg: register address to adjust divider877 * @shift: number of bits to shift the bitfield878 * @width: width of the bitfield879 * @clk_divider_flags: divider-specific flags for this clock880 * @table: array of divider/value pairs ending with a div set to 0881 * @lock: shared register lock for this clock882 */883#define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \884 flags, reg, shift, width, \885 clk_divider_flags, table, \886 lock) \887 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \888 (parent_data), (flags), (reg), (shift), \889 (width), (clk_divider_flags), (table), \890 (lock))891/**892 * devm_clk_hw_register_divider - register a divider clock with the clock framework893 * @dev: device registering this clock894 * @name: name of this clock895 * @parent_name: name of clock's parent896 * @flags: framework-specific flags897 * @reg: register address to adjust divider898 * @shift: number of bits to shift the bitfield899 * @width: width of the bitfield900 * @clk_divider_flags: divider-specific flags for this clock901 * @lock: shared register lock for this clock902 */903#define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \904 width, clk_divider_flags, lock) \905 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \906 NULL, (flags), (reg), (shift), (width), \907 (clk_divider_flags), NULL, (lock))908/**909 * devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework910 * @dev: device registering this clock911 * @name: name of this clock912 * @parent_hw: pointer to parent clk913 * @flags: framework-specific flags914 * @reg: register address to adjust divider915 * @shift: number of bits to shift the bitfield916 * @width: width of the bitfield917 * @clk_divider_flags: divider-specific flags for this clock918 * @lock: shared register lock for this clock919 */920#define devm_clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, \921 reg, shift, width, \922 clk_divider_flags, lock) \923 __devm_clk_hw_register_divider((dev), NULL, (name), NULL, \924 (parent_hw), NULL, (flags), (reg), \925 (shift), (width), (clk_divider_flags), \926 NULL, (lock))927/**928 * devm_clk_hw_register_divider_table - register a table based divider clock929 * with the clock framework (devres variant)930 * @dev: device registering this clock931 * @name: name of this clock932 * @parent_name: name of clock's parent933 * @flags: framework-specific flags934 * @reg: register address to adjust divider935 * @shift: number of bits to shift the bitfield936 * @width: width of the bitfield937 * @clk_divider_flags: divider-specific flags for this clock938 * @table: array of divider/value pairs ending with a div set to 0939 * @lock: shared register lock for this clock940 */941#define devm_clk_hw_register_divider_table(dev, name, parent_name, flags, \942 reg, shift, width, \943 clk_divider_flags, table, lock) \944 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), \945 NULL, NULL, (flags), (reg), (shift), \946 (width), (clk_divider_flags), (table), \947 (lock))948 949void clk_unregister_divider(struct clk *clk);950void clk_hw_unregister_divider(struct clk_hw *hw);951 952/**953 * struct clk_mux - multiplexer clock954 *955 * @hw: handle between common and hardware-specific interfaces956 * @reg: register controlling multiplexer957 * @table: array of register values corresponding to the parent index958 * @shift: shift to multiplexer bit field959 * @mask: mask of mutliplexer bit field960 * @flags: hardware-specific flags961 * @lock: register lock962 *963 * Clock with multiple selectable parents. Implements .get_parent, .set_parent964 * and .recalc_rate965 *966 * Flags:967 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0968 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)969 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this970 * register, and mask of mux bits are in higher 16-bit of this register.971 * While setting the mux bits, higher 16-bit should also be updated to972 * indicate changing mux bits.973 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the974 * .get_parent clk_op.975 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired976 * frequency.977 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for978 * the mux register. Setting this flag makes the register accesses big979 * endian.980 */981struct clk_mux {982 struct clk_hw hw;983 void __iomem *reg;984 const u32 *table;985 u32 mask;986 u8 shift;987 u8 flags;988 spinlock_t *lock;989};990 991#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)992 993#define CLK_MUX_INDEX_ONE BIT(0)994#define CLK_MUX_INDEX_BIT BIT(1)995#define CLK_MUX_HIWORD_MASK BIT(2)996#define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */997#define CLK_MUX_ROUND_CLOSEST BIT(4)998#define CLK_MUX_BIG_ENDIAN BIT(5)999 1000extern const struct clk_ops clk_mux_ops;1001extern const struct clk_ops clk_mux_ro_ops;1002 1003struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,1004 const char *name, u8 num_parents,1005 const char * const *parent_names,1006 const struct clk_hw **parent_hws,1007 const struct clk_parent_data *parent_data,1008 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,1009 u8 clk_mux_flags, const u32 *table, spinlock_t *lock);1010struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np,1011 const char *name, u8 num_parents,1012 const char * const *parent_names,1013 const struct clk_hw **parent_hws,1014 const struct clk_parent_data *parent_data,1015 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,1016 u8 clk_mux_flags, const u32 *table, spinlock_t *lock);1017struct clk *clk_register_mux_table(struct device *dev, const char *name,1018 const char * const *parent_names, u8 num_parents,1019 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,1020 u8 clk_mux_flags, const u32 *table, spinlock_t *lock);1021 1022#define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \1023 shift, width, clk_mux_flags, lock) \1024 clk_register_mux_table((dev), (name), (parent_names), (num_parents), \1025 (flags), (reg), (shift), BIT((width)) - 1, \1026 (clk_mux_flags), NULL, (lock))1027#define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \1028 flags, reg, shift, mask, clk_mux_flags, \1029 table, lock) \1030 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \1031 (parent_names), NULL, NULL, (flags), (reg), \1032 (shift), (mask), (clk_mux_flags), (table), \1033 (lock))1034#define clk_hw_register_mux_table_parent_data(dev, name, parent_data, \1035 num_parents, flags, reg, shift, mask, \1036 clk_mux_flags, table, lock) \1037 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \1038 NULL, NULL, (parent_data), (flags), (reg), \1039 (shift), (mask), (clk_mux_flags), (table), \1040 (lock))1041#define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \1042 shift, width, clk_mux_flags, lock) \1043 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \1044 (parent_names), NULL, NULL, (flags), (reg), \1045 (shift), BIT((width)) - 1, (clk_mux_flags), \1046 NULL, (lock))1047#define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \1048 reg, shift, width, clk_mux_flags, lock) \1049 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \1050 (parent_hws), NULL, (flags), (reg), (shift), \1051 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))1052#define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \1053 flags, reg, shift, width, \1054 clk_mux_flags, lock) \1055 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \1056 (parent_data), (flags), (reg), (shift), \1057 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))1058#define clk_hw_register_mux_parent_data_table(dev, name, parent_data, \1059 num_parents, flags, reg, shift, \1060 width, clk_mux_flags, table, \1061 lock) \1062 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \1063 (parent_data), (flags), (reg), (shift), \1064 BIT((width)) - 1, (clk_mux_flags), table, (lock))1065#define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \1066 shift, width, clk_mux_flags, lock) \1067 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \1068 (parent_names), NULL, NULL, (flags), (reg), \1069 (shift), BIT((width)) - 1, (clk_mux_flags), \1070 NULL, (lock))1071#define devm_clk_hw_register_mux_parent_hws(dev, name, parent_hws, \1072 num_parents, flags, reg, shift, \1073 width, clk_mux_flags, lock) \1074 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \1075 (parent_hws), NULL, (flags), (reg), \1076 (shift), BIT((width)) - 1, \1077 (clk_mux_flags), NULL, (lock))1078#define devm_clk_hw_register_mux_parent_data_table(dev, name, parent_data, \1079 num_parents, flags, reg, shift, \1080 width, clk_mux_flags, table, \1081 lock) \1082 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \1083 NULL, (parent_data), (flags), (reg), (shift), \1084 BIT((width)) - 1, (clk_mux_flags), table, (lock))1085 1086int clk_mux_val_to_index(struct clk_hw *hw, const u32 *table, unsigned int flags,1087 unsigned int val);1088unsigned int clk_mux_index_to_val(const u32 *table, unsigned int flags, u8 index);1089 1090void clk_unregister_mux(struct clk *clk);1091void clk_hw_unregister_mux(struct clk_hw *hw);1092 1093void of_fixed_factor_clk_setup(struct device_node *node);1094 1095/**1096 * struct clk_fixed_factor - fixed multiplier and divider clock1097 *1098 * @hw: handle between common and hardware-specific interfaces1099 * @mult: multiplier1100 * @div: divider1101 * @acc: fixed accuracy in ppb1102 * @flags: behavior modifying flags1103 *1104 * Clock with a fixed multiplier and divider. The output frequency is the1105 * parent clock rate divided by div and multiplied by mult.1106 * Implements .recalc_rate, .set_rate, .round_rate and .recalc_accuracy1107 *1108 * Flags:1109 * * CLK_FIXED_FACTOR_FIXED_ACCURACY - Use the value in @acc instead of the1110 * parent clk accuracy.1111 */1112 1113struct clk_fixed_factor {1114 struct clk_hw hw;1115 unsigned int mult;1116 unsigned int div;1117 unsigned long acc;1118 unsigned int flags;1119};1120 1121#define CLK_FIXED_FACTOR_FIXED_ACCURACY BIT(0)1122 1123#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)1124 1125extern const struct clk_ops clk_fixed_factor_ops;1126struct clk *clk_register_fixed_factor(struct device *dev, const char *name,1127 const char *parent_name, unsigned long flags,1128 unsigned int mult, unsigned int div);1129void clk_unregister_fixed_factor(struct clk *clk);1130struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,1131 const char *name, const char *parent_name, unsigned long flags,1132 unsigned int mult, unsigned int div);1133struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev,1134 struct device_node *np, const char *name, const char *fw_name,1135 unsigned long flags, unsigned int mult, unsigned int div);1136struct clk_hw *clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev,1137 struct device_node *np, const char *name, const char *fw_name,1138 unsigned long flags, unsigned int mult, unsigned int div,1139 unsigned long acc);1140void clk_hw_unregister_fixed_factor(struct clk_hw *hw);1141struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,1142 const char *name, const char *parent_name, unsigned long flags,1143 unsigned int mult, unsigned int div);1144struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev,1145 struct device_node *np, const char *name, const char *fw_name,1146 unsigned long flags, unsigned int mult, unsigned int div);1147struct clk_hw *devm_clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev,1148 struct device_node *np, const char *name, const char *fw_name,1149 unsigned long flags, unsigned int mult, unsigned int div,1150 unsigned long acc);1151struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev,1152 const char *name, unsigned int index, unsigned long flags,1153 unsigned int mult, unsigned int div);1154 1155struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev,1156 const char *name, const struct clk_hw *parent_hw,1157 unsigned long flags, unsigned int mult, unsigned int div);1158 1159struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev,1160 const char *name, const struct clk_hw *parent_hw,1161 unsigned long flags, unsigned int mult, unsigned int div);1162/**1163 * struct clk_fractional_divider - adjustable fractional divider clock1164 *1165 * @hw: handle between common and hardware-specific interfaces1166 * @reg: register containing the divider1167 * @mshift: shift to the numerator bit field1168 * @mwidth: width of the numerator bit field1169 * @nshift: shift to the denominator bit field1170 * @nwidth: width of the denominator bit field1171 * @approximation: clk driver's callback for calculating the divider clock1172 * @lock: register lock1173 *1174 * Clock with adjustable fractional divider affecting its output frequency.1175 *1176 * @flags:1177 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator1178 * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED1179 * is set then the numerator and denominator are both the value read1180 * plus one.1181 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are1182 * used for the divider register. Setting this flag makes the register1183 * accesses big endian.1184 * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might1185 * be saturated and the caller will get quite far from the good enough1186 * approximation. Instead the caller may require, by setting this flag,1187 * to shift left by a few bits in case, when the asked one is quite small1188 * to satisfy the desired range of denominator. It assumes that on the1189 * caller's side the power-of-two capable prescaler exists.1190 */1191struct clk_fractional_divider {1192 struct clk_hw hw;1193 void __iomem *reg;1194 u8 mshift;1195 u8 mwidth;1196 u8 nshift;1197 u8 nwidth;1198 u8 flags;1199 void (*approximation)(struct clk_hw *hw,1200 unsigned long rate, unsigned long *parent_rate,1201 unsigned long *m, unsigned long *n);1202 spinlock_t *lock;1203};1204 1205#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)1206 1207#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)1208#define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)1209#define CLK_FRAC_DIVIDER_POWER_OF_TWO_PS BIT(2)1210 1211struct clk *clk_register_fractional_divider(struct device *dev,1212 const char *name, const char *parent_name, unsigned long flags,1213 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,1214 u8 clk_divider_flags, spinlock_t *lock);1215struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,1216 const char *name, const char *parent_name, unsigned long flags,1217 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,1218 u8 clk_divider_flags, spinlock_t *lock);1219void clk_hw_unregister_fractional_divider(struct clk_hw *hw);1220 1221/**1222 * struct clk_multiplier - adjustable multiplier clock1223 *1224 * @hw: handle between common and hardware-specific interfaces1225 * @reg: register containing the multiplier1226 * @shift: shift to the multiplier bit field1227 * @width: width of the multiplier bit field1228 * @lock: register lock1229 *1230 * Clock with an adjustable multiplier affecting its output frequency.1231 * Implements .recalc_rate, .set_rate and .round_rate1232 *1233 * @flags:1234 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read1235 * from the register, with 0 being a valid value effectively1236 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is1237 * set, then a null multiplier will be considered as a bypass,1238 * leaving the parent rate unmodified.1239 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be1240 * rounded to the closest integer instead of the down one.1241 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are1242 * used for the multiplier register. Setting this flag makes the register1243 * accesses big endian.1244 */1245struct clk_multiplier {1246 struct clk_hw hw;1247 void __iomem *reg;1248 u8 shift;1249 u8 width;1250 u8 flags;1251 spinlock_t *lock;1252};1253 1254#define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)1255 1256#define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)1257#define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)1258#define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)1259 1260extern const struct clk_ops clk_multiplier_ops;1261 1262/***1263 * struct clk_composite - aggregate clock of mux, divider and gate clocks1264 *1265 * @hw: handle between common and hardware-specific interfaces1266 * @mux_hw: handle between composite and hardware-specific mux clock1267 * @rate_hw: handle between composite and hardware-specific rate clock1268 * @gate_hw: handle between composite and hardware-specific gate clock1269 * @mux_ops: clock ops for mux1270 * @rate_ops: clock ops for rate1271 * @gate_ops: clock ops for gate1272 */1273struct clk_composite {1274 struct clk_hw hw;1275 struct clk_ops ops;1276 1277 struct clk_hw *mux_hw;1278 struct clk_hw *rate_hw;1279 struct clk_hw *gate_hw;1280 1281 const struct clk_ops *mux_ops;1282 const struct clk_ops *rate_ops;1283 const struct clk_ops *gate_ops;1284};1285 1286#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)1287 1288struct clk *clk_register_composite(struct device *dev, const char *name,1289 const char * const *parent_names, int num_parents,1290 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,1291 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,1292 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,1293 unsigned long flags);1294struct clk *clk_register_composite_pdata(struct device *dev, const char *name,1295 const struct clk_parent_data *parent_data, int num_parents,1296 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,1297 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,1298 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,1299 unsigned long flags);1300void clk_unregister_composite(struct clk *clk);1301struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,1302 const char * const *parent_names, int num_parents,1303 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,1304 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,1305 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,1306 unsigned long flags);1307struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,1308 const char *name,1309 const struct clk_parent_data *parent_data, int num_parents,1310 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,1311 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,1312 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,1313 unsigned long flags);1314struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev,1315 const char *name, const struct clk_parent_data *parent_data,1316 int num_parents,1317 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,1318 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,1319 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,1320 unsigned long flags);1321void clk_hw_unregister_composite(struct clk_hw *hw);1322 1323struct clk *clk_register(struct device *dev, struct clk_hw *hw) HWJS_SUSPENDS;1324struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw) HWJS_SUSPENDS;1325 1326int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw) HWJS_SUSPENDS;1327int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw) HWJS_SUSPENDS;1328int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw) HWJS_SUSPENDS;1329 1330void clk_unregister(struct clk *clk) HWJS_SUSPENDS;1331 1332void clk_hw_unregister(struct clk_hw *hw) HWJS_SUSPENDS;1333 1334/* helper functions */1335const char *__clk_get_name(const struct clk *clk);1336const char *clk_hw_get_name(const struct clk_hw *hw);1337#ifdef CONFIG_COMMON_CLK1338struct clk_hw *__clk_get_hw(struct clk *clk);1339#else1340static inline struct clk_hw *__clk_get_hw(struct clk *clk)1341{1342 return (struct clk_hw *)clk;1343}1344#endif1345 1346struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id);1347struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,1348 const char *con_id) HWJS_SUSPENDS;1349 1350unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);1351struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);1352struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,1353 unsigned int index);1354int clk_hw_get_parent_index(struct clk_hw *hw);1355int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent) HWJS_SUSPENDS;1356unsigned int __clk_get_enable_count(struct clk *clk);1357unsigned long clk_hw_get_rate(const struct clk_hw *hw);1358unsigned long clk_hw_get_flags(const struct clk_hw *hw);1359#define clk_hw_can_set_rate_parent(hw) \1360 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)1361 1362bool clk_hw_is_prepared(const struct clk_hw *hw);1363bool clk_hw_rate_is_protected(const struct clk_hw *hw);1364bool clk_hw_is_enabled(const struct clk_hw *hw);1365bool __clk_is_enabled(struct clk *clk);1366struct clk *__clk_lookup(const char *name);1367int __clk_mux_determine_rate(struct clk_hw *hw,1368 struct clk_rate_request *req);1369int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);1370int __clk_mux_determine_rate_closest(struct clk_hw *hw,1371 struct clk_rate_request *req);1372int clk_mux_determine_rate_flags(struct clk_hw *hw,1373 struct clk_rate_request *req,1374 unsigned long flags);1375int clk_hw_determine_rate_no_reparent(struct clk_hw *hw,1376 struct clk_rate_request *req);1377void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);1378void clk_hw_get_rate_range(struct clk_hw *hw, unsigned long *min_rate,1379 unsigned long *max_rate);1380void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,1381 unsigned long max_rate);1382 1383static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)1384{1385 dst->clk = src->clk;1386 dst->core = src->core;1387}1388 1389static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,1390 unsigned long *prate,1391 const struct clk_div_table *table,1392 u8 width, unsigned long flags)1393{1394 return divider_round_rate_parent(hw, clk_hw_get_parent(hw),1395 rate, prate, table, width, flags);1396}1397 1398static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,1399 unsigned long *prate,1400 const struct clk_div_table *table,1401 u8 width, unsigned long flags,1402 unsigned int val)1403{1404 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),1405 rate, prate, table, width, flags,1406 val);1407}1408 1409/*1410 * FIXME clock api without lock protection1411 */1412unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);1413 1414struct clk_onecell_data {1415 struct clk **clks;1416 unsigned int clk_num;1417};1418 1419struct clk_hw_onecell_data {1420 unsigned int num;1421 struct clk_hw *hws[] __counted_by(num);1422};1423 1424#define CLK_OF_DECLARE(name, compat, fn) \1425 static void __init __##name##_of_clk_init_declare(struct device_node *np) \1426 { \1427 fn(np); \1428 fwnode_dev_initialized(of_fwnode_handle(np), true); \1429 } \1430 OF_DECLARE_1(clk, name, compat, __##name##_of_clk_init_declare)1431 1432/*1433 * Use this macro when you have a driver that requires two initialization1434 * routines, one at of_clk_init(), and one at platform device probe1435 */1436#define CLK_OF_DECLARE_DRIVER(name, compat, fn) \1437 static void __init name##_of_clk_init_driver(struct device_node *np) \1438 { \1439 of_node_clear_flag(np, OF_POPULATED); \1440 fn(np); \1441 } \1442 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)1443 1444#define CLK_HW_INIT(_name, _parent, _ops, _flags) \1445 (&(struct clk_init_data) { \1446 .flags = _flags, \1447 .name = _name, \1448 .parent_names = (const char *[]) { _parent }, \1449 .num_parents = 1, \1450 .ops = _ops, \1451 })1452 1453#define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \1454 (&(struct clk_init_data) { \1455 .flags = _flags, \1456 .name = _name, \1457 .parent_hws = (const struct clk_hw*[]) { _parent }, \1458 .num_parents = 1, \1459 .ops = _ops, \1460 })1461 1462/*1463 * This macro is intended for drivers to be able to share the otherwise1464 * individual struct clk_hw[] compound literals created by the compiler1465 * when using CLK_HW_INIT_HW. It does NOT support multiple parents.1466 */1467#define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \1468 (&(struct clk_init_data) { \1469 .flags = _flags, \1470 .name = _name, \1471 .parent_hws = _parent, \1472 .num_parents = 1, \1473 .ops = _ops, \1474 })1475 1476#define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \1477 (&(struct clk_init_data) { \1478 .flags = _flags, \1479 .name = _name, \1480 .parent_data = (const struct clk_parent_data[]) { \1481 { .fw_name = _parent }, \1482 }, \1483 .num_parents = 1, \1484 .ops = _ops, \1485 })1486 1487#define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \1488 (&(struct clk_init_data) { \1489 .flags = _flags, \1490 .name = _name, \1491 .parent_names = _parents, \1492 .num_parents = ARRAY_SIZE(_parents), \1493 .ops = _ops, \1494 })1495 1496#define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \1497 (&(struct clk_init_data) { \1498 .flags = _flags, \1499 .name = _name, \1500 .parent_hws = _parents, \1501 .num_parents = ARRAY_SIZE(_parents), \1502 .ops = _ops, \1503 })1504 1505#define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \1506 (&(struct clk_init_data) { \1507 .flags = _flags, \1508 .name = _name, \1509 .parent_data = _parents, \1510 .num_parents = ARRAY_SIZE(_parents), \1511 .ops = _ops, \1512 })1513 1514#define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \1515 (&(struct clk_init_data) { \1516 .flags = _flags, \1517 .name = _name, \1518 .parent_names = NULL, \1519 .num_parents = 0, \1520 .ops = _ops, \1521 })1522 1523#define CLK_FIXED_FACTOR(_struct, _name, _parent, \1524 _div, _mult, _flags) \1525 struct clk_fixed_factor _struct = { \1526 .div = _div, \1527 .mult = _mult, \1528 .hw.init = CLK_HW_INIT(_name, \1529 _parent, \1530 &clk_fixed_factor_ops, \1531 _flags), \1532 }1533 1534#define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \1535 _div, _mult, _flags) \1536 struct clk_fixed_factor _struct = { \1537 .div = _div, \1538 .mult = _mult, \1539 .hw.init = CLK_HW_INIT_HW(_name, \1540 _parent, \1541 &clk_fixed_factor_ops, \1542 _flags), \1543 }1544 1545/*1546 * This macro allows the driver to reuse the _parent array for multiple1547 * fixed factor clk declarations.1548 */1549#define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \1550 _div, _mult, _flags) \1551 struct clk_fixed_factor _struct = { \1552 .div = _div, \1553 .mult = _mult, \1554 .hw.init = CLK_HW_INIT_HWS(_name, \1555 _parent, \1556 &clk_fixed_factor_ops, \1557 _flags), \1558 }1559 1560#define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \1561 _div, _mult, _flags) \1562 struct clk_fixed_factor _struct = { \1563 .div = _div, \1564 .mult = _mult, \1565 .hw.init = CLK_HW_INIT_FW_NAME(_name, \1566 _parent, \1567 &clk_fixed_factor_ops, \1568 _flags), \1569 }1570 1571#ifdef CONFIG_OF1572int of_clk_add_provider(struct device_node *np,1573 struct clk *(*clk_src_get)(struct of_phandle_args *args,1574 void *data),1575 void *data);1576int of_clk_add_hw_provider(struct device_node *np,1577 struct clk_hw *(*get)(struct of_phandle_args *clkspec,1578 void *data),1579 void *data);1580int devm_of_clk_add_hw_provider(struct device *dev,1581 struct clk_hw *(*get)(struct of_phandle_args *clkspec,1582 void *data),1583 void *data);1584void of_clk_del_provider(struct device_node *np);1585 1586struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,1587 void *data);1588struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,1589 void *data);1590struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);1591struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,1592 void *data);1593int of_clk_parent_fill(struct device_node *np, const char **parents,1594 unsigned int size);1595int of_clk_detect_critical(struct device_node *np, int index,1596 unsigned long *flags);1597 1598#else /* !CONFIG_OF */1599 1600static inline int of_clk_add_provider(struct device_node *np,1601 struct clk *(*clk_src_get)(struct of_phandle_args *args,1602 void *data),1603 void *data)1604{1605 return 0;1606}1607static inline int of_clk_add_hw_provider(struct device_node *np,1608 struct clk_hw *(*get)(struct of_phandle_args *clkspec,1609 void *data),1610 void *data)1611{1612 return 0;1613}1614static inline int devm_of_clk_add_hw_provider(struct device *dev,1615 struct clk_hw *(*get)(struct of_phandle_args *clkspec,1616 void *data),1617 void *data)1618{1619 return 0;1620}1621static inline void of_clk_del_provider(struct device_node *np) {}1622 1623static inline struct clk *of_clk_src_simple_get(1624 struct of_phandle_args *clkspec, void *data)1625{1626 return ERR_PTR(-ENOENT);1627}1628static inline struct clk_hw *1629of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)1630{1631 return ERR_PTR(-ENOENT);1632}1633static inline struct clk *of_clk_src_onecell_get(1634 struct of_phandle_args *clkspec, void *data)1635{1636 return ERR_PTR(-ENOENT);1637}1638static inline struct clk_hw *1639of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)1640{1641 return ERR_PTR(-ENOENT);1642}1643static inline int of_clk_parent_fill(struct device_node *np,1644 const char **parents, unsigned int size)1645{1646 return 0;1647}1648static inline int of_clk_detect_critical(struct device_node *np, int index,1649 unsigned long *flags)1650{1651 return 0;1652}1653#endif /* CONFIG_OF */1654 1655void clk_gate_restore_context(struct clk_hw *hw);1656 1657#endif /* CLK_PROVIDER_H */1658