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1/* SPDX-License-Identifier: GPL-2.0 OR MIT */2/*3 * MTK SDG1 ECC controller4 *5 * Copyright (c) 2016 Mediatek6 * Authors: Xiaolei Li <xiaolei.li@mediatek.com>7 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>8 */9 10#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__11#define __DRIVERS_MTD_NAND_MTK_ECC_H__12 13#include <linux/types.h>14 15enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1};16enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE};17 18struct device_node;19struct mtk_ecc;20 21struct mtk_ecc_stats {22 u32 corrected;23 u32 bitflips;24 u32 failed;25};26 27struct mtk_ecc_config {28 enum mtk_ecc_operation op;29 enum mtk_ecc_mode mode;30 dma_addr_t addr;31 u32 strength;32 u32 sectors;33 u32 len;34};35 36int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32);37void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int);38int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation);39int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *);40void mtk_ecc_disable(struct mtk_ecc *);41void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p);42unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc);43 44struct mtk_ecc *of_mtk_ecc_get(struct device_node *);45void mtk_ecc_release(struct mtk_ecc *);46 47#endif48