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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * MV-643XX ethernet platform device data definition file.4 */5 6#ifndef __LINUX_MV643XX_ETH_H7#define __LINUX_MV643XX_ETH_H8 9#include <linux/mbus.h>10#include <linux/if_ether.h>11#include <linux/phy.h>12 13#define MV643XX_ETH_SHARED_NAME "mv643xx_eth"14#define MV643XX_ETH_NAME "mv643xx_eth_port"15#define MV643XX_ETH_SHARED_REGS 0x200016#define MV643XX_ETH_SHARED_REGS_SIZE 0x200017#define MV643XX_ETH_BAR_4 0x222018#define MV643XX_ETH_SIZE_REG_4 0x222419#define MV643XX_ETH_BASE_ADDR_ENABLE_REG 0x229020 21#define MV643XX_TX_CSUM_DEFAULT_LIMIT 022 23struct mv643xx_eth_shared_platform_data {24 struct mbus_dram_target_info *dram;25 /*26 * Max packet size for Tx IP/Layer 4 checksum, when set to 0, default27 * limit of 9KiB will be used.28 */29 int tx_csum_limit;30};31 32#define MV643XX_ETH_PHY_ADDR_DEFAULT 033#define MV643XX_ETH_PHY_ADDR(x) (0x80 | (x))34#define MV643XX_ETH_PHY_NONE 0xff35 36struct device_node;37struct mv643xx_eth_platform_data {38 /*39 * Pointer back to our parent instance, and our port number.40 */41 struct platform_device *shared;42 int port_number;43 44 /*45 * Whether a PHY is present, and if yes, at which address.46 */47 int phy_addr;48 struct device_node *phy_node;49 50 /*51 * Use this MAC address if it is valid, overriding the52 * address that is already in the hardware.53 */54 u8 mac_addr[ETH_ALEN];55 56 /*57 * If speed is 0, autonegotiation is enabled.58 * Valid values for speed: 0, SPEED_10, SPEED_100, SPEED_1000.59 * Valid values for duplex: DUPLEX_HALF, DUPLEX_FULL.60 */61 int speed;62 int duplex;63 phy_interface_t interface;64 65 /*66 * How many RX/TX queues to use.67 */68 int rx_queue_count;69 int tx_queue_count;70 71 /*72 * Override default RX/TX queue sizes if nonzero.73 */74 int rx_queue_size;75 int tx_queue_size;76 77 /*78 * Use on-chip SRAM for RX/TX descriptors if size is nonzero79 * and sufficient to contain all descriptors for the requested80 * ring sizes.81 */82 unsigned long rx_sram_addr;83 int rx_sram_size;84 unsigned long tx_sram_addr;85 int tx_sram_size;86};87 88 89#endif90