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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * cisreg.h4 *5 * The initial developer of the original code is David A. Hinds6 * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds7 * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.8 *9 * (C) 1999 David A. Hinds10 */11 12#ifndef _LINUX_CISREG_H13#define _LINUX_CISREG_H14 15/*16 * Offsets from ConfigBase for CIS registers17 */18#define CISREG_COR 0x0019#define CISREG_CCSR 0x0220#define CISREG_PRR 0x0421#define CISREG_SCR 0x0622#define CISREG_ESR 0x0823#define CISREG_IOBASE_0 0x0a24#define CISREG_IOBASE_1 0x0c25#define CISREG_IOBASE_2 0x0e26#define CISREG_IOBASE_3 0x1027#define CISREG_IOSIZE 0x1228 29/*30 * Configuration Option Register31 */32#define COR_CONFIG_MASK 0x3f33#define COR_MFC_CONFIG_MASK 0x3834#define COR_FUNC_ENA 0x0135#define COR_ADDR_DECODE 0x0236#define COR_IREQ_ENA 0x0437#define COR_LEVEL_REQ 0x4038#define COR_SOFT_RESET 0x8039 40/*41 * Card Configuration and Status Register42 */43#define CCSR_INTR_ACK 0x0144#define CCSR_INTR_PENDING 0x0245#define CCSR_POWER_DOWN 0x0446#define CCSR_AUDIO_ENA 0x0847#define CCSR_IOIS8 0x2048#define CCSR_SIGCHG_ENA 0x4049#define CCSR_CHANGED 0x8050 51/*52 * Pin Replacement Register53 */54#define PRR_WP_STATUS 0x0155#define PRR_READY_STATUS 0x0256#define PRR_BVD2_STATUS 0x0457#define PRR_BVD1_STATUS 0x0858#define PRR_WP_EVENT 0x1059#define PRR_READY_EVENT 0x2060#define PRR_BVD2_EVENT 0x4061#define PRR_BVD1_EVENT 0x8062 63/*64 * Socket and Copy Register65 */66#define SCR_SOCKET_NUM 0x0f67#define SCR_COPY_NUM 0x7068 69/*70 * Extended Status Register71 */72#define ESR_REQ_ATTN_ENA 0x0173#define ESR_REQ_ATTN 0x1074 75/*76 * CardBus Function Status Registers77 */78#define CBFN_EVENT 0x0079#define CBFN_MASK 0x0480#define CBFN_STATE 0x0881#define CBFN_FORCE 0x0c82 83/*84 * These apply to all the CardBus function registers85 */86#define CBFN_WP 0x000187#define CBFN_READY 0x000288#define CBFN_BVD2 0x000489#define CBFN_BVD1 0x000890#define CBFN_GWAKE 0x001091#define CBFN_INTR 0x800092 93/*94 * Extra bits in the Function Event Mask Register95 */96#define FEMR_BAM_ENA 0x002097#define FEMR_PWM_ENA 0x004098#define FEMR_WKUP_MASK 0x400099 100/*101 * Indirect Addressing Registers for Zoomed Video: these are addresses102 * in common memory space103 */104#define CISREG_ICTRL0 0x02 /* control registers */105#define CISREG_ICTRL1 0x03106#define CISREG_IADDR0 0x04 /* address registers */107#define CISREG_IADDR1 0x05108#define CISREG_IADDR2 0x06109#define CISREG_IADDR3 0x07110#define CISREG_IDATA0 0x08 /* data registers */111#define CISREG_IDATA1 0x09112 113#define ICTRL0_COMMON 0x01114#define ICTRL0_AUTOINC 0x02115#define ICTRL0_BYTEGRAN 0x04116 117#endif /* _LINUX_CISREG_H */118