134 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * ARConnect IP Support (Multi core enabler: Cross core IPI, RTC ...)4 *5 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)6 */7 8#ifndef __SOC_ARC_MCIP_H9#define __SOC_ARC_MCIP_H10 11#include <soc/arc/aux.h>12 13#define ARC_REG_MCIP_BCR 0x0d014#define ARC_REG_MCIP_IDU_BCR 0x0D515#define ARC_REG_GFRC_BUILD 0x0D616#define ARC_REG_MCIP_CMD 0x60017#define ARC_REG_MCIP_WDATA 0x60118#define ARC_REG_MCIP_READBACK 0x60219 20struct mcip_cmd {21#ifdef CONFIG_CPU_BIG_ENDIAN22 unsigned int pad:8, param:16, cmd:8;23#else24 unsigned int cmd:8, param:16, pad:8;25#endif26 27#define CMD_INTRPT_GENERATE_IRQ 0x0128#define CMD_INTRPT_GENERATE_ACK 0x0229#define CMD_INTRPT_READ_STATUS 0x0330#define CMD_INTRPT_CHECK_SOURCE 0x0431 32/* Semaphore Commands */33#define CMD_SEMA_CLAIM_AND_READ 0x1134#define CMD_SEMA_RELEASE 0x1235 36#define CMD_DEBUG_SET_MASK 0x3437#define CMD_DEBUG_READ_MASK 0x3538#define CMD_DEBUG_SET_SELECT 0x3639#define CMD_DEBUG_READ_SELECT 0x3740 41#define CMD_GFRC_READ_LO 0x4242#define CMD_GFRC_READ_HI 0x4343#define CMD_GFRC_SET_CORE 0x4744#define CMD_GFRC_READ_CORE 0x4845 46#define CMD_IDU_ENABLE 0x7147#define CMD_IDU_DISABLE 0x7248#define CMD_IDU_SET_MODE 0x7449#define CMD_IDU_READ_MODE 0x7550#define CMD_IDU_SET_DEST 0x7651#define CMD_IDU_ACK_CIRQ 0x7952#define CMD_IDU_SET_MASK 0x7C53 54#define IDU_M_TRIG_LEVEL 0x055#define IDU_M_TRIG_EDGE 0x156 57#define IDU_M_DISTRI_RR 0x058#define IDU_M_DISTRI_DEST 0x259};60 61struct mcip_bcr {62#ifdef CONFIG_CPU_BIG_ENDIAN63 unsigned int pad4:6, pw_dom:1, pad3:1,64 idu:1, pad2:1, num_cores:6,65 pad:1, gfrc:1, dbg:1, pw:1,66 msg:1, sem:1, ipi:1, slv:1,67 ver:8;68#else69 unsigned int ver:8,70 slv:1, ipi:1, sem:1, msg:1,71 pw:1, dbg:1, gfrc:1, pad:1,72 num_cores:6, pad2:1, idu:1,73 pad3:1, pw_dom:1, pad4:6;74#endif75};76 77struct mcip_idu_bcr {78#ifdef CONFIG_CPU_BIG_ENDIAN79 unsigned int pad:21, cirqnum:3, ver:8;80#else81 unsigned int ver:8, cirqnum:3, pad:21;82#endif83};84 85 86/*87 * Build register for IDU contains not an actual number of supported common88 * interrupts but an exponent of 2 which must be multiplied by 4 to89 * get a number of supported common interrupts.90 */91#define mcip_idu_bcr_to_nr_irqs(bcr) (4 * (1 << (bcr).cirqnum))92 93/*94 * MCIP programming model95 *96 * - Simple commands write {cmd:8,param:16} to MCIP_CMD aux reg97 * (param could be irq, common_irq, core_id ...)98 * - More involved commands setup MCIP_WDATA with cmd specific data99 * before invoking the simple command100 */101static inline void __mcip_cmd(unsigned int cmd, unsigned int param)102{103 struct mcip_cmd buf;104 105 buf.pad = 0;106 buf.cmd = cmd;107 buf.param = param;108 109 WRITE_AUX(ARC_REG_MCIP_CMD, buf);110}111 112/*113 * Setup additional data for a cmd114 * Callers need to lock to ensure atomicity115 */116static inline void __mcip_cmd_data(unsigned int cmd, unsigned int param,117 unsigned int data)118{119 write_aux_reg(ARC_REG_MCIP_WDATA, data);120 121 __mcip_cmd(cmd, param);122}123 124/*125 * Read MCIP register126 */127static inline unsigned int __mcip_cmd_read(unsigned int cmd, unsigned int param)128{129 __mcip_cmd(cmd, param);130 return read_aux_reg(ARC_REG_MCIP_READBACK);131}132 133#endif134