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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * arch/arm/mach-at91/include/mach/at91sam9_sdramc.h4 *5 * Copyright (C) 2007 Andrew Victor6 * Copyright (C) 2007 Atmel Corporation.7 *8 * SDRAM Controllers (SDRAMC) - System peripherals registers.9 * Based on AT91SAM9261 datasheet revision D.10 */11 12#ifndef AT91SAM9_SDRAMC_H13#define AT91SAM9_SDRAMC_H14 15/* SDRAM Controller (SDRAMC) registers */16#define AT91_SDRAMC_MR 0x00 /* SDRAM Controller Mode Register */17#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */18#define AT91_SDRAMC_MODE_NORMAL 019#define AT91_SDRAMC_MODE_NOP 120#define AT91_SDRAMC_MODE_PRECHARGE 221#define AT91_SDRAMC_MODE_LMR 322#define AT91_SDRAMC_MODE_REFRESH 423#define AT91_SDRAMC_MODE_EXT_LMR 524#define AT91_SDRAMC_MODE_DEEP 625 26#define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */27#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */28 29#define AT91_SDRAMC_CR 0x08 /* SDRAM Controller Configuration Register */30#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */31#define AT91_SDRAMC_NC_8 (0 << 0)32#define AT91_SDRAMC_NC_9 (1 << 0)33#define AT91_SDRAMC_NC_10 (2 << 0)34#define AT91_SDRAMC_NC_11 (3 << 0)35#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */36#define AT91_SDRAMC_NR_11 (0 << 2)37#define AT91_SDRAMC_NR_12 (1 << 2)38#define AT91_SDRAMC_NR_13 (2 << 2)39#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */40#define AT91_SDRAMC_NB_2 (0 << 4)41#define AT91_SDRAMC_NB_4 (1 << 4)42#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */43#define AT91_SDRAMC_CAS_1 (1 << 5)44#define AT91_SDRAMC_CAS_2 (2 << 5)45#define AT91_SDRAMC_CAS_3 (3 << 5)46#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */47#define AT91_SDRAMC_DBW_32 (0 << 7)48#define AT91_SDRAMC_DBW_16 (1 << 7)49#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */50#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */51#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */52#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */53#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */54#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */55 56#define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */57#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */58#define AT91_SDRAMC_LPCB_DISABLE 059#define AT91_SDRAMC_LPCB_SELF_REFRESH 160#define AT91_SDRAMC_LPCB_POWER_DOWN 261#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 362#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */63#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */64#define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */65#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */66#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)67#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)68#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)69 70#define AT91_SDRAMC_IER 0x14 /* SDRAM Controller Interrupt Enable Register */71#define AT91_SDRAMC_IDR 0x18 /* SDRAM Controller Interrupt Disable Register */72#define AT91_SDRAMC_IMR 0x1C /* SDRAM Controller Interrupt Mask Register */73#define AT91_SDRAMC_ISR 0x20 /* SDRAM Controller Interrupt Status Register */74#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */75 76#define AT91_SDRAMC_MDR 0x24 /* SDRAM Memory Device Register */77#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */78#define AT91_SDRAMC_MD_SDRAM 079#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 180 81#endif82