52 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Atmel SFR (Special Function Registers) register offsets and bit definitions.4 *5 * Copyright (C) 2016 Atmel6 *7 * Author: Ludovic Desroches <ludovic.desroches@atmel.com>8 */9 10#ifndef _LINUX_MFD_SYSCON_ATMEL_SFR_H11#define _LINUX_MFD_SYSCON_ATMEL_SFR_H12 13#define AT91_SFR_DDRCFG 0x04 /* DDR Configuration Register */14#define AT91_SFR_CCFG_EBICSA 0x04 /* EBI Chip Select Register */15/* 0x08 ~ 0x0c: Reserved */16#define AT91_SFR_OHCIICR 0x10 /* OHCI INT Configuration Register */17#define AT91_SFR_OHCIISR 0x14 /* OHCI INT Status Register */18#define AT91_SFR_UTMICKTRIM 0x30 /* UTMI Clock Trimming Register */19#define AT91_SFR_UTMISWAP 0x3c /* UTMI DP/DM Pin Swapping Register */20#define AT91_SFR_LS 0x7c /* Light Sleep Register */21#define AT91_SFR_I2SCLKSEL 0x90 /* I2SC Register */22#define AT91_SFR_WPMR 0xe4 /* Write Protection Mode Register */23 24/* Field definitions */25#define AT91_SFR_CCFG_EBI_CSA(cs, val) ((val) << (cs))26#define AT91_SFR_CCFG_EBI_DBPUC BIT(8)27#define AT91_SFR_CCFG_EBI_DBPDC BIT(9)28#define AT91_SFR_CCFG_EBI_DRIVE BIT(17)29#define AT91_SFR_CCFG_NFD0_ON_D16 BIT(24)30#define AT91_SFR_CCFG_DDR_MP_EN BIT(25)31 32#define AT91_SFR_OHCIICR_RES(x) BIT(x)33#define AT91_SFR_OHCIICR_ARIE BIT(4)34#define AT91_SFR_OHCIICR_APPSTART BIT(5)35#define AT91_SFR_OHCIICR_USB_SUSP(x) BIT(8 + (x))36#define AT91_SFR_OHCIICR_UDPPUDIS BIT(23)37#define AT91_OHCIICR_USB_SUSPEND GENMASK(10, 8)38 39#define AT91_SFR_OHCIISR_RIS(x) BIT(x)40 41#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0)42 43#define AT91_SFR_UTMISWAP_PORT(x) BIT(x)44 45#define AT91_SFR_LS_VALUE(x) BIT(x)46#define AT91_SFR_LS_MEM_POWER_GATING_ULP1_EN BIT(16)47 48#define AT91_SFR_WPMR_WPEN BIT(0)49#define AT91_SFR_WPMR_WPKEY_MASK GENMASK(31, 8)50 51#endif /* _LINUX_MFD_SYSCON_ATMEL_SFR_H */52