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1/*2 * Timer/Counter Unit (TC) registers.3 *4 * This program is free software; you can redistribute it and/or modify5 * it under the terms of the GNU General Public License as published by6 * the Free Software Foundation; either version 2 of the License, or7 * (at your option) any later version.8 */9 10#ifndef __SOC_ATMEL_TCB_H11#define __SOC_ATMEL_TCB_H12 13#include <linux/compiler.h>14#include <linux/list.h>15 16/*17 * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds18 * three general-purpose 16-bit timers. These timers share one register bank.19 * Depending on the SOC, each timer may have its own clock and IRQ, or those20 * may be shared by the whole TC block.21 *22 * These TC blocks may have up to nine external pins: TCLK0..2 signals for23 * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM24 * or triggering. Those pins need to be set up for use with the TC block,25 * else they will be used as GPIOs or for a different controller.26 *27 * Although we expect each TC block to have a platform_device node, those28 * nodes are not what drivers bind to. Instead, they ask for a specific29 * TC block, by number ... which is a common approach on systems with many30 * timers. Then they use clk_get() and platform_get_irq() to get clock and31 * IRQ resources.32 */33 34struct clk;35 36/**37 * struct atmel_tcb_config - SoC data for a Timer/Counter Block38 * @counter_width: size in bits of a timer counter register39 * @has_gclk: boolean indicating if a timer counter has a generic clock40 * @has_qdec: boolean indicating if a timer counter has a quadrature41 * decoder.42 */43struct atmel_tcb_config {44 size_t counter_width;45 bool has_gclk;46 bool has_qdec;47};48 49/**50 * struct atmel_tc - information about a Timer/Counter Block51 * @pdev: physical device52 * @regs: mapping through which the I/O registers can be accessed53 * @id: block id54 * @tcb_config: configuration data from SoC55 * @irq: irq for each of the three channels56 * @clk: internal clock source for each of the three channels57 * @node: list node, for tclib internal use58 * @allocated: if already used, for tclib internal use59 *60 * On some platforms, each TC channel has its own clocks and IRQs,61 * while on others, all TC channels share the same clock and IRQ.62 * Drivers should clk_enable() all the clocks they need even though63 * all the entries in @clk may point to the same physical clock.64 * Likewise, drivers should request irqs independently for each65 * channel, but they must use IRQF_SHARED in case some of the entries66 * in @irq are actually the same IRQ.67 */68struct atmel_tc {69 struct platform_device *pdev;70 void __iomem *regs;71 int id;72 const struct atmel_tcb_config *tcb_config;73 int irq[3];74 struct clk *clk[3];75 struct clk *slow_clk;76 struct list_head node;77 bool allocated;78};79 80/* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */81extern const u8 atmel_tc_divisors[5];82 83 84/*85 * Two registers have block-wide controls. These are: configuring the three86 * "external" clocks (or event sources) used by the timer channels; and87 * synchronizing the timers by resetting them all at once.88 *89 * "External" can mean "external to chip" using the TCLK0, TCLK1, or TCLK290 * signals. Or, it can mean "external to timer", using the TIOA output from91 * one of the other two timers that's being run in waveform mode.92 */93 94#define ATMEL_TC_BCR 0xc0 /* TC Block Control Register */95#define ATMEL_TC_SYNC (1 << 0) /* synchronize timers */96 97#define ATMEL_TC_BMR 0xc4 /* TC Block Mode Register */98#define ATMEL_TC_TC0XC0S (3 << 0) /* external clock 0 source */99#define ATMEL_TC_TC0XC0S_TCLK0 (0 << 0)100#define ATMEL_TC_TC0XC0S_NONE (1 << 0)101#define ATMEL_TC_TC0XC0S_TIOA1 (2 << 0)102#define ATMEL_TC_TC0XC0S_TIOA2 (3 << 0)103#define ATMEL_TC_TC1XC1S (3 << 2) /* external clock 1 source */104#define ATMEL_TC_TC1XC1S_TCLK1 (0 << 2)105#define ATMEL_TC_TC1XC1S_NONE (1 << 2)106#define ATMEL_TC_TC1XC1S_TIOA0 (2 << 2)107#define ATMEL_TC_TC1XC1S_TIOA2 (3 << 2)108#define ATMEL_TC_TC2XC2S (3 << 4) /* external clock 2 source */109#define ATMEL_TC_TC2XC2S_TCLK2 (0 << 4)110#define ATMEL_TC_TC2XC2S_NONE (1 << 4)111#define ATMEL_TC_TC2XC2S_TIOA0 (2 << 4)112#define ATMEL_TC_TC2XC2S_TIOA1 (3 << 4)113 114 115/*116 * Each TC block has three "channels", each with one counter and controls.117 *118 * Note that the semantics of ATMEL_TC_TIMER_CLOCKx (input clock selection119 * when it's not "external") is silicon-specific. AT91 platforms use one120 * set of definitions; AVR32 platforms use a different set. Don't hard-wire121 * such knowledge into your code, use the global "atmel_tc_divisors" ...122 * where index N is the divisor for clock N+1, else zero to indicate it uses123 * the 32 KiHz clock.124 *125 * The timers can be chained in various ways, and operated in "waveform"126 * generation mode (including PWM) or "capture" mode (to time events). In127 * both modes, behavior can be configured in many ways.128 *129 * Each timer has two I/O pins, TIOA and TIOB. Waveform mode uses TIOA as a130 * PWM output, and TIOB as either another PWM or as a trigger. Capture mode131 * uses them only as inputs.132 */133#define ATMEL_TC_CHAN(idx) ((idx)*0x40)134#define ATMEL_TC_REG(idx, reg) (ATMEL_TC_CHAN(idx) + ATMEL_TC_ ## reg)135 136#define ATMEL_TC_CCR 0x00 /* Channel Control Register */137#define ATMEL_TC_CLKEN (1 << 0) /* clock enable */138#define ATMEL_TC_CLKDIS (1 << 1) /* clock disable */139#define ATMEL_TC_SWTRG (1 << 2) /* software trigger */140 141#define ATMEL_TC_CMR 0x04 /* Channel Mode Register */142 143/* Both modes share some CMR bits */144#define ATMEL_TC_TCCLKS (7 << 0) /* clock source */145#define ATMEL_TC_TIMER_CLOCK1 (0 << 0)146#define ATMEL_TC_TIMER_CLOCK2 (1 << 0)147#define ATMEL_TC_TIMER_CLOCK3 (2 << 0)148#define ATMEL_TC_TIMER_CLOCK4 (3 << 0)149#define ATMEL_TC_TIMER_CLOCK5 (4 << 0)150#define ATMEL_TC_XC0 (5 << 0)151#define ATMEL_TC_XC1 (6 << 0)152#define ATMEL_TC_XC2 (7 << 0)153#define ATMEL_TC_CLKI (1 << 3) /* clock invert */154#define ATMEL_TC_BURST (3 << 4) /* clock gating */155#define ATMEL_TC_GATE_NONE (0 << 4)156#define ATMEL_TC_GATE_XC0 (1 << 4)157#define ATMEL_TC_GATE_XC1 (2 << 4)158#define ATMEL_TC_GATE_XC2 (3 << 4)159#define ATMEL_TC_WAVE (1 << 15) /* true = Waveform mode */160 161/* CAPTURE mode CMR bits */162#define ATMEL_TC_LDBSTOP (1 << 6) /* counter stops on RB load */163#define ATMEL_TC_LDBDIS (1 << 7) /* counter disable on RB load */164#define ATMEL_TC_ETRGEDG (3 << 8) /* external trigger edge */165#define ATMEL_TC_ETRGEDG_NONE (0 << 8)166#define ATMEL_TC_ETRGEDG_RISING (1 << 8)167#define ATMEL_TC_ETRGEDG_FALLING (2 << 8)168#define ATMEL_TC_ETRGEDG_BOTH (3 << 8)169#define ATMEL_TC_ABETRG (1 << 10) /* external trigger is TIOA? */170#define ATMEL_TC_CPCTRG (1 << 14) /* RC compare trigger enable */171#define ATMEL_TC_LDRA (3 << 16) /* RA loading edge (of TIOA) */172#define ATMEL_TC_LDRA_NONE (0 << 16)173#define ATMEL_TC_LDRA_RISING (1 << 16)174#define ATMEL_TC_LDRA_FALLING (2 << 16)175#define ATMEL_TC_LDRA_BOTH (3 << 16)176#define ATMEL_TC_LDRB (3 << 18) /* RB loading edge (of TIOA) */177#define ATMEL_TC_LDRB_NONE (0 << 18)178#define ATMEL_TC_LDRB_RISING (1 << 18)179#define ATMEL_TC_LDRB_FALLING (2 << 18)180#define ATMEL_TC_LDRB_BOTH (3 << 18)181 182/* WAVEFORM mode CMR bits */183#define ATMEL_TC_CPCSTOP (1 << 6) /* RC compare stops counter */184#define ATMEL_TC_CPCDIS (1 << 7) /* RC compare disables counter */185#define ATMEL_TC_EEVTEDG (3 << 8) /* external event edge */186#define ATMEL_TC_EEVTEDG_NONE (0 << 8)187#define ATMEL_TC_EEVTEDG_RISING (1 << 8)188#define ATMEL_TC_EEVTEDG_FALLING (2 << 8)189#define ATMEL_TC_EEVTEDG_BOTH (3 << 8)190#define ATMEL_TC_EEVT (3 << 10) /* external event source */191#define ATMEL_TC_EEVT_TIOB (0 << 10)192#define ATMEL_TC_EEVT_XC0 (1 << 10)193#define ATMEL_TC_EEVT_XC1 (2 << 10)194#define ATMEL_TC_EEVT_XC2 (3 << 10)195#define ATMEL_TC_ENETRG (1 << 12) /* external event is trigger */196#define ATMEL_TC_WAVESEL (3 << 13) /* waveform type */197#define ATMEL_TC_WAVESEL_UP (0 << 13)198#define ATMEL_TC_WAVESEL_UPDOWN (1 << 13)199#define ATMEL_TC_WAVESEL_UP_AUTO (2 << 13)200#define ATMEL_TC_WAVESEL_UPDOWN_AUTO (3 << 13)201#define ATMEL_TC_ACPA (3 << 16) /* RA compare changes TIOA */202#define ATMEL_TC_ACPA_NONE (0 << 16)203#define ATMEL_TC_ACPA_SET (1 << 16)204#define ATMEL_TC_ACPA_CLEAR (2 << 16)205#define ATMEL_TC_ACPA_TOGGLE (3 << 16)206#define ATMEL_TC_ACPC (3 << 18) /* RC compare changes TIOA */207#define ATMEL_TC_ACPC_NONE (0 << 18)208#define ATMEL_TC_ACPC_SET (1 << 18)209#define ATMEL_TC_ACPC_CLEAR (2 << 18)210#define ATMEL_TC_ACPC_TOGGLE (3 << 18)211#define ATMEL_TC_AEEVT (3 << 20) /* external event changes TIOA */212#define ATMEL_TC_AEEVT_NONE (0 << 20)213#define ATMEL_TC_AEEVT_SET (1 << 20)214#define ATMEL_TC_AEEVT_CLEAR (2 << 20)215#define ATMEL_TC_AEEVT_TOGGLE (3 << 20)216#define ATMEL_TC_ASWTRG (3 << 22) /* software trigger changes TIOA */217#define ATMEL_TC_ASWTRG_NONE (0 << 22)218#define ATMEL_TC_ASWTRG_SET (1 << 22)219#define ATMEL_TC_ASWTRG_CLEAR (2 << 22)220#define ATMEL_TC_ASWTRG_TOGGLE (3 << 22)221#define ATMEL_TC_BCPB (3 << 24) /* RB compare changes TIOB */222#define ATMEL_TC_BCPB_NONE (0 << 24)223#define ATMEL_TC_BCPB_SET (1 << 24)224#define ATMEL_TC_BCPB_CLEAR (2 << 24)225#define ATMEL_TC_BCPB_TOGGLE (3 << 24)226#define ATMEL_TC_BCPC (3 << 26) /* RC compare changes TIOB */227#define ATMEL_TC_BCPC_NONE (0 << 26)228#define ATMEL_TC_BCPC_SET (1 << 26)229#define ATMEL_TC_BCPC_CLEAR (2 << 26)230#define ATMEL_TC_BCPC_TOGGLE (3 << 26)231#define ATMEL_TC_BEEVT (3 << 28) /* external event changes TIOB */232#define ATMEL_TC_BEEVT_NONE (0 << 28)233#define ATMEL_TC_BEEVT_SET (1 << 28)234#define ATMEL_TC_BEEVT_CLEAR (2 << 28)235#define ATMEL_TC_BEEVT_TOGGLE (3 << 28)236#define ATMEL_TC_BSWTRG (3 << 30) /* software trigger changes TIOB */237#define ATMEL_TC_BSWTRG_NONE (0 << 30)238#define ATMEL_TC_BSWTRG_SET (1 << 30)239#define ATMEL_TC_BSWTRG_CLEAR (2 << 30)240#define ATMEL_TC_BSWTRG_TOGGLE (3 << 30)241 242#define ATMEL_TC_CV 0x10 /* counter Value */243#define ATMEL_TC_RA 0x14 /* register A */244#define ATMEL_TC_RB 0x18 /* register B */245#define ATMEL_TC_RC 0x1c /* register C */246 247#define ATMEL_TC_SR 0x20 /* status (read-only) */248/* Status-only flags */249#define ATMEL_TC_CLKSTA (1 << 16) /* clock enabled */250#define ATMEL_TC_MTIOA (1 << 17) /* TIOA mirror */251#define ATMEL_TC_MTIOB (1 << 18) /* TIOB mirror */252 253#define ATMEL_TC_IER 0x24 /* interrupt enable (write-only) */254#define ATMEL_TC_IDR 0x28 /* interrupt disable (write-only) */255#define ATMEL_TC_IMR 0x2c /* interrupt mask (read-only) */256 257/* Status and IRQ flags */258#define ATMEL_TC_COVFS (1 << 0) /* counter overflow */259#define ATMEL_TC_LOVRS (1 << 1) /* load overrun */260#define ATMEL_TC_CPAS (1 << 2) /* RA compare */261#define ATMEL_TC_CPBS (1 << 3) /* RB compare */262#define ATMEL_TC_CPCS (1 << 4) /* RC compare */263#define ATMEL_TC_LDRAS (1 << 5) /* RA loading */264#define ATMEL_TC_LDRBS (1 << 6) /* RB loading */265#define ATMEL_TC_ETRGS (1 << 7) /* external trigger */266#define ATMEL_TC_ALL_IRQ (ATMEL_TC_COVFS | ATMEL_TC_LOVRS | \267 ATMEL_TC_CPAS | ATMEL_TC_CPBS | \268 ATMEL_TC_CPCS | ATMEL_TC_LDRAS | \269 ATMEL_TC_LDRBS | ATMEL_TC_ETRGS) \270 /* all IRQs */271 272#endif273