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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Microchip SAMA7 UDDR Controller and DDR3 PHY Controller registers offsets4 * and bit definitions.5 *6 * Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries7 *8 * Author: Claudu Beznea <claudiu.beznea@microchip.com>9 */10 11#ifndef __SAMA7_DDR_H__12#define __SAMA7_DDR_H__13 14/* DDR3PHY */15#define DDR3PHY_PIR (0x04) /* DDR3PHY PHY Initialization Register */16#define DDR3PHY_PIR_DLLBYP (1 << 17) /* DLL Bypass */17#define DDR3PHY_PIR_ITMSRST (1 << 4) /* Interface Timing Module Soft Reset */18#define DDR3PHY_PIR_DLLLOCK (1 << 2) /* DLL Lock */19#define DDR3PHY_PIR_DLLSRST (1 << 1) /* DLL Soft Rest */20#define DDR3PHY_PIR_INIT (1 << 0) /* Initialization Trigger */21 22#define DDR3PHY_PGCR (0x08) /* DDR3PHY PHY General Configuration Register */23#define DDR3PHY_PGCR_CKDV1 (1 << 13) /* CK# Disable Value */24#define DDR3PHY_PGCR_CKDV0 (1 << 12) /* CK Disable Value */25 26#define DDR3PHY_PGSR (0x0C) /* DDR3PHY PHY General Status Register */27#define DDR3PHY_PGSR_IDONE (1 << 0) /* Initialization Done */28 29#define DDR3PHY_ACDLLCR (0x14) /* DDR3PHY AC DLL Control Register */30#define DDR3PHY_ACDLLCR_DLLSRST (1 << 30) /* DLL Soft Reset */31 32#define DDR3PHY_ACIOCR (0x24) /* DDR3PHY AC I/O Configuration Register */33#define DDR3PHY_ACIOCR_CSPDD_CS0 (1 << 18) /* CS#[0] Power Down Driver */34#define DDR3PHY_ACIOCR_CKPDD_CK0 (1 << 8) /* CK[0] Power Down Driver */35#define DDR3PHY_ACIORC_ACPDD (1 << 3) /* AC Power Down Driver */36 37#define DDR3PHY_DXCCR (0x28) /* DDR3PHY DATX8 Common Configuration Register */38#define DDR3PHY_DXCCR_DXPDR (1 << 3) /* Data Power Down Receiver */39 40#define DDR3PHY_DSGCR (0x2C) /* DDR3PHY DDR System General Configuration Register */41#define DDR3PHY_DSGCR_ODTPDD_ODT0 (1 << 20) /* ODT[0] Power Down Driver */42 43#define DDR3PHY_ZQ0SR0 (0x188) /* ZQ status register 0 */44#define DDR3PHY_ZQ0SR0_PDO_OFF (0) /* Pull-down output impedance select offset */45#define DDR3PHY_ZQ0SR0_PUO_OFF (5) /* Pull-up output impedance select offset */46#define DDR3PHY_ZQ0SR0_PDODT_OFF (10) /* Pull-down on-die termination impedance select offset */47#define DDR3PHY_ZQ0SRO_PUODT_OFF (15) /* Pull-up on-die termination impedance select offset */48 49#define DDR3PHY_DX0DLLCR (0x1CC) /* DDR3PHY DATX8 DLL Control Register */50#define DDR3PHY_DX1DLLCR (0x20C) /* DDR3PHY DATX8 DLL Control Register */51#define DDR3PHY_DXDLLCR_DLLDIS (1 << 31) /* DLL Disable */52 53/* UDDRC */54#define UDDRC_STAT (0x04) /* UDDRC Operating Mode Status Register */55#define UDDRC_STAT_SELFREF_TYPE_DIS (0x0 << 4) /* SDRAM is not in Self-refresh */56#define UDDRC_STAT_SELFREF_TYPE_PHY (0x1 << 4) /* SDRAM is in Self-refresh, which was caused by PHY Master Request */57#define UDDRC_STAT_SELFREF_TYPE_SW (0x2 << 4) /* SDRAM is in Self-refresh, which was not caused solely under Automatic Self-refresh control */58#define UDDRC_STAT_SELFREF_TYPE_AUTO (0x3 << 4) /* SDRAM is in Self-refresh, which was caused by Automatic Self-refresh only */59#define UDDRC_STAT_SELFREF_TYPE_MSK (0x3 << 4) /* Self-refresh type mask */60#define UDDRC_STAT_OPMODE_INIT (0x0 << 0) /* Init */61#define UDDRC_STAT_OPMODE_NORMAL (0x1 << 0) /* Normal */62#define UDDRC_STAT_OPMODE_PWRDOWN (0x2 << 0) /* Power-down */63#define UDDRC_STAT_OPMODE_SELF_REFRESH (0x3 << 0) /* Self-refresh */64#define UDDRC_STAT_OPMODE_MSK (0x7 << 0) /* Operating mode mask */65 66#define UDDRC_PWRCTL (0x30) /* UDDRC Low Power Control Register */67#define UDDRC_PWRCTL_SELFREF_EN (1 << 0) /* Automatic self-refresh */68#define UDDRC_PWRCTL_SELFREF_SW (1 << 5) /* Software self-refresh */69 70#define UDDRC_DFIMISC (0x1B0) /* UDDRC DFI Miscellaneous Control Register */71#define UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN (1 << 0) /* PHY initialization complete enable signal */72 73#define UDDRC_SWCTRL (0x320) /* UDDRC Software Register Programming Control Enable */74#define UDDRC_SWCTRL_SW_DONE (1 << 0) /* Enable quasi-dynamic register programming outside reset */75 76#define UDDRC_SWSTAT (0x324) /* UDDRC Software Register Programming Control Status */77#define UDDRC_SWSTAT_SW_DONE_ACK (1 << 0) /* Register programming done */78 79#define UDDRC_PSTAT (0x3FC) /* UDDRC Port Status Register */80#define UDDRC_PSTAT_ALL_PORTS (0x1F001F) /* Read + writes outstanding transactions on all ports */81 82#define UDDRC_PCTRL_0 (0x490) /* UDDRC Port 0 Control Register */83#define UDDRC_PCTRL_1 (0x540) /* UDDRC Port 1 Control Register */84#define UDDRC_PCTRL_2 (0x5F0) /* UDDRC Port 2 Control Register */85#define UDDRC_PCTRL_3 (0x6A0) /* UDDRC Port 3 Control Register */86#define UDDRC_PCTRL_4 (0x750) /* UDDRC Port 4 Control Register */87 88#endif /* __SAMA7_DDR_H__ */89