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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.4 *5 * Authors: Shlomi Gridish <gridish@freescale.com>6 * Li Yang <leoli@freescale.com>7 *8 * Description:9 * QUICC Engine (QE) external definitions and structure.10 */11#ifndef _ASM_POWERPC_QE_H12#define _ASM_POWERPC_QE_H13#ifdef __KERNEL__14 15#include <linux/compiler.h>16#include <linux/genalloc.h>17#include <linux/spinlock.h>18#include <linux/errno.h>19#include <linux/err.h>20#include <soc/fsl/cpm.h>21#include <soc/fsl/qe/immap_qe.h>22#include <linux/of.h>23#include <linux/of_address.h>24#include <linux/types.h>25 26struct device;27 28#define QE_NUM_OF_SNUM 256 /* There are 256 serial number in QE */29#define QE_NUM_OF_BRGS 1630#define QE_NUM_OF_PORTS 102431 32/* Clocks and BRGs */33enum qe_clock {34 QE_CLK_NONE = 0,35 QE_BRG1, /* Baud Rate Generator 1 */36 QE_BRG2, /* Baud Rate Generator 2 */37 QE_BRG3, /* Baud Rate Generator 3 */38 QE_BRG4, /* Baud Rate Generator 4 */39 QE_BRG5, /* Baud Rate Generator 5 */40 QE_BRG6, /* Baud Rate Generator 6 */41 QE_BRG7, /* Baud Rate Generator 7 */42 QE_BRG8, /* Baud Rate Generator 8 */43 QE_BRG9, /* Baud Rate Generator 9 */44 QE_BRG10, /* Baud Rate Generator 10 */45 QE_BRG11, /* Baud Rate Generator 11 */46 QE_BRG12, /* Baud Rate Generator 12 */47 QE_BRG13, /* Baud Rate Generator 13 */48 QE_BRG14, /* Baud Rate Generator 14 */49 QE_BRG15, /* Baud Rate Generator 15 */50 QE_BRG16, /* Baud Rate Generator 16 */51 QE_CLK1, /* Clock 1 */52 QE_CLK2, /* Clock 2 */53 QE_CLK3, /* Clock 3 */54 QE_CLK4, /* Clock 4 */55 QE_CLK5, /* Clock 5 */56 QE_CLK6, /* Clock 6 */57 QE_CLK7, /* Clock 7 */58 QE_CLK8, /* Clock 8 */59 QE_CLK9, /* Clock 9 */60 QE_CLK10, /* Clock 10 */61 QE_CLK11, /* Clock 11 */62 QE_CLK12, /* Clock 12 */63 QE_CLK13, /* Clock 13 */64 QE_CLK14, /* Clock 14 */65 QE_CLK15, /* Clock 15 */66 QE_CLK16, /* Clock 16 */67 QE_CLK17, /* Clock 17 */68 QE_CLK18, /* Clock 18 */69 QE_CLK19, /* Clock 19 */70 QE_CLK20, /* Clock 20 */71 QE_CLK21, /* Clock 21 */72 QE_CLK22, /* Clock 22 */73 QE_CLK23, /* Clock 23 */74 QE_CLK24, /* Clock 24 */75 QE_RSYNC_PIN, /* RSYNC from pin */76 QE_TSYNC_PIN, /* TSYNC from pin */77 QE_CLK_DUMMY78};79 80static inline bool qe_clock_is_brg(enum qe_clock clk)81{82 return clk >= QE_BRG1 && clk <= QE_BRG16;83}84 85extern spinlock_t cmxgcr_lock;86 87/* Export QE common operations */88#ifdef CONFIG_QUICC_ENGINE89extern void qe_reset(void);90#else91static inline void qe_reset(void) {}92#endif93 94int cpm_muram_init(void);95 96#if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE)97s32 cpm_muram_alloc(unsigned long size, unsigned long align);98s32 devm_cpm_muram_alloc(struct device *dev, unsigned long size,99 unsigned long align);100void cpm_muram_free(s32 offset);101s32 cpm_muram_alloc_fixed(unsigned long offset, unsigned long size);102s32 devm_cpm_muram_alloc_fixed(struct device *dev, unsigned long offset,103 unsigned long size);104void __iomem *cpm_muram_addr(unsigned long offset);105unsigned long cpm_muram_offset(const void __iomem *addr);106dma_addr_t cpm_muram_dma(void __iomem *addr);107void cpm_muram_free_addr(const void __iomem *addr);108#else109static inline s32 cpm_muram_alloc(unsigned long size,110 unsigned long align)111{112 return -ENOSYS;113}114 115static inline s32 devm_cpm_muram_alloc(struct device *dev, unsigned long size,116 unsigned long align)117{118 return -ENOSYS;119}120 121static inline void cpm_muram_free(s32 offset)122{123}124 125static inline s32 cpm_muram_alloc_fixed(unsigned long offset,126 unsigned long size)127{128 return -ENOSYS;129}130 131static inline s32 devm_cpm_muram_alloc_fixed(struct device *dev,132 unsigned long offset,133 unsigned long size)134{135 return -ENOSYS;136}137 138static inline void __iomem *cpm_muram_addr(unsigned long offset)139{140 return NULL;141}142 143static inline unsigned long cpm_muram_offset(const void __iomem *addr)144{145 return -ENOSYS;146}147 148static inline dma_addr_t cpm_muram_dma(void __iomem *addr)149{150 return 0;151}152static inline void cpm_muram_free_addr(const void __iomem *addr)153{154}155#endif /* defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) */156 157/* QE PIO */158#define QE_PIO_PINS 32159 160struct qe_pio_regs {161 __be32 cpodr; /* Open drain register */162 __be32 cpdata; /* Data register */163 __be32 cpdir1; /* Direction register */164 __be32 cpdir2; /* Direction register */165 __be32 cppar1; /* Pin assignment register */166 __be32 cppar2; /* Pin assignment register */167#ifdef CONFIG_PPC_85xx168 u8 pad[8];169#endif170};171 172#define QE_PIO_DIR_IN 2173#define QE_PIO_DIR_OUT 1174extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin,175 int dir, int open_drain, int assignment,176 int has_irq);177#ifdef CONFIG_QUICC_ENGINE178extern int par_io_init(struct device_node *np);179extern int par_io_of_config(struct device_node *np);180extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,181 int assignment, int has_irq);182extern int par_io_data_set(u8 port, u8 pin, u8 val);183#else184static inline int par_io_init(struct device_node *np) { return -ENOSYS; }185static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; }186static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,187 int assignment, int has_irq) { return -ENOSYS; }188static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; }189#endif /* CONFIG_QUICC_ENGINE */190 191/*192 * Pin multiplexing functions.193 */194struct qe_pin;195#ifdef CONFIG_QE_GPIO196extern struct qe_pin *qe_pin_request(struct device *dev, int index);197extern void qe_pin_free(struct qe_pin *qe_pin);198extern void qe_pin_set_gpio(struct qe_pin *qe_pin);199extern void qe_pin_set_dedicated(struct qe_pin *pin);200#else201static inline struct qe_pin *qe_pin_request(struct device *dev, int index)202{203 return ERR_PTR(-ENOSYS);204}205static inline void qe_pin_free(struct qe_pin *qe_pin) {}206static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {}207static inline void qe_pin_set_dedicated(struct qe_pin *pin) {}208#endif /* CONFIG_QE_GPIO */209 210#ifdef CONFIG_QUICC_ENGINE211int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);212#else213static inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol,214 u32 cmd_input)215{216 return -ENOSYS;217}218#endif /* CONFIG_QUICC_ENGINE */219 220/* QE internal API */221enum qe_clock qe_clock_source(const char *source);222unsigned int qe_get_brg_clk(void);223int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);224int qe_get_snum(void);225void qe_put_snum(u8 snum);226unsigned int qe_get_num_of_risc(void);227unsigned int qe_get_num_of_snums(void);228 229static inline int qe_alive_during_sleep(void)230{231 /*232 * MPC8568E reference manual says:233 *234 * "...power down sequence waits for all I/O interfaces to become idle.235 * In some applications this may happen eventually without actively236 * shutting down interfaces, but most likely, software will have to237 * take steps to shut down the eTSEC, QUICC Engine Block, and PCI238 * interfaces before issuing the command (either the write to the core239 * MSR[WE] as described above or writing to POWMGTCSR) to put the240 * device into sleep state."241 *242 * MPC8569E reference manual has a similar paragraph.243 */244#ifdef CONFIG_PPC_85xx245 return 0;246#else247 return 1;248#endif249}250 251/* we actually use cpm_muram implementation, define this for convenience */252#define qe_muram_init cpm_muram_init253#define qe_muram_alloc cpm_muram_alloc254#define devm_qe_muram_alloc devm_cpm_muram_alloc255#define qe_muram_alloc_fixed cpm_muram_alloc_fixed256#define devm_qe_muram_alloc_fixed devm_cpm_muram_alloc_fixed257#define qe_muram_free cpm_muram_free258#define qe_muram_addr cpm_muram_addr259#define qe_muram_offset cpm_muram_offset260#define qe_muram_dma cpm_muram_dma261#define qe_muram_free_addr cpm_muram_free_addr262 263#define qe_setbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr))264#define qe_clrbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))265 266#define qe_setbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr))267#define qe_clrbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))268 269#define qe_setbits_8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr))270#define qe_clrbits_8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))271 272#define qe_clrsetbits_be32(addr, clear, set) \273 iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))274#define qe_clrsetbits_be16(addr, clear, set) \275 iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))276#define qe_clrsetbits_8(addr, clear, set) \277 iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))278 279/* Structure that defines QE firmware binary files.280 *281 * See Documentation/arch/powerpc/qe_firmware.rst for a description of these282 * fields.283 */284struct qe_firmware {285 struct qe_header {286 __be32 length; /* Length of the entire structure, in bytes */287 u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */288 u8 version; /* Version of this layout. First ver is '1' */289 } header;290 u8 id[62]; /* Null-terminated identifier string */291 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */292 u8 count; /* Number of microcode[] structures */293 struct {294 __be16 model; /* The SOC model */295 u8 major; /* The SOC revision major */296 u8 minor; /* The SOC revision minor */297 } __attribute__ ((packed)) soc;298 u8 padding[4]; /* Reserved, for alignment */299 __be64 extended_modes; /* Extended modes */300 __be32 vtraps[8]; /* Virtual trap addresses */301 u8 reserved[4]; /* Reserved, for future expansion */302 struct qe_microcode {303 u8 id[32]; /* Null-terminated identifier */304 __be32 traps[16]; /* Trap addresses, 0 == ignore */305 __be32 eccr; /* The value for the ECCR register */306 __be32 iram_offset; /* Offset into I-RAM for the code */307 __be32 count; /* Number of 32-bit words of the code */308 __be32 code_offset; /* Offset of the actual microcode */309 u8 major; /* The microcode version major */310 u8 minor; /* The microcode version minor */311 u8 revision; /* The microcode version revision */312 u8 padding; /* Reserved, for alignment */313 u8 reserved[4]; /* Reserved, for future expansion */314 } __packed microcode[];315 /* All microcode binaries should be located here */316 /* CRC32 should be located here, after the microcode binaries */317} __attribute__ ((packed));318 319struct qe_firmware_info {320 char id[64]; /* Firmware name */321 u32 vtraps[8]; /* Virtual trap addresses */322 u64 extended_modes; /* Extended modes */323};324 325#ifdef CONFIG_QUICC_ENGINE326/* Upload a firmware to the QE */327int qe_upload_firmware(const struct qe_firmware *firmware);328#else329static inline int qe_upload_firmware(const struct qe_firmware *firmware)330{331 return -ENOSYS;332}333#endif /* CONFIG_QUICC_ENGINE */334 335/* Obtain information on the uploaded firmware */336struct qe_firmware_info *qe_get_firmware_info(void);337 338/* QE USB */339int qe_usb_clock_set(enum qe_clock clk, int rate);340 341/* Buffer descriptors */342struct qe_bd {343 __be16 status;344 __be16 length;345 __be32 buf;346} __attribute__ ((packed));347 348#define BD_STATUS_MASK 0xffff0000349#define BD_LENGTH_MASK 0x0000ffff350 351/* Alignment */352#define QE_INTR_TABLE_ALIGN 16 /* ??? */353#define QE_ALIGNMENT_OF_BD 8354#define QE_ALIGNMENT_OF_PRAM 64355 356/* RISC allocation */357#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */358#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */359#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */360#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */361#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \362 QE_RISC_ALLOCATION_RISC2)363#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \364 QE_RISC_ALLOCATION_RISC2 | \365 QE_RISC_ALLOCATION_RISC3 | \366 QE_RISC_ALLOCATION_RISC4)367 368/* QE extended filtering Table Lookup Key Size */369enum qe_fltr_tbl_lookup_key_size {370 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES371 = 0x3f, /* LookupKey parsed by the Generate LookupKey372 CMD is truncated to 8 bytes */373 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES374 = 0x5f, /* LookupKey parsed by the Generate LookupKey375 CMD is truncated to 16 bytes */376};377 378/* QE FLTR extended filtering Largest External Table Lookup Key Size */379enum qe_fltr_largest_external_tbl_lookup_key_size {380 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE381 = 0x0,/* not used */382 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES383 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */384 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES385 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */386};387 388/* structure representing QE parameter RAM */389struct qe_timer_tables {390 u16 tm_base; /* QE timer table base adr */391 u16 tm_ptr; /* QE timer table pointer */392 u16 r_tmr; /* QE timer mode register */393 u16 r_tmv; /* QE timer valid register */394 u32 tm_cmd; /* QE timer cmd register */395 u32 tm_cnt; /* QE timer internal cnt */396} __attribute__ ((packed));397 398#define QE_FLTR_TAD_SIZE 8399 400/* QE extended filtering Termination Action Descriptor (TAD) */401struct qe_fltr_tad {402 u8 serialized[QE_FLTR_TAD_SIZE];403} __attribute__ ((packed));404 405/* Communication Direction */406enum comm_dir {407 COMM_DIR_NONE = 0,408 COMM_DIR_RX = 1,409 COMM_DIR_TX = 2,410 COMM_DIR_RX_AND_TX = 3411};412 413/* QE CMXUCR Registers.414 * There are two UCCs represented in each of the four CMXUCR registers.415 * These values are for the UCC in the LSBs416 */417#define QE_CMXUCR_MII_ENET_MNG 0x00007000418#define QE_CMXUCR_MII_ENET_MNG_SHIFT 12419#define QE_CMXUCR_GRANT 0x00008000420#define QE_CMXUCR_TSA 0x00004000421#define QE_CMXUCR_BKPT 0x00000100422#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F423 424/* QE CMXGCR Registers.425*/426#define QE_CMXGCR_MII_ENET_MNG 0x00007000427#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12428#define QE_CMXGCR_USBCS 0x0000000f429#define QE_CMXGCR_USBCS_CLK3 0x1430#define QE_CMXGCR_USBCS_CLK5 0x2431#define QE_CMXGCR_USBCS_CLK7 0x3432#define QE_CMXGCR_USBCS_CLK9 0x4433#define QE_CMXGCR_USBCS_CLK13 0x5434#define QE_CMXGCR_USBCS_CLK17 0x6435#define QE_CMXGCR_USBCS_CLK19 0x7436#define QE_CMXGCR_USBCS_CLK21 0x8437#define QE_CMXGCR_USBCS_BRG9 0x9438#define QE_CMXGCR_USBCS_BRG10 0xa439 440/* QE CECR Commands.441*/442#define QE_CR_FLG 0x00010000443#define QE_RESET 0x80000000444#define QE_INIT_TX_RX 0x00000000445#define QE_INIT_RX 0x00000001446#define QE_INIT_TX 0x00000002447#define QE_ENTER_HUNT_MODE 0x00000003448#define QE_STOP_TX 0x00000004449#define QE_GRACEFUL_STOP_TX 0x00000005450#define QE_RESTART_TX 0x00000006451#define QE_CLOSE_RX_BD 0x00000007452#define QE_SWITCH_COMMAND 0x00000007453#define QE_SET_GROUP_ADDRESS 0x00000008454#define QE_START_IDMA 0x00000009455#define QE_MCC_STOP_RX 0x00000009456#define QE_ATM_TRANSMIT 0x0000000a457#define QE_HPAC_CLEAR_ALL 0x0000000b458#define QE_GRACEFUL_STOP_RX 0x0000001a459#define QE_RESTART_RX 0x0000001b460#define QE_HPAC_SET_PRIORITY 0x0000010b461#define QE_HPAC_STOP_TX 0x0000020b462#define QE_HPAC_STOP_RX 0x0000030b463#define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b464#define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b465#define QE_HPAC_START_TX 0x0000060b466#define QE_HPAC_START_RX 0x0000070b467#define QE_USB_STOP_TX 0x0000000a468#define QE_USB_RESTART_TX 0x0000000c469#define QE_QMC_STOP_TX 0x0000000c470#define QE_QMC_STOP_RX 0x0000000d471#define QE_SS7_SU_FIL_RESET 0x0000000e472#define QE_PUSHSCHED 0x0000000f473/* jonathbr added from here down for 83xx */474#define QE_RESET_BCS 0x0000000a475#define QE_MCC_INIT_TX_RX_16 0x00000003476#define QE_MCC_STOP_TX 0x00000004477#define QE_MCC_INIT_TX_1 0x00000005478#define QE_MCC_INIT_RX_1 0x00000006479#define QE_MCC_RESET 0x00000007480#define QE_SET_TIMER 0x00000008481#define QE_RANDOM_NUMBER 0x0000000c482#define QE_ATM_MULTI_THREAD_INIT 0x00000011483#define QE_ASSIGN_PAGE 0x00000012484#define QE_ADD_REMOVE_HASH_ENTRY 0x00000013485#define QE_START_FLOW_CONTROL 0x00000014486#define QE_STOP_FLOW_CONTROL 0x00000015487#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016488 489#define QE_ASSIGN_RISC 0x00000010490#define QE_CR_MCN_NORMAL_SHIFT 6491#define QE_CR_MCN_USB_SHIFT 4492#define QE_CR_MCN_RISC_ASSIGN_SHIFT 8493#define QE_CR_SNUM_SHIFT 17494 495/* QE CECR Sub Block - sub block of QE command.496*/497#define QE_CR_SUBBLOCK_INVALID 0x00000000498#define QE_CR_SUBBLOCK_USB 0x03200000499#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000500#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000501#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000502#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000503#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000504#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000505#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000506#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000507#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000508#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000509#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000510#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000511#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000512#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000513#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000514#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000515#define QE_CR_SUBBLOCK_MCC1 0x03800000516#define QE_CR_SUBBLOCK_MCC2 0x03a00000517#define QE_CR_SUBBLOCK_MCC3 0x03000000518#define QE_CR_SUBBLOCK_IDMA1 0x02800000519#define QE_CR_SUBBLOCK_IDMA2 0x02a00000520#define QE_CR_SUBBLOCK_IDMA3 0x02c00000521#define QE_CR_SUBBLOCK_IDMA4 0x02e00000522#define QE_CR_SUBBLOCK_HPAC 0x01e00000523#define QE_CR_SUBBLOCK_SPI1 0x01400000524#define QE_CR_SUBBLOCK_SPI2 0x01600000525#define QE_CR_SUBBLOCK_RAND 0x01c00000526#define QE_CR_SUBBLOCK_TIMER 0x01e00000527#define QE_CR_SUBBLOCK_GENERAL 0x03c00000528 529/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */530#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */531#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00532#define QE_CR_PROTOCOL_QMC 0x02533#define QE_CR_PROTOCOL_UART 0x04534#define QE_CR_PROTOCOL_ATM_POS 0x0A535#define QE_CR_PROTOCOL_ETHERNET 0x0C536#define QE_CR_PROTOCOL_L2_SWITCH 0x0D537 538/* BRG configuration register */539#define QE_BRGC_ENABLE 0x00010000540#define QE_BRGC_DIVISOR_SHIFT 1541#define QE_BRGC_DIVISOR_MAX 0xFFF542#define QE_BRGC_DIV16 1543 544/* QE Timers registers */545#define QE_GTCFR1_PCAS 0x80546#define QE_GTCFR1_STP2 0x20547#define QE_GTCFR1_RST2 0x10548#define QE_GTCFR1_GM2 0x08549#define QE_GTCFR1_GM1 0x04550#define QE_GTCFR1_STP1 0x02551#define QE_GTCFR1_RST1 0x01552 553/* SDMA registers */554#define QE_SDSR_BER1 0x02000000555#define QE_SDSR_BER2 0x01000000556 557#define QE_SDMR_GLB_1_MSK 0x80000000558#define QE_SDMR_ADR_SEL 0x20000000559#define QE_SDMR_BER1_MSK 0x02000000560#define QE_SDMR_BER2_MSK 0x01000000561#define QE_SDMR_EB1_MSK 0x00800000562#define QE_SDMR_ER1_MSK 0x00080000563#define QE_SDMR_ER2_MSK 0x00040000564#define QE_SDMR_CEN_MASK 0x0000E000565#define QE_SDMR_SBER_1 0x00000200566#define QE_SDMR_SBER_2 0x00000200567#define QE_SDMR_EB1_PR_MASK 0x000000C0568#define QE_SDMR_ER1_PR 0x00000008569 570#define QE_SDMR_CEN_SHIFT 13571#define QE_SDMR_EB1_PR_SHIFT 6572 573#define QE_SDTM_MSNUM_SHIFT 24574 575#define QE_SDEBCR_BA_MASK 0x01FFFFFF576 577/* Communication Processor */578#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */579#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */580#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */581 582/* I-RAM */583#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */584#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */585#define QE_IRAM_READY 0x80000000 /* Ready */586 587/* UPC */588#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */589#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */590#define UPGCR_RMS 0x20000000 /* Receive master/slave mode */591#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */592#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */593 594/* UCC GUEMR register */595#define UCC_GUEMR_MODE_MASK_RX 0x02596#define UCC_GUEMR_MODE_FAST_RX 0x02597#define UCC_GUEMR_MODE_SLOW_RX 0x00598#define UCC_GUEMR_MODE_MASK_TX 0x01599#define UCC_GUEMR_MODE_FAST_TX 0x01600#define UCC_GUEMR_MODE_SLOW_TX 0x00601#define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)602#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but603 must be set 1 */604 605/* structure representing UCC SLOW parameter RAM */606struct ucc_slow_pram {607 __be16 rbase; /* RX BD base address */608 __be16 tbase; /* TX BD base address */609 u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */610 u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */611 __be16 mrblr; /* Rx buffer length */612 __be32 rstate; /* Rx internal state */613 __be32 rptr; /* Rx internal data pointer */614 __be16 rbptr; /* rb BD Pointer */615 __be16 rcount; /* Rx internal byte count */616 __be32 rtemp; /* Rx temp */617 __be32 tstate; /* Tx internal state */618 __be32 tptr; /* Tx internal data pointer */619 __be16 tbptr; /* Tx BD pointer */620 __be16 tcount; /* Tx byte count */621 __be32 ttemp; /* Tx temp */622 __be32 rcrc; /* temp receive CRC */623 __be32 tcrc; /* temp transmit CRC */624} __attribute__ ((packed));625 626/* General UCC SLOW Mode Register (GUMRH & GUMRL) */627#define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000628#define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000629#define UCC_SLOW_GUMR_H_REVD 0x00002000630#define UCC_SLOW_GUMR_H_TRX 0x00001000631#define UCC_SLOW_GUMR_H_TTX 0x00000800632#define UCC_SLOW_GUMR_H_CDP 0x00000400633#define UCC_SLOW_GUMR_H_CTSP 0x00000200634#define UCC_SLOW_GUMR_H_CDS 0x00000100635#define UCC_SLOW_GUMR_H_CTSS 0x00000080636#define UCC_SLOW_GUMR_H_TFL 0x00000040637#define UCC_SLOW_GUMR_H_RFW 0x00000020638#define UCC_SLOW_GUMR_H_TXSY 0x00000010639#define UCC_SLOW_GUMR_H_4SYNC 0x00000004640#define UCC_SLOW_GUMR_H_8SYNC 0x00000008641#define UCC_SLOW_GUMR_H_16SYNC 0x0000000c642#define UCC_SLOW_GUMR_H_RTSM 0x00000002643#define UCC_SLOW_GUMR_H_RSYN 0x00000001644 645#define UCC_SLOW_GUMR_L_TCI 0x10000000646#define UCC_SLOW_GUMR_L_RINV 0x02000000647#define UCC_SLOW_GUMR_L_TINV 0x01000000648#define UCC_SLOW_GUMR_L_TEND 0x00040000649#define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000650#define UCC_SLOW_GUMR_L_TDCR_32 0x00030000651#define UCC_SLOW_GUMR_L_TDCR_16 0x00020000652#define UCC_SLOW_GUMR_L_TDCR_8 0x00010000653#define UCC_SLOW_GUMR_L_TDCR_1 0x00000000654#define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000655#define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000656#define UCC_SLOW_GUMR_L_RDCR_16 0x00008000657#define UCC_SLOW_GUMR_L_RDCR_8 0x00004000658#define UCC_SLOW_GUMR_L_RDCR_1 0x00000000659#define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800660#define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000661#define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100662#define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000663#define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0664#define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0665#define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080666#define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040667#define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000668#define UCC_SLOW_GUMR_L_ENR 0x00000020669#define UCC_SLOW_GUMR_L_ENT 0x00000010670#define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F671#define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008672#define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006673#define UCC_SLOW_GUMR_L_MODE_UART 0x00000004674#define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002675 676/* General UCC FAST Mode Register */677#define UCC_FAST_GUMR_LOOPBACK 0x40000000678#define UCC_FAST_GUMR_TCI 0x20000000679#define UCC_FAST_GUMR_TRX 0x10000000680#define UCC_FAST_GUMR_TTX 0x08000000681#define UCC_FAST_GUMR_CDP 0x04000000682#define UCC_FAST_GUMR_CTSP 0x02000000683#define UCC_FAST_GUMR_CDS 0x01000000684#define UCC_FAST_GUMR_CTSS 0x00800000685#define UCC_FAST_GUMR_TXSY 0x00020000686#define UCC_FAST_GUMR_RSYN 0x00010000687#define UCC_FAST_GUMR_SYNL_MASK 0x0000C000688#define UCC_FAST_GUMR_SYNL_16 0x0000C000689#define UCC_FAST_GUMR_SYNL_8 0x00008000690#define UCC_FAST_GUMR_SYNL_AUTO 0x00004000691#define UCC_FAST_GUMR_RTSM 0x00002000692#define UCC_FAST_GUMR_REVD 0x00000400693#define UCC_FAST_GUMR_ENR 0x00000020694#define UCC_FAST_GUMR_ENT 0x00000010695 696/* UART Slow UCC Event Register (UCCE) */697#define UCC_UART_UCCE_AB 0x0200698#define UCC_UART_UCCE_IDLE 0x0100699#define UCC_UART_UCCE_GRA 0x0080700#define UCC_UART_UCCE_BRKE 0x0040701#define UCC_UART_UCCE_BRKS 0x0020702#define UCC_UART_UCCE_CCR 0x0008703#define UCC_UART_UCCE_BSY 0x0004704#define UCC_UART_UCCE_TX 0x0002705#define UCC_UART_UCCE_RX 0x0001706 707/* HDLC Slow UCC Event Register (UCCE) */708#define UCC_HDLC_UCCE_GLR 0x1000709#define UCC_HDLC_UCCE_GLT 0x0800710#define UCC_HDLC_UCCE_IDLE 0x0100711#define UCC_HDLC_UCCE_BRKE 0x0040712#define UCC_HDLC_UCCE_BRKS 0x0020713#define UCC_HDLC_UCCE_TXE 0x0010714#define UCC_HDLC_UCCE_RXF 0x0008715#define UCC_HDLC_UCCE_BSY 0x0004716#define UCC_HDLC_UCCE_TXB 0x0002717#define UCC_HDLC_UCCE_RXB 0x0001718 719/* BISYNC Slow UCC Event Register (UCCE) */720#define UCC_BISYNC_UCCE_GRA 0x0080721#define UCC_BISYNC_UCCE_TXE 0x0010722#define UCC_BISYNC_UCCE_RCH 0x0008723#define UCC_BISYNC_UCCE_BSY 0x0004724#define UCC_BISYNC_UCCE_TXB 0x0002725#define UCC_BISYNC_UCCE_RXB 0x0001726 727/* Gigabit Ethernet Fast UCC Event Register (UCCE) */728#define UCC_GETH_UCCE_MPD 0x80000000729#define UCC_GETH_UCCE_SCAR 0x40000000730#define UCC_GETH_UCCE_GRA 0x20000000731#define UCC_GETH_UCCE_CBPR 0x10000000732#define UCC_GETH_UCCE_BSY 0x08000000733#define UCC_GETH_UCCE_RXC 0x04000000734#define UCC_GETH_UCCE_TXC 0x02000000735#define UCC_GETH_UCCE_TXE 0x01000000736#define UCC_GETH_UCCE_TXB7 0x00800000737#define UCC_GETH_UCCE_TXB6 0x00400000738#define UCC_GETH_UCCE_TXB5 0x00200000739#define UCC_GETH_UCCE_TXB4 0x00100000740#define UCC_GETH_UCCE_TXB3 0x00080000741#define UCC_GETH_UCCE_TXB2 0x00040000742#define UCC_GETH_UCCE_TXB1 0x00020000743#define UCC_GETH_UCCE_TXB0 0x00010000744#define UCC_GETH_UCCE_RXB7 0x00008000745#define UCC_GETH_UCCE_RXB6 0x00004000746#define UCC_GETH_UCCE_RXB5 0x00002000747#define UCC_GETH_UCCE_RXB4 0x00001000748#define UCC_GETH_UCCE_RXB3 0x00000800749#define UCC_GETH_UCCE_RXB2 0x00000400750#define UCC_GETH_UCCE_RXB1 0x00000200751#define UCC_GETH_UCCE_RXB0 0x00000100752#define UCC_GETH_UCCE_RXF7 0x00000080753#define UCC_GETH_UCCE_RXF6 0x00000040754#define UCC_GETH_UCCE_RXF5 0x00000020755#define UCC_GETH_UCCE_RXF4 0x00000010756#define UCC_GETH_UCCE_RXF3 0x00000008757#define UCC_GETH_UCCE_RXF2 0x00000004758#define UCC_GETH_UCCE_RXF1 0x00000002759#define UCC_GETH_UCCE_RXF0 0x00000001760 761/* UCC Protocol Specific Mode Register (UPSMR), when used for UART */762#define UCC_UART_UPSMR_FLC 0x8000763#define UCC_UART_UPSMR_SL 0x4000764#define UCC_UART_UPSMR_CL_MASK 0x3000765#define UCC_UART_UPSMR_CL_8 0x3000766#define UCC_UART_UPSMR_CL_7 0x2000767#define UCC_UART_UPSMR_CL_6 0x1000768#define UCC_UART_UPSMR_CL_5 0x0000769#define UCC_UART_UPSMR_UM_MASK 0x0c00770#define UCC_UART_UPSMR_UM_NORMAL 0x0000771#define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400772#define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00773#define UCC_UART_UPSMR_FRZ 0x0200774#define UCC_UART_UPSMR_RZS 0x0100775#define UCC_UART_UPSMR_SYN 0x0080776#define UCC_UART_UPSMR_DRT 0x0040777#define UCC_UART_UPSMR_PEN 0x0010778#define UCC_UART_UPSMR_RPM_MASK 0x000c779#define UCC_UART_UPSMR_RPM_ODD 0x0000780#define UCC_UART_UPSMR_RPM_LOW 0x0004781#define UCC_UART_UPSMR_RPM_EVEN 0x0008782#define UCC_UART_UPSMR_RPM_HIGH 0x000C783#define UCC_UART_UPSMR_TPM_MASK 0x0003784#define UCC_UART_UPSMR_TPM_ODD 0x0000785#define UCC_UART_UPSMR_TPM_LOW 0x0001786#define UCC_UART_UPSMR_TPM_EVEN 0x0002787#define UCC_UART_UPSMR_TPM_HIGH 0x0003788 789/* UCC Protocol Specific Mode Register (UPSMR), when used for Ethernet */790#define UCC_GETH_UPSMR_FTFE 0x80000000791#define UCC_GETH_UPSMR_PTPE 0x40000000792#define UCC_GETH_UPSMR_ECM 0x04000000793#define UCC_GETH_UPSMR_HSE 0x02000000794#define UCC_GETH_UPSMR_PRO 0x00400000795#define UCC_GETH_UPSMR_CAP 0x00200000796#define UCC_GETH_UPSMR_RSH 0x00100000797#define UCC_GETH_UPSMR_RPM 0x00080000798#define UCC_GETH_UPSMR_R10M 0x00040000799#define UCC_GETH_UPSMR_RLPB 0x00020000800#define UCC_GETH_UPSMR_TBIM 0x00010000801#define UCC_GETH_UPSMR_RES1 0x00002000802#define UCC_GETH_UPSMR_RMM 0x00001000803#define UCC_GETH_UPSMR_CAM 0x00000400804#define UCC_GETH_UPSMR_BRO 0x00000200805#define UCC_GETH_UPSMR_SMM 0x00000080806#define UCC_GETH_UPSMR_SGMM 0x00000020807 808/* UCC Protocol Specific Mode Register (UPSMR), when used for HDLC */809#define UCC_HDLC_UPSMR_RTE 0x02000000810#define UCC_HDLC_UPSMR_BUS 0x00200000811#define UCC_HDLC_UPSMR_CW8 0x00007000812 813/* UCC Transmit On Demand Register (UTODR) */814#define UCC_SLOW_TOD 0x8000815#define UCC_FAST_TOD 0x8000816 817/* UCC Bus Mode Register masks */818/* Not to be confused with the Bundle Mode Register */819#define UCC_BMR_GBL 0x20820#define UCC_BMR_BO_BE 0x10821#define UCC_BMR_CETM 0x04822#define UCC_BMR_DTB 0x02823#define UCC_BMR_BDB 0x01824 825/* Function code masks */826#define FC_GBL 0x20827#define FC_DTB_LCL 0x02828#define UCC_FAST_FUNCTION_CODE_GBL 0x20829#define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02830#define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01831 832#endif /* __KERNEL__ */833#endif /* _ASM_POWERPC_QE_H */834