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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * QMC management4 *5 * Copyright 2022 CS GROUP France6 *7 * Author: Herve Codina <herve.codina@bootlin.com>8 */9#ifndef __SOC_FSL_QMC_H__10#define __SOC_FSL_QMC_H__11 12#include <linux/bits.h>13#include <linux/types.h>14 15struct device_node;16struct device;17struct qmc_chan;18 19int qmc_chan_count_phandles(struct device_node *np, const char *phandles_name);20 21struct qmc_chan *qmc_chan_get_byphandles_index(struct device_node *np,22 const char *phandles_name,23 int index);24struct qmc_chan *devm_qmc_chan_get_byphandles_index(struct device *dev,25 struct device_node *np,26 const char *phandles_name,27 int index);28 29static inline struct qmc_chan *qmc_chan_get_byphandle(struct device_node *np,30 const char *phandle_name)31{32 return qmc_chan_get_byphandles_index(np, phandle_name, 0);33}34 35static inline struct qmc_chan *devm_qmc_chan_get_byphandle(struct device *dev,36 struct device_node *np,37 const char *phandle_name)38{39 return devm_qmc_chan_get_byphandles_index(dev, np, phandle_name, 0);40}41 42struct qmc_chan *qmc_chan_get_bychild(struct device_node *np);43void qmc_chan_put(struct qmc_chan *chan);44 45struct qmc_chan *devm_qmc_chan_get_bychild(struct device *dev, struct device_node *np);46 47enum qmc_mode {48 QMC_TRANSPARENT,49 QMC_HDLC,50};51 52struct qmc_chan_info {53 enum qmc_mode mode;54 unsigned long rx_fs_rate;55 unsigned long rx_bit_rate;56 u8 nb_rx_ts;57 unsigned long tx_fs_rate;58 unsigned long tx_bit_rate;59 u8 nb_tx_ts;60};61 62int qmc_chan_get_info(struct qmc_chan *chan, struct qmc_chan_info *info);63 64struct qmc_chan_ts_info {65 u64 rx_ts_mask_avail;66 u64 tx_ts_mask_avail;67 u64 rx_ts_mask;68 u64 tx_ts_mask;69};70 71int qmc_chan_get_ts_info(struct qmc_chan *chan, struct qmc_chan_ts_info *ts_info);72int qmc_chan_set_ts_info(struct qmc_chan *chan, const struct qmc_chan_ts_info *ts_info);73 74struct qmc_chan_param {75 enum qmc_mode mode;76 union {77 struct {78 u16 max_rx_buf_size;79 u16 max_rx_frame_size;80 bool is_crc32;81 } hdlc;82 struct {83 u16 max_rx_buf_size;84 } transp;85 };86};87 88int qmc_chan_set_param(struct qmc_chan *chan, const struct qmc_chan_param *param);89 90int qmc_chan_write_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,91 void (*complete)(void *context), void *context);92 93/* Flags available (ORed) for read complete() flags parameter in HDLC mode.94 * No flags are available in transparent mode and the read complete() flags95 * parameter has no meaning in transparent mode.96 */97#define QMC_RX_FLAG_HDLC_LAST BIT(11) /* Last in frame */98#define QMC_RX_FLAG_HDLC_FIRST BIT(10) /* First in frame */99#define QMC_RX_FLAG_HDLC_OVF BIT(5) /* Data overflow */100#define QMC_RX_FLAG_HDLC_UNA BIT(4) /* Unaligned (ie. bits received not multiple of 8) */101#define QMC_RX_FLAG_HDLC_ABORT BIT(3) /* Received an abort sequence (seven consecutive ones) */102#define QMC_RX_FLAG_HDLC_CRC BIT(2) /* CRC error */103 104int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,105 void (*complete)(void *context, size_t length,106 unsigned int flags),107 void *context);108 109#define QMC_CHAN_READ (1<<0)110#define QMC_CHAN_WRITE (1<<1)111#define QMC_CHAN_ALL (QMC_CHAN_READ | QMC_CHAN_WRITE)112 113int qmc_chan_start(struct qmc_chan *chan, int direction);114int qmc_chan_stop(struct qmc_chan *chan, int direction);115int qmc_chan_reset(struct qmc_chan *chan, int direction);116 117#endif /* __SOC_FSL_QMC_H__ */118