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1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * AMD ACP 6.3 Register Documentation4 *5 * Copyright 2022 Advanced Micro Devices, Inc.6 */7 8#ifndef _acp_ip_OFFSET_HEADER9#define _acp_ip_OFFSET_HEADER10 11/* Registers from ACP_DMA block */12#define ACP_DMA_CNTL_0 0x000000013#define ACP_DMA_CNTL_1 0x000000414#define ACP_DMA_CNTL_2 0x000000815#define ACP_DMA_CNTL_3 0x000000C16#define ACP_DMA_CNTL_4 0x000001017#define ACP_DMA_CNTL_5 0x000001418#define ACP_DMA_CNTL_6 0x000001819#define ACP_DMA_CNTL_7 0x000001C20#define ACP_DMA_DSCR_STRT_IDX_0 0x000002021#define ACP_DMA_DSCR_STRT_IDX_1 0x000002422#define ACP_DMA_DSCR_STRT_IDX_2 0x000002823#define ACP_DMA_DSCR_STRT_IDX_3 0x000002C24#define ACP_DMA_DSCR_STRT_IDX_4 0x000003025#define ACP_DMA_DSCR_STRT_IDX_5 0x000003426#define ACP_DMA_DSCR_STRT_IDX_6 0x000003827#define ACP_DMA_DSCR_STRT_IDX_7 0x000003C28#define ACP_DMA_DSCR_CNT_0 0x000004029#define ACP_DMA_DSCR_CNT_1 0x000004430#define ACP_DMA_DSCR_CNT_2 0x000004831#define ACP_DMA_DSCR_CNT_3 0x000004C32#define ACP_DMA_DSCR_CNT_4 0x000005033#define ACP_DMA_DSCR_CNT_5 0x000005434#define ACP_DMA_DSCR_CNT_6 0x000005835#define ACP_DMA_DSCR_CNT_7 0x000005C36#define ACP_DMA_PRIO_0 0x000006037#define ACP_DMA_PRIO_1 0x000006438#define ACP_DMA_PRIO_2 0x000006839#define ACP_DMA_PRIO_3 0x000006C40#define ACP_DMA_PRIO_4 0x000007041#define ACP_DMA_PRIO_5 0x000007442#define ACP_DMA_PRIO_6 0x000007843#define ACP_DMA_PRIO_7 0x000007C44#define ACP_DMA_CUR_DSCR_0 0x000008045#define ACP_DMA_CUR_DSCR_1 0x000008446#define ACP_DMA_CUR_DSCR_2 0x000008847#define ACP_DMA_CUR_DSCR_3 0x000008C48#define ACP_DMA_CUR_DSCR_4 0x000009049#define ACP_DMA_CUR_DSCR_5 0x000009450#define ACP_DMA_CUR_DSCR_6 0x000009851#define ACP_DMA_CUR_DSCR_7 0x000009C52#define ACP_DMA_CUR_TRANS_CNT_0 0x00000A053#define ACP_DMA_CUR_TRANS_CNT_1 0x00000A454#define ACP_DMA_CUR_TRANS_CNT_2 0x00000A855#define ACP_DMA_CUR_TRANS_CNT_3 0x00000AC56#define ACP_DMA_CUR_TRANS_CNT_4 0x00000B057#define ACP_DMA_CUR_TRANS_CNT_5 0x00000B458#define ACP_DMA_CUR_TRANS_CNT_6 0x00000B859#define ACP_DMA_CUR_TRANS_CNT_7 0x00000BC60#define ACP_DMA_ERR_STS_0 0x00000C061#define ACP_DMA_ERR_STS_1 0x00000C462#define ACP_DMA_ERR_STS_2 0x00000C863#define ACP_DMA_ERR_STS_3 0x00000CC64#define ACP_DMA_ERR_STS_4 0x00000D065#define ACP_DMA_ERR_STS_5 0x00000D466#define ACP_DMA_ERR_STS_6 0x00000D867#define ACP_DMA_ERR_STS_7 0x00000DC68#define ACP_DMA_DESC_BASE_ADDR 0x00000E069#define ACP_DMA_DESC_MAX_NUM_DSCR 0x00000E470#define ACP_DMA_CH_STS 0x00000E871#define ACP_DMA_CH_GROUP 0x00000EC72#define ACP_DMA_CH_RST_STS 0x00000F073 74/* Registers from ACP_AXI2AXIATU block */75#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x0000C0076#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x0000C0477#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x0000C0878#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x0000C0C79#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x0000C1080#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x0000C1481#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x0000C1882#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x0000C1C83#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x0000C2084#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x0000C2485#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x0000C2886#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x0000C2C87#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x0000C3088#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x0000C3489#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x0000C3890#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x0000C3C91#define ACPAXI2AXI_ATU_CTRL 0x0000C4092#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_9 0x0000C4493#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_9 0x0000C4894#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_10 0x0000C4C95#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_10 0x0000C5096#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_11 0x0000C5497#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_11 0x0000C5898#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_12 0x0000C5C99#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_12 0x0000C60100#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_13 0x0000C64101#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_13 0x0000C68102#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_14 0x0000C6C103#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_14 0x0000C70104#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_15 0x0000C74105#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_15 0x0000C78106#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_16 0x0000C7C107#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_16 0x0000C80108 109/* Registers from ACP_CLKRST block */110#define ACP_SOFT_RESET 0x0001000111#define ACP_CONTROL 0x0001004112#define ACP_STATUS 0x0001008113#define ACP_DYNAMIC_CG_MASTER_CONTROL 0x0001010114#define ACP_ZSC_DSP_CTRL 0x0001014115#define ACP_ZSC_STS 0x0001018116#define ACP_PGFSM_CONTROL 0x0001024117#define ACP_PGFSM_STATUS 0x0001028118#define ACP_CLKMUX_SEL 0x000102C119 120/* Registers from ACP_AON block */121#define ACP_PME_EN 0x0001400122#define ACP_DEVICE_STATE 0x0001404123#define AZ_DEVICE_STATE 0x0001408124#define ACP_PIN_CONFIG 0x0001440125#define ACP_PAD_PULLUP_CTRL 0x0001444126#define ACP_PAD_PULLDOWN_CTRL 0x0001448127#define ACP_PAD_DRIVE_STRENGTH_CTRL 0x000144C128#define ACP_PAD_SCHMEN_CTRL 0x0001450129#define ACP_SW0_PAD_KEEPER_EN 0x0001454130#define ACP_SW0_WAKE_EN 0x0001458131#define ACP_I2S_WAKE_EN 0x000145C132#define ACP_SW1_WAKE_EN 0x0001460133 134#define ACP_SW0_I2S_ERROR_REASON 0x00018B4135#define ACP_SW0_POS_TRACK_AUDIO0_TX_CTRL 0x00018B8136#define ACP_SW0_AUDIO0_TX_DMA_POS 0x00018BC137#define ACP_SW0_POS_TRACK_AUDIO1_TX_CTRL 0x00018C0138#define ACP_SW0_AUDIO1_TX_DMA_POS 0x00018C4139#define ACP_SW0_POS_TRACK_AUDIO2_TX_CTRL 0x00018C8140#define ACP_SW0_AUDIO2_TX_DMA_POS 0x00018CC141#define ACP_SW0_POS_TRACK_AUDIO0_RX_CTRL 0x00018D0142#define ACP_SW0_AUDIO0_DMA_POS 0x00018D4143#define ACP_SW0_POS_TRACK_AUDIO1_RX_CTRL 0x00018D8144#define ACP_SW0_AUDIO1_RX_DMA_POS 0x00018DC145#define ACP_SW0_POS_TRACK_AUDIO2_RX_CTRL 0x00018E0146#define ACP_SW0_AUDIO2_RX_DMA_POS 0x00018E4147#define ACP_ERROR_INTR_MASK1 0X0001974148#define ACP_ERROR_INTR_MASK2 0X0001978149#define ACP_ERROR_INTR_MASK3 0X000197C150 151/* Registers from ACP_P1_MISC block */152#define ACP_EXTERNAL_INTR_ENB 0x0001A00153#define ACP_EXTERNAL_INTR_CNTL 0x0001A04154#define ACP_EXTERNAL_INTR_CNTL1 0x0001A08155#define ACP_EXTERNAL_INTR_STAT 0x0001A0C156#define ACP_EXTERNAL_INTR_STAT1 0x0001A10157#define ACP_ERROR_STATUS 0x0001A4C158#define ACP_SW1_I2S_ERROR_REASON 0x0001A50159#define ACP_SW1_POS_TRACK_AUDIO0_TX_CTRL 0x0001A6C160#define ACP_SW1_AUDIO0_TX_DMA_POS 0x0001A70161#define ACP_SW1_POS_TRACK_AUDIO0_RX_CTRL 0x0001A74162#define ACP_SW1_AUDIO0_RX_DMA_POS 0x0001A78163#define ACP_P1_DMIC_I2S_GPIO_INTR_CTRL 0x0001A7C164#define ACP_P1_DMIC_I2S_GPIO_INTR_STATUS 0x0001A80165#define ACP_SCRATCH_REG_BASE_ADDR 0x0001A84166#define ACP_SW1_POS_TRACK_AUDIO1_TX_CTRL 0x0001A88167#define ACP_SW1_AUDIO1_TX_DMA_POS 0x0001A8C168#define ACP_SW1_POS_TRACK_AUDIO2_TX_CTRL 0x0001A90169#define ACP_SW1_AUDIO2_TX_DMA_POS 0x0001A94170#define ACP_SW1_POS_TRACK_AUDIO1_RX_CTRL 0x0001A98171#define ACP_SW1_AUDIO1_RX_DMA_POS 0x0001A9C172#define ACP_SW1_POS_TRACK_AUDIO2_RX_CTRL 0x0001AA0173#define ACP_SW1_AUDIO2_RX_DMA_POS 0x0001AA4174#define ACP_ERROR_INTR_MASK4 0X0001AEC175#define ACP_ERROR_INTR_MASK5 0X0001AF0176 177/* Registers from ACP_AUDIO_BUFFERS block */178#define ACP_AUDIO0_RX_RINGBUFADDR 0x0002000179#define ACP_AUDIO0_RX_RINGBUFSIZE 0x0002004180#define ACP_AUDIO0_RX_LINKPOSITIONCNTR 0x0002008181#define ACP_AUDIO0_RX_FIFOADDR 0x000200C182#define ACP_AUDIO0_RX_FIFOSIZE 0x0002010183#define ACP_AUDIO0_RX_DMA_SIZE 0x0002014184#define ACP_AUDIO0_RX_LINEARPOSITIONCNTR_HIGH 0x0002018185#define ACP_AUDIO0_RX_LINEARPOSITIONCNTR_LOW 0x000201C186#define ACP_AUDIO0_RX_INTR_WATERMARK_SIZE 0x0002020187#define ACP_AUDIO0_TX_RINGBUFADDR 0x0002024188#define ACP_AUDIO0_TX_RINGBUFSIZE 0x0002028189#define ACP_AUDIO0_TX_LINKPOSITIONCNTR 0x000202C190#define ACP_AUDIO0_TX_FIFOADDR 0x0002030191#define ACP_AUDIO0_TX_FIFOSIZE 0x0002034192#define ACP_AUDIO0_TX_DMA_SIZE 0x0002038193#define ACP_AUDIO0_TX_LINEARPOSITIONCNTR_HIGH 0x000203C194#define ACP_AUDIO0_TX_LINEARPOSITIONCNTR_LOW 0x0002040195#define ACP_AUDIO0_TX_INTR_WATERMARK_SIZE 0x0002044196#define ACP_AUDIO1_RX_RINGBUFADDR 0x0002048197#define ACP_AUDIO1_RX_RINGBUFSIZE 0x000204C198#define ACP_AUDIO1_RX_LINKPOSITIONCNTR 0x0002050199#define ACP_AUDIO1_RX_FIFOADDR 0x0002054200#define ACP_AUDIO1_RX_FIFOSIZE 0x0002058201#define ACP_AUDIO1_RX_DMA_SIZE 0x000205C202#define ACP_AUDIO1_RX_LINEARPOSITIONCNTR_HIGH 0x0002060203#define ACP_AUDIO1_RX_LINEARPOSITIONCNTR_LOW 0x0002064204#define ACP_AUDIO1_RX_INTR_WATERMARK_SIZE 0x0002068205#define ACP_AUDIO1_TX_RINGBUFADDR 0x000206C206#define ACP_AUDIO1_TX_RINGBUFSIZE 0x0002070207#define ACP_AUDIO1_TX_LINKPOSITIONCNTR 0x0002074208#define ACP_AUDIO1_TX_FIFOADDR 0x0002078209#define ACP_AUDIO1_TX_FIFOSIZE 0x000207C210#define ACP_AUDIO1_TX_DMA_SIZE 0x0002080211#define ACP_AUDIO1_TX_LINEARPOSITIONCNTR_HIGH 0x0002084212#define ACP_AUDIO1_TX_LINEARPOSITIONCNTR_LOW 0x0002088213#define ACP_AUDIO1_TX_INTR_WATERMARK_SIZE 0x000208C214#define ACP_AUDIO2_RX_RINGBUFADDR 0x0002090215#define ACP_AUDIO2_RX_RINGBUFSIZE 0x0002094216#define ACP_AUDIO2_RX_LINKPOSITIONCNTR 0x0002098217#define ACP_AUDIO2_RX_FIFOADDR 0x000209C218#define ACP_AUDIO2_RX_FIFOSIZE 0x00020A0219#define ACP_AUDIO2_RX_DMA_SIZE 0x00020A4220#define ACP_AUDIO2_RX_LINEARPOSITIONCNTR_HIGH 0x00020A8221#define ACP_AUDIO2_RX_LINEARPOSITIONCNTR_LOW 0x00020AC222#define ACP_AUDIO2_RX_INTR_WATERMARK_SIZE 0x00020B0223#define ACP_AUDIO2_TX_RINGBUFADDR 0x00020B4224#define ACP_AUDIO2_TX_RINGBUFSIZE 0x00020B8225#define ACP_AUDIO2_TX_LINKPOSITIONCNTR 0x00020BC226#define ACP_AUDIO2_TX_FIFOADDR 0x00020C0227#define ACP_AUDIO2_TX_FIFOSIZE 0x00020C4228#define ACP_AUDIO2_TX_DMA_SIZE 0x00020C8229#define ACP_AUDIO2_TX_LINEARPOSITIONCNTR_HIGH 0x00020CC230#define ACP_AUDIO2_TX_LINEARPOSITIONCNTR_LOW 0x00020D0231#define ACP_AUDIO2_TX_INTR_WATERMARK_SIZE 0x00020D4232 233/* Registers from ACP_I2S_TDM block */234#define ACP_I2STDM_IER 0x0002400235#define ACP_I2STDM_IRER 0x0002404236#define ACP_I2STDM_RXFRMT 0x0002408237#define ACP_I2STDM_ITER 0x000240C238#define ACP_I2STDM_TXFRMT 0x0002410239#define ACP_I2STDM0_MSTRCLKGEN 0x0002414240#define ACP_I2STDM1_MSTRCLKGEN 0x0002418241#define ACP_I2STDM2_MSTRCLKGEN 0x000241C242#define ACP_I2STDM_REFCLKGEN 0x0002420243 244/* Registers from ACP_BT_TDM block */245#define ACP_BTTDM_IER 0x0002800246#define ACP_BTTDM_IRER 0x0002804247#define ACP_BTTDM_RXFRMT 0x0002808248#define ACP_BTTDM_ITER 0x000280C249#define ACP_BTTDM_TXFRMT 0x0002810250#define ACP_HSTDM_IER 0x0002814251#define ACP_HSTDM_IRER 0x0002818252#define ACP_HSTDM_RXFRMT 0x000281C253#define ACP_HSTDM_ITER 0x0002820254#define ACP_HSTDM_TXFRMT 0x0002824255 256/* Registers from ACP_WOV block */257#define ACP_WOV_PDM_ENABLE 0x0002C04258#define ACP_WOV_PDM_DMA_ENABLE 0x0002C08259#define ACP_WOV_RX_RINGBUFADDR 0x0002C0C260#define ACP_WOV_RX_RINGBUFSIZE 0x0002C10261#define ACP_WOV_RX_LINKPOSITIONCNTR 0x0002C14262#define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH 0x0002C18263#define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW 0x0002C1C264#define ACP_WOV_RX_INTR_WATERMARK_SIZE 0x0002C20265#define ACP_WOV_PDM_FIFO_FLUSH 0x0002C24266#define ACP_WOV_PDM_NO_OF_CHANNELS 0x0002C28267#define ACP_WOV_PDM_DECIMATION_FACTOR 0x0002C2C268#define ACP_WOV_PDM_VAD_CTRL 0x0002C30269#define ACP_WOV_WAKE 0x0002C54270#define ACP_WOV_BUFFER_STATUS 0x0002C58271#define ACP_WOV_MISC_CTRL 0x0002C5C272#define ACP_WOV_CLK_CTRL 0x0002C60273#define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x0002C64274#define ACP_WOV_ERROR_STATUS_REGISTER 0x0002C68275#define ACP_PDM_CLKDIV 0x0002C6C276 277/* Registers from ACP_SW0_SWCLK block */278#define ACP_SW0_EN 0x0003000279#define ACP_SW0_EN_STATUS 0x0003004280#define ACP_SW0_FRAMESIZE 0x0003008281#define ACP_SW0_SSP_COUNTER 0x000300C282#define ACP_SW0_AUDIO0_TX_EN 0x0003010283#define ACP_SW0_AUDIO0_TX_EN_STATUS 0x0003014284#define ACP_SW0_AUDIO0_TX_FRAME_FORMAT 0x0003018285#define ACP_SW0_AUDIO0_TX_SAMPLEINTERVAL 0x000301C286#define ACP_SW0_AUDIO0_TX_HCTRL_DP0 0x0003020287#define ACP_SW0_AUDIO0_TX_HCTRL_DP1 0x0003024288#define ACP_SW0_AUDIO0_TX_HCTRL_DP2 0x0003028289#define ACP_SW0_AUDIO0_TX_HCTRL_DP3 0x000302C290#define ACP_SW0_AUDIO0_TX_OFFSET_DP0 0x0003030291#define ACP_SW0_AUDIO0_TX_OFFSET_DP1 0x0003034292#define ACP_SW0_AUDIO0_TX_OFFSET_DP2 0x0003038293#define ACP_SW0_AUDIO0_TX_OFFSET_DP3 0x000303C294#define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP0 0x0003040295#define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP1 0x0003044296#define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP2 0x0003048297#define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP3 0x000304C298#define ACP_SW0_AUDIO1_TX_EN 0x0003050299#define ACP_SW0_AUDIO1_TX_EN_STATUS 0x0003054300#define ACP_SW0_AUDIO1_TX_FRAME_FORMAT 0x0003058301#define ACP_SW0_AUDIO1_TX_SAMPLEINTERVAL 0x000305C302#define ACP_SW0_AUDIO1_TX_HCTRL 0x0003060303#define ACP_SW0_AUDIO1_TX_OFFSET 0x0003064304#define ACP_SW0_AUDIO1_TX_CHANNEL_ENABLE_DP0 0x0003068305#define ACP_SW0_AUDIO2_TX_EN 0x000306C306#define ACP_SW0_AUDIO2_TX_EN_STATUS 0x0003070307#define ACP_SW0_AUDIO2_TX_FRAME_FORMAT 0x0003074308#define ACP_SW0_AUDIO2_TX_SAMPLEINTERVAL 0x0003078309#define ACP_SW0_AUDIO2_TX_HCTRL 0x000307C310#define ACP_SW0_AUDIO2_TX_OFFSET 0x0003080311#define ACP_SW0_AUDIO2_TX_CHANNEL_ENABLE_DP0 0x0003084312#define ACP_SW0_AUDIO0_RX_EN 0x0003088313#define ACP_SW0_AUDIO0_RX_EN_STATUS 0x000308C314#define ACP_SW0_AUDIO0_RX_FRAME_FORMAT 0x0003090315#define ACP_SW0_AUDIO0_RX_SAMPLEINTERVAL 0x0003094316#define ACP_SW0_AUDIO0_RX_HCTRL_DP0 0x0003098317#define ACP_SW0_AUDIO0_RX_HCTRL_DP1 0x000309C318#define ACP_SW0_AUDIO0_RX_HCTRL_DP2 0x0003100319#define ACP_SW0_AUDIO0_RX_HCTRL_DP3 0x0003104320#define ACP_SW0_AUDIO0_RX_OFFSET_DP0 0x0003108321#define ACP_SW0_AUDIO0_RX_OFFSET_DP1 0x000310C322#define ACP_SW0_AUDIO0_RX_OFFSET_DP2 0x0003110323#define ACP_SW0_AUDIO0_RX_OFFSET_DP3 0x0003114324#define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP0 0x0003118325#define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP1 0x000311C326#define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP2 0x0003120327#define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP3 0x0003124328#define ACP_SW0_AUDIO1_RX_EN 0x0003128329#define ACP_SW0_AUDIO1_RX_EN_STATUS 0x000312C330#define ACP_SW0_AUDIO1_RX_FRAME_FORMAT 0x0003130331#define ACP_SW0_AUDIO1_RX_SAMPLEINTERVAL 0x0003134332#define ACP_SW0_AUDIO1_RX_HCTRL 0x0003138333#define ACP_SW0_AUDIO1_RX_OFFSET 0x000313C334#define ACP_SW0_AUDIO1_RX_CHANNEL_ENABLE_DP0 0x0003140335#define ACP_SW0_AUDIO2_RX_EN 0x0003144336#define ACP_SW0_AUDIO2_RX_EN_STATUS 0x0003148337#define ACP_SW0_AUDIO2_RX_FRAME_FORMAT 0x000314C338#define ACP_SW0_AUDIO2_RX_SAMPLEINTERVAL 0x0003150339#define ACP_SW0_AUDIO2_RX_HCTRL 0x0003154340#define ACP_SW0_AUDIO2_RX_OFFSET 0x0003158341#define ACP_SW0_AUDIO2_RX_CHANNEL_ENABLE_DP0 0x000315C342#define ACP_SW0_BPT_PORT_EN 0x0003160343#define ACP_SW0_BPT_PORT_EN_STATUS 0x0003164344#define ACP_SW0_BPT_PORT_FRAME_FORMAT 0x0003168345#define ACP_SW0_BPT_PORT_SAMPLEINTERVAL 0x000316C346#define ACP_SW0_BPT_PORT_HCTRL 0x0003170347#define ACP_SW0_BPT_PORT_OFFSET 0x0003174348#define ACP_SW0_BPT_PORT_CHANNEL_ENABLE 0x0003178349#define ACP_SW0_BPT_PORT_FIRST_BYTE_ADDR 0x000317C350#define ACP_SW0_CLK_RESUME_CTRL 0x0003180351#define ACP_SW0_CLK_RESUME_DELAY_CNTR 0x0003184352#define ACP_SW0_BUS_RESET_CTRL 0x0003188353#define ACP_SW0_PRBS_ERR_STATUS 0x000318C354#define ACP_SW0_IMM_CMD_UPPER_WORD 0x0003230355#define ACP_SW0_IMM_CMD_LOWER_QWORD 0x0003234356#define ACP_SW0_IMM_RESP_UPPER_WORD 0x0003238357#define ACP_SW0_IMM_RESP_LOWER_QWORD 0x000323C358#define ACP_SW0_IMM_CMD_STS 0x0003240359#define ACP_SW0_BRA_BASE_ADDRESS 0x0003244360#define ACP_SW0_BRA_TRANSFER_SIZE 0x0003248361#define ACP_SW0_BRA_DMA_BUSY 0x000324C362#define ACP_SW0_BRA_RESP 0x0003250363#define ACP_SW0_BRA_RESP_FRAME_ADDR 0x0003254364#define ACP_SW0_BRA_CURRENT_TRANSFER_SIZE 0x0003258365#define ACP_SW0_STATECHANGE_STATUS_0TO7 0x000325C366#define ACP_SW0_STATECHANGE_STATUS_8TO11 0x0003260367#define ACP_SW0_STATECHANGE_STATUS_MASK_0TO7 0x0003264368#define ACP_SW0_STATECHANGE_STATUS_MASK_8TO11 0x0003268369#define ACP_SW0_CLK_FREQUENCY_CTRL 0x000326C370#define ACP_SW0_ERROR_INTR_MASK 0x0003270371#define ACP_SW0_PHY_TEST_MODE_DATA_OFF 0x0003274372 373/* Registers from ACP_P1_AUDIO_BUFFERS block */374#define ACP_P1_AUDIO0_RX_RINGBUFADDR 0x0003A00375#define ACP_P1_AUDIO0_RX_RINGBUFSIZE 0x0003A04376#define ACP_P1_AUDIO0_RX_LINKPOSITIONCNTR 0x0003A08377#define ACP_P1_AUDIO0_RX_FIFOADDR 0x0003A0C378#define ACP_P1_AUDIO0_RX_FIFOSIZE 0x0003A10379#define ACP_P1_AUDIO0_RX_DMA_SIZE 0x0003A14380#define ACP_P1_AUDIO0_RX_LINEARPOSITIONCNTR_HIGH 0x0003A18381#define ACP_P1_AUDIO0_RX_LINEARPOSITIONCNTR_LOW 0x0003A1C382#define ACP_P1_AUDIO0_RX_INTR_WATERMARK_SIZE 0x0003A20383#define ACP_P1_AUDIO0_TX_RINGBUFADDR 0x0003A24384#define ACP_P1_AUDIO0_TX_RINGBUFSIZE 0x0003A28385#define ACP_P1_AUDIO0_TX_LINKPOSITIONCNTR 0x0003A2C386#define ACP_P1_AUDIO0_TX_FIFOADDR 0x0003A30387#define ACP_P1_AUDIO0_TX_FIFOSIZE 0x0003A34388#define ACP_P1_AUDIO0_TX_DMA_SIZE 0x0003A38389#define ACP_P1_AUDIO0_TX_LINEARPOSITIONCNTR_HIGH 0x0003A3C390#define ACP_P1_AUDIO0_TX_LINEARPOSITIONCNTR_LOW 0x0003A40391#define ACP_P1_AUDIO0_TX_INTR_WATERMARK_SIZE 0x0003A44392#define ACP_P1_AUDIO1_RX_RINGBUFADDR 0x0003A48393#define ACP_P1_AUDIO1_RX_RINGBUFSIZE 0x0003A4C394#define ACP_P1_AUDIO1_RX_LINKPOSITIONCNTR 0x0003A50395#define ACP_P1_AUDIO1_RX_FIFOADDR 0x0003A54396#define ACP_P1_AUDIO1_RX_FIFOSIZE 0x0003A58397#define ACP_P1_AUDIO1_RX_DMA_SIZE 0x0003A5C398#define ACP_P1_AUDIO1_RX_LINEARPOSITIONCNTR_HIGH 0x0003A60399#define ACP_P1_AUDIO1_RX_LINEARPOSITIONCNTR_LOW 0x0003A64400#define ACP_P1_AUDIO1_RX_INTR_WATERMARK_SIZE 0x0003A68401#define ACP_P1_AUDIO1_TX_RINGBUFADDR 0x0003A6C402#define ACP_P1_AUDIO1_TX_RINGBUFSIZE 0x0003A70403#define ACP_P1_AUDIO1_TX_LINKPOSITIONCNTR 0x0003A74404#define ACP_P1_AUDIO1_TX_FIFOADDR 0x0003A78405#define ACP_P1_AUDIO1_TX_FIFOSIZE 0x0003A7C406#define ACP_P1_AUDIO1_TX_DMA_SIZE 0x0003A80407#define ACP_P1_AUDIO1_TX_LINEARPOSITIONCNTR_HIGH 0x0003A84408#define ACP_P1_AUDIO1_TX_LINEARPOSITIONCNTR_LOW 0x0003A88409#define ACP_P1_AUDIO1_TX_INTR_WATERMARK_SIZE 0x0003A8C410#define ACP_P1_AUDIO2_RX_RINGBUFADDR 0x0003A90411#define ACP_P1_AUDIO2_RX_RINGBUFSIZE 0x0003A94412#define ACP_P1_AUDIO2_RX_LINKPOSITIONCNTR 0x0003A98413#define ACP_P1_AUDIO2_RX_FIFOADDR 0x0003A9C414#define ACP_P1_AUDIO2_RX_FIFOSIZE 0x0003AA0415#define ACP_P1_AUDIO2_RX_DMA_SIZE 0x0003AA4416#define ACP_P1_AUDIO2_RX_LINEARPOSITIONCNTR_HIGH 0x0003AA8417#define ACP_P1_AUDIO2_RX_LINEARPOSITIONCNTR_LOW 0x0003AAC418#define ACP_P1_AUDIO2_RX_INTR_WATERMARK_SIZE 0x0003AB0419#define ACP_P1_AUDIO2_TX_RINGBUFADDR 0x0003AB4420#define ACP_P1_AUDIO2_TX_RINGBUFSIZE 0x0003AB8421#define ACP_P1_AUDIO2_TX_LINKPOSITIONCNTR 0x0003ABC422#define ACP_P1_AUDIO2_TX_FIFOADDR 0x0003AC0423#define ACP_P1_AUDIO2_TX_FIFOSIZE 0x0003AC4424#define ACP_P1_AUDIO2_TX_DMA_SIZE 0x0003AC8425#define ACP_P1_AUDIO2_TX_LINEARPOSITIONCNTR_HIGH 0x0003ACC426#define ACP_P1_AUDIO2_TX_LINEARPOSITIONCNTR_LOW 0x0003AD0427#define ACP_P1_AUDIO2_TX_INTR_WATERMARK_SIZE 0x0003AD4428 429/* Registers from ACP_SW1_SWCLK block */430#define ACP_SW1_EN 0x0003C00431#define ACP_SW1_EN_STATUS 0x0003C04432#define ACP_SW1_FRAMESIZE 0x0003C08433#define ACP_SW1_SSP_COUNTER 0x0003C0C434#define ACP_SW1_AUDIO1_TX_EN 0x0003C50435#define ACP_SW1_AUDIO1_TX_EN_STATUS 0x0003C54436#define ACP_SW1_AUDIO1_TX_FRAME_FORMAT 0x0003C58437#define ACP_SW1_AUDIO1_TX_SAMPLEINTERVAL 0x0003C5C438#define ACP_SW1_AUDIO1_TX_HCTRL 0x0003C60439#define ACP_SW1_AUDIO1_TX_OFFSET 0x0003C64440#define ACP_SW1_AUDIO1_TX_CHANNEL_ENABLE_DP0 0x0003C68441#define ACP_SW1_AUDIO1_RX_EN 0x0003D28442#define ACP_SW1_AUDIO1_RX_EN_STATUS 0x0003D2C443#define ACP_SW1_AUDIO1_RX_FRAME_FORMAT 0x0003D30444#define ACP_SW1_AUDIO1_RX_SAMPLEINTERVAL 0x0003D34445#define ACP_SW1_AUDIO1_RX_HCTRL 0x0003D38446#define ACP_SW1_AUDIO1_RX_OFFSET 0x0003D3C447#define ACP_SW1_AUDIO1_RX_CHANNEL_ENABLE_DP0 0x0003D40448#define ACP_SW1_BPT_PORT_EN 0x0003D60449#define ACP_SW1_BPT_PORT_EN_STATUS 0x0003D64450#define ACP_SW1_BPT_PORT_FRAME_FORMAT 0x0003D68451#define ACP_SW1_BPT_PORT_SAMPLEINTERVAL 0x0003D6C452#define ACP_SW1_BPT_PORT_HCTRL 0x0003D70453#define ACP_SW1_BPT_PORT_OFFSET 0x0003D74454#define ACP_SW1_BPT_PORT_CHANNEL_ENABLE 0x0003D78455#define ACP_SW1_BPT_PORT_FIRST_BYTE_ADDR 0x0003D7C456#define ACP_SW1_CLK_RESUME_CTRL 0x0003D80457#define ACP_SW1_CLK_RESUME_DELAY_CNTR 0x0003D84458#define ACP_SW1_BUS_RESET_CTRL 0x0003D88459#define ACP_SW1_PRBS_ERR_STATUS 0x0003D8C460 461/* Registers from ACP_SW1_ACLK block */462#define ACP_SW1_CORB_BASE_ADDRESS 0x0003E00463#define ACP_SW1_CORB_WRITE_POINTER 0x0003E04464#define ACP_SW1_CORB_READ_POINTER 0x0003E08465#define ACP_SW1_CORB_CONTROL 0x0003E0C466#define ACP_SW1_CORB_SIZE 0x0003E14467#define ACP_SW1_RIRB_BASE_ADDRESS 0x0003E18468#define ACP_SW1_RIRB_WRITE_POINTER 0x0003E1C469#define ACP_SW1_RIRB_RESPONSE_INTERRUPT_COUNT 0x0003E20470#define ACP_SW1_RIRB_CONTROL 0x0003E24471#define ACP_SW1_RIRB_SIZE 0x0003E28472#define ACP_SW1_RIRB_FIFO_MIN_THDL 0x0003E2C473#define ACP_SW1_IMM_CMD_UPPER_WORD 0x0003E30474#define ACP_SW1_IMM_CMD_LOWER_QWORD 0x0003E34475#define ACP_SW1_IMM_RESP_UPPER_WORD 0x0003E38476#define ACP_SW1_IMM_RESP_LOWER_QWORD 0x0003E3C477#define ACP_SW1_IMM_CMD_STS 0x0003E40478#define ACP_SW1_BRA_BASE_ADDRESS 0x0003E44479#define ACP_SW1_BRA_TRANSFER_SIZE 0x0003E48480#define ACP_SW1_BRA_DMA_BUSY 0x0003E4C481#define ACP_SW1_BRA_RESP 0x0003E50482#define ACP_SW1_BRA_RESP_FRAME_ADDR 0x0003E54483#define ACP_SW1_BRA_CURRENT_TRANSFER_SIZE 0x0003E58484#define ACP_SW1_STATECHANGE_STATUS_0TO7 0x0003E5C485#define ACP_SW1_STATECHANGE_STATUS_8TO11 0x0003E60486#define ACP_SW1_STATECHANGE_STATUS_MASK_0TO7 0x0003E64487#define ACP_SW1_STATECHANGE_STATUS_MASK_8TO11 0x0003E68488#define ACP_SW1_CLK_FREQUENCY_CTRL 0x0003E6C489#define ACP_SW1_ERROR_INTR_MASK 0x0003E70490#define ACP_SW1_PHY_TEST_MODE_DATA_OFF 0x0003E74491 492/* Registers from ACP_SCRATCH block */493#define ACP_SCRATCH_REG_0 0x0010000494 495#endif496