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1/* SPDX-License-Identifier: GPL-2.02 *3 * linux/sound/cs35l41.h -- Platform data for CS35L414 *5 * Copyright (c) 2017-2021 Cirrus Logic Inc.6 *7 * Author: David Rhodes <david.rhodes@cirrus.com>8 */9 10#ifndef __CS35L41_H11#define __CS35L41_H12 13#include <linux/regmap.h>14#include <linux/firmware/cirrus/cs_dsp.h>15 16#define CS35L41_FIRSTREG 0x0000000017#define CS35L41_LASTREG 0x03804FE818#define CS35L41_DEVID 0x0000000019#define CS35L41_REVID 0x0000000420#define CS35L41_FABID 0x0000000821#define CS35L41_RELID 0x0000000C22#define CS35L41_OTPID 0x0000001023#define CS35L41_SFT_RESET 0x0000002024#define CS35L41_TEST_KEY_CTL 0x0000004025#define CS35L41_USER_KEY_CTL 0x0000004426#define CS35L41_OTP_MEM0 0x0000040027#define CS35L41_OTP_MEM31 0x0000047C28#define CS35L41_OTP_CTRL0 0x0000050029#define CS35L41_OTP_CTRL1 0x0000050430#define CS35L41_OTP_CTRL3 0x0000050831#define CS35L41_OTP_CTRL4 0x0000050C32#define CS35L41_OTP_CTRL5 0x0000051033#define CS35L41_OTP_CTRL6 0x0000051434#define CS35L41_OTP_CTRL7 0x0000051835#define CS35L41_OTP_CTRL8 0x0000051C36#define CS35L41_PWR_CTRL1 0x0000201437#define CS35L41_PWR_CTRL2 0x0000201838#define CS35L41_PWR_CTRL3 0x0000201C39#define CS35L41_CTRL_OVRRIDE 0x0000202040#define CS35L41_AMP_OUT_MUTE 0x0000202441#define CS35L41_PROTECT_REL_ERR_IGN 0x0000203442#define CS35L41_GPIO_PAD_CONTROL 0x0000242C43#define CS35L41_JTAG_CONTROL 0x0000243844#define CS35L41_PWRMGT_CTL 0x0000290045#define CS35L41_WAKESRC_CTL 0x0000290446#define CS35L41_PWRMGT_STS 0x0000290847#define CS35L41_PLL_CLK_CTRL 0x00002C0448#define CS35L41_DSP_CLK_CTRL 0x00002C0849#define CS35L41_GLOBAL_CLK_CTRL 0x00002C0C50#define CS35L41_DATA_FS_SEL 0x00002C1051#define CS35L41_TST_FS_MON0 0x00002D1052#define CS35L41_MDSYNC_EN 0x0000340053#define CS35L41_MDSYNC_TX_ID 0x0000340854#define CS35L41_MDSYNC_PWR_CTRL 0x0000340C55#define CS35L41_MDSYNC_DATA_TX 0x0000341056#define CS35L41_MDSYNC_TX_STATUS 0x0000341457#define CS35L41_MDSYNC_DATA_RX 0x0000341C58#define CS35L41_MDSYNC_RX_STATUS 0x0000342059#define CS35L41_MDSYNC_ERR_STATUS 0x0000342460#define CS35L41_MDSYNC_SYNC_PTE2 0x0000352861#define CS35L41_MDSYNC_SYNC_PTE3 0x0000352C62#define CS35L41_MDSYNC_SYNC_MSM_STATUS 0x0000353C63#define CS35L41_BSTCVRT_VCTRL1 0x0000380064#define CS35L41_BSTCVRT_VCTRL2 0x0000380465#define CS35L41_BSTCVRT_PEAK_CUR 0x0000380866#define CS35L41_BSTCVRT_SFT_RAMP 0x0000380C67#define CS35L41_BSTCVRT_COEFF 0x0000381068#define CS35L41_BSTCVRT_SLOPE_LBST 0x0000381469#define CS35L41_BSTCVRT_SW_FREQ 0x0000381870#define CS35L41_BSTCVRT_DCM_CTRL 0x0000381C71#define CS35L41_BSTCVRT_DCM_MODE_FORCE 0x0000382072#define CS35L41_BSTCVRT_OVERVOLT_CTRL 0x0000383073#define CS35L41_VI_VOL_POL 0x0000400074#define CS35L41_VIMON_SPKMON_RESYNC 0x0000410075#define CS35L41_DTEMP_WARN_THLD 0x0000422076#define CS35L41_DTEMP_CFG 0x0000422477#define CS35L41_DTEMP_EN 0x0000430878#define CS35L41_VPVBST_FS_SEL 0x0000440079#define CS35L41_SP_ENABLES 0x0000480080#define CS35L41_SP_RATE_CTRL 0x0000480481#define CS35L41_SP_FORMAT 0x0000480882#define CS35L41_SP_HIZ_CTRL 0x0000480C83#define CS35L41_SP_FRAME_TX_SLOT 0x0000481084#define CS35L41_SP_FRAME_RX_SLOT 0x0000482085#define CS35L41_SP_TX_WL 0x0000483086#define CS35L41_SP_RX_WL 0x0000484087#define CS35L41_ASP_CONTROL4 0x0000485488#define CS35L41_DAC_PCM1_SRC 0x00004C0089#define CS35L41_ASP_TX1_SRC 0x00004C2090#define CS35L41_ASP_TX2_SRC 0x00004C2491#define CS35L41_ASP_TX3_SRC 0x00004C2892#define CS35L41_ASP_TX4_SRC 0x00004C2C93#define CS35L41_DSP1_RX1_SRC 0x00004C4094#define CS35L41_DSP1_RX2_SRC 0x00004C4495#define CS35L41_DSP1_RX3_SRC 0x00004C4896#define CS35L41_DSP1_RX4_SRC 0x00004C4C97#define CS35L41_DSP1_RX5_SRC 0x00004C5098#define CS35L41_DSP1_RX6_SRC 0x00004C5499#define CS35L41_DSP1_RX7_SRC 0x00004C58100#define CS35L41_DSP1_RX8_SRC 0x00004C5C101#define CS35L41_NGATE1_SRC 0x00004C60102#define CS35L41_NGATE2_SRC 0x00004C64103#define CS35L41_AMP_DIG_VOL_CTRL 0x00006000104#define CS35L41_VPBR_CFG 0x00006404105#define CS35L41_VBBR_CFG 0x00006408106#define CS35L41_VPBR_STATUS 0x0000640C107#define CS35L41_VBBR_STATUS 0x00006410108#define CS35L41_OVERTEMP_CFG 0x00006414109#define CS35L41_AMP_ERR_VOL 0x00006418110#define CS35L41_VOL_STATUS_TO_DSP 0x00006450111#define CS35L41_CLASSH_CFG 0x00006800112#define CS35L41_WKFET_CFG 0x00006804113#define CS35L41_NG_CFG 0x00006808114#define CS35L41_AMP_GAIN_CTRL 0x00006C04115#define CS35L41_DAC_MSM_CFG 0x00007400116#define CS35L41_IRQ1_CFG 0x00010000117#define CS35L41_IRQ1_STATUS 0x00010004118#define CS35L41_IRQ1_STATUS1 0x00010010119#define CS35L41_IRQ1_STATUS2 0x00010014120#define CS35L41_IRQ1_STATUS3 0x00010018121#define CS35L41_IRQ1_STATUS4 0x0001001C122#define CS35L41_IRQ1_RAW_STATUS1 0x00010090123#define CS35L41_IRQ1_RAW_STATUS2 0x00010094124#define CS35L41_IRQ1_RAW_STATUS3 0x00010098125#define CS35L41_IRQ1_RAW_STATUS4 0x0001009C126#define CS35L41_IRQ1_MASK1 0x00010110127#define CS35L41_IRQ1_MASK2 0x00010114128#define CS35L41_IRQ1_MASK3 0x00010118129#define CS35L41_IRQ1_MASK4 0x0001011C130#define CS35L41_IRQ1_FRC1 0x00010190131#define CS35L41_IRQ1_FRC2 0x00010194132#define CS35L41_IRQ1_FRC3 0x00010198133#define CS35L41_IRQ1_FRC4 0x0001019C134#define CS35L41_IRQ1_EDGE1 0x00010210135#define CS35L41_IRQ1_EDGE4 0x0001021C136#define CS35L41_IRQ1_POL1 0x00010290137#define CS35L41_IRQ1_POL2 0x00010294138#define CS35L41_IRQ1_POL3 0x00010298139#define CS35L41_IRQ1_POL4 0x0001029C140#define CS35L41_IRQ1_DB3 0x00010318141#define CS35L41_IRQ2_CFG 0x00010800142#define CS35L41_IRQ2_STATUS 0x00010804143#define CS35L41_IRQ2_STATUS1 0x00010810144#define CS35L41_IRQ2_STATUS2 0x00010814145#define CS35L41_IRQ2_STATUS3 0x00010818146#define CS35L41_IRQ2_STATUS4 0x0001081C147#define CS35L41_IRQ2_RAW_STATUS1 0x00010890148#define CS35L41_IRQ2_RAW_STATUS2 0x00010894149#define CS35L41_IRQ2_RAW_STATUS3 0x00010898150#define CS35L41_IRQ2_RAW_STATUS4 0x0001089C151#define CS35L41_IRQ2_MASK1 0x00010910152#define CS35L41_IRQ2_MASK2 0x00010914153#define CS35L41_IRQ2_MASK3 0x00010918154#define CS35L41_IRQ2_MASK4 0x0001091C155#define CS35L41_IRQ2_FRC1 0x00010990156#define CS35L41_IRQ2_FRC2 0x00010994157#define CS35L41_IRQ2_FRC3 0x00010998158#define CS35L41_IRQ2_FRC4 0x0001099C159#define CS35L41_IRQ2_EDGE1 0x00010A10160#define CS35L41_IRQ2_EDGE4 0x00010A1C161#define CS35L41_IRQ2_POL1 0x00010A90162#define CS35L41_IRQ2_POL2 0x00010A94163#define CS35L41_IRQ2_POL3 0x00010A98164#define CS35L41_IRQ2_POL4 0x00010A9C165#define CS35L41_IRQ2_DB3 0x00010B18166#define CS35L41_GPIO_STATUS1 0x00011000167#define CS35L41_GPIO1_CTRL1 0x00011008168#define CS35L41_GPIO2_CTRL1 0x0001100C169#define CS35L41_MIXER_NGATE_CFG 0x00012000170#define CS35L41_MIXER_NGATE_CH1_CFG 0x00012004171#define CS35L41_MIXER_NGATE_CH2_CFG 0x00012008172#define CS35L41_DSP_MBOX_1 0x00013000173#define CS35L41_DSP_MBOX_2 0x00013004174#define CS35L41_DSP_MBOX_3 0x00013008175#define CS35L41_DSP_MBOX_4 0x0001300C176#define CS35L41_DSP_MBOX_5 0x00013010177#define CS35L41_DSP_MBOX_6 0x00013014178#define CS35L41_DSP_MBOX_7 0x00013018179#define CS35L41_DSP_MBOX_8 0x0001301C180#define CS35L41_DSP_VIRT1_MBOX_1 0x00013020181#define CS35L41_DSP_VIRT1_MBOX_2 0x00013024182#define CS35L41_DSP_VIRT1_MBOX_3 0x00013028183#define CS35L41_DSP_VIRT1_MBOX_4 0x0001302C184#define CS35L41_DSP_VIRT1_MBOX_5 0x00013030185#define CS35L41_DSP_VIRT1_MBOX_6 0x00013034186#define CS35L41_DSP_VIRT1_MBOX_7 0x00013038187#define CS35L41_DSP_VIRT1_MBOX_8 0x0001303C188#define CS35L41_DSP_VIRT2_MBOX_1 0x00013040189#define CS35L41_DSP_VIRT2_MBOX_2 0x00013044190#define CS35L41_DSP_VIRT2_MBOX_3 0x00013048191#define CS35L41_DSP_VIRT2_MBOX_4 0x0001304C192#define CS35L41_DSP_VIRT2_MBOX_5 0x00013050193#define CS35L41_DSP_VIRT2_MBOX_6 0x00013054194#define CS35L41_DSP_VIRT2_MBOX_7 0x00013058195#define CS35L41_DSP_VIRT2_MBOX_8 0x0001305C196#define CS35L41_CLOCK_DETECT_1 0x00014000197#define CS35L41_TIMER1_CONTROL 0x00015000198#define CS35L41_TIMER1_COUNT_PRESET 0x00015004199#define CS35L41_TIMER1_START_STOP 0x0001500C200#define CS35L41_TIMER1_STATUS 0x00015010201#define CS35L41_TIMER1_COUNT_READBACK 0x00015014202#define CS35L41_TIMER1_DSP_CLK_CFG 0x00015018203#define CS35L41_TIMER1_DSP_CLK_STATUS 0x0001501C204#define CS35L41_TIMER2_CONTROL 0x00015100205#define CS35L41_TIMER2_COUNT_PRESET 0x00015104206#define CS35L41_TIMER2_START_STOP 0x0001510C207#define CS35L41_TIMER2_STATUS 0x00015110208#define CS35L41_TIMER2_COUNT_READBACK 0x00015114209#define CS35L41_TIMER2_DSP_CLK_CFG 0x00015118210#define CS35L41_TIMER2_DSP_CLK_STATUS 0x0001511C211#define CS35L41_DFT_JTAG_CONTROL 0x00016000212#define CS35L41_DIE_STS1 0x00017040213#define CS35L41_DIE_STS2 0x00017044214#define CS35L41_TEMP_CAL1 0x00017048215#define CS35L41_TEMP_CAL2 0x0001704C216#define CS35L41_DSP1_XMEM_PACK_0 0x02000000217#define CS35L41_DSP1_XMEM_PACK_3068 0x02002FF0218#define CS35L41_DSP1_XMEM_UNPACK32_0 0x02400000219#define CS35L41_DSP1_XMEM_UNPACK32_2046 0x02401FF8220#define CS35L41_DSP1_TIMESTAMP_COUNT 0x025C0800221#define CS35L41_DSP1_SYS_ID 0x025E0000222#define CS35L41_DSP1_SYS_VERSION 0x025E0004223#define CS35L41_DSP1_SYS_CORE_ID 0x025E0008224#define CS35L41_DSP1_SYS_AHB_ADDR 0x025E000C225#define CS35L41_DSP1_SYS_XSRAM_SIZE 0x025E0010226#define CS35L41_DSP1_SYS_YSRAM_SIZE 0x025E0018227#define CS35L41_DSP1_SYS_PSRAM_SIZE 0x025E0020228#define CS35L41_DSP1_SYS_PM_BOOT_SIZE 0x025E0028229#define CS35L41_DSP1_SYS_FEATURES 0x025E002C230#define CS35L41_DSP1_SYS_FIR_FILTERS 0x025E0030231#define CS35L41_DSP1_SYS_LMS_FILTERS 0x025E0034232#define CS35L41_DSP1_SYS_XM_BANK_SIZE 0x025E0038233#define CS35L41_DSP1_SYS_YM_BANK_SIZE 0x025E003C234#define CS35L41_DSP1_SYS_PM_BANK_SIZE 0x025E0040235#define CS35L41_DSP1_AHBM_WIN0_CTRL0 0x025E2000236#define CS35L41_DSP1_AHBM_WIN0_CTRL1 0x025E2004237#define CS35L41_DSP1_AHBM_WIN1_CTRL0 0x025E2008238#define CS35L41_DSP1_AHBM_WIN1_CTRL1 0x025E200C239#define CS35L41_DSP1_AHBM_WIN2_CTRL0 0x025E2010240#define CS35L41_DSP1_AHBM_WIN2_CTRL1 0x025E2014241#define CS35L41_DSP1_AHBM_WIN3_CTRL0 0x025E2018242#define CS35L41_DSP1_AHBM_WIN3_CTRL1 0x025E201C243#define CS35L41_DSP1_AHBM_WIN4_CTRL0 0x025E2020244#define CS35L41_DSP1_AHBM_WIN4_CTRL1 0x025E2024245#define CS35L41_DSP1_AHBM_WIN5_CTRL0 0x025E2028246#define CS35L41_DSP1_AHBM_WIN5_CTRL1 0x025E202C247#define CS35L41_DSP1_AHBM_WIN6_CTRL0 0x025E2030248#define CS35L41_DSP1_AHBM_WIN6_CTRL1 0x025E2034249#define CS35L41_DSP1_AHBM_WIN7_CTRL0 0x025E2038250#define CS35L41_DSP1_AHBM_WIN7_CTRL1 0x025E203C251#define CS35L41_DSP1_AHBM_WIN_DBG_CTRL0 0x025E2040252#define CS35L41_DSP1_AHBM_WIN_DBG_CTRL1 0x025E2044253#define CS35L41_DSP1_XMEM_UNPACK24_0 0x02800000254#define CS35L41_DSP1_XMEM_UNPACK24_4093 0x02803FF4255#define CS35L41_DSP1_CTRL_BASE 0x02B80000256#define CS35L41_DSP1_CORE_SOFT_RESET 0x02B80010257#define CS35L41_DSP1_DEBUG 0x02B80040258#define CS35L41_DSP1_TIMER_CTRL 0x02B80048259#define CS35L41_DSP1_STREAM_ARB_CTRL 0x02B80050260#define CS35L41_DSP1_RX1_RATE 0x02B80080261#define CS35L41_DSP1_RX2_RATE 0x02B80088262#define CS35L41_DSP1_RX3_RATE 0x02B80090263#define CS35L41_DSP1_RX4_RATE 0x02B80098264#define CS35L41_DSP1_RX5_RATE 0x02B800A0265#define CS35L41_DSP1_RX6_RATE 0x02B800A8266#define CS35L41_DSP1_RX7_RATE 0x02B800B0267#define CS35L41_DSP1_RX8_RATE 0x02B800B8268#define CS35L41_DSP1_TX1_RATE 0x02B80280269#define CS35L41_DSP1_TX2_RATE 0x02B80288270#define CS35L41_DSP1_TX3_RATE 0x02B80290271#define CS35L41_DSP1_TX4_RATE 0x02B80298272#define CS35L41_DSP1_TX5_RATE 0x02B802A0273#define CS35L41_DSP1_TX6_RATE 0x02B802A8274#define CS35L41_DSP1_TX7_RATE 0x02B802B0275#define CS35L41_DSP1_TX8_RATE 0x02B802B8276#define CS35L41_DSP1_NMI_CTRL1 0x02B80480277#define CS35L41_DSP1_NMI_CTRL2 0x02B80488278#define CS35L41_DSP1_NMI_CTRL3 0x02B80490279#define CS35L41_DSP1_NMI_CTRL4 0x02B80498280#define CS35L41_DSP1_NMI_CTRL5 0x02B804A0281#define CS35L41_DSP1_NMI_CTRL6 0x02B804A8282#define CS35L41_DSP1_NMI_CTRL7 0x02B804B0283#define CS35L41_DSP1_NMI_CTRL8 0x02B804B8284#define CS35L41_DSP1_RESUME_CTRL 0x02B80500285#define CS35L41_DSP1_IRQ1_CTRL 0x02B80508286#define CS35L41_DSP1_IRQ2_CTRL 0x02B80510287#define CS35L41_DSP1_IRQ3_CTRL 0x02B80518288#define CS35L41_DSP1_IRQ4_CTRL 0x02B80520289#define CS35L41_DSP1_IRQ5_CTRL 0x02B80528290#define CS35L41_DSP1_IRQ6_CTRL 0x02B80530291#define CS35L41_DSP1_IRQ7_CTRL 0x02B80538292#define CS35L41_DSP1_IRQ8_CTRL 0x02B80540293#define CS35L41_DSP1_IRQ9_CTRL 0x02B80548294#define CS35L41_DSP1_IRQ10_CTRL 0x02B80550295#define CS35L41_DSP1_IRQ11_CTRL 0x02B80558296#define CS35L41_DSP1_IRQ12_CTRL 0x02B80560297#define CS35L41_DSP1_IRQ13_CTRL 0x02B80568298#define CS35L41_DSP1_IRQ14_CTRL 0x02B80570299#define CS35L41_DSP1_IRQ15_CTRL 0x02B80578300#define CS35L41_DSP1_IRQ16_CTRL 0x02B80580301#define CS35L41_DSP1_IRQ17_CTRL 0x02B80588302#define CS35L41_DSP1_IRQ18_CTRL 0x02B80590303#define CS35L41_DSP1_IRQ19_CTRL 0x02B80598304#define CS35L41_DSP1_IRQ20_CTRL 0x02B805A0305#define CS35L41_DSP1_IRQ21_CTRL 0x02B805A8306#define CS35L41_DSP1_IRQ22_CTRL 0x02B805B0307#define CS35L41_DSP1_IRQ23_CTRL 0x02B805B8308#define CS35L41_DSP1_SCRATCH1 0x02B805C0309#define CS35L41_DSP1_SCRATCH2 0x02B805C8310#define CS35L41_DSP1_SCRATCH3 0x02B805D0311#define CS35L41_DSP1_SCRATCH4 0x02B805D8312#define CS35L41_DSP1_CCM_CORE_CTRL 0x02BC1000313#define CS35L41_DSP1_CCM_CLK_OVERRIDE 0x02BC1008314#define CS35L41_DSP1_XM_MSTR_EN 0x02BC2000315#define CS35L41_DSP1_XM_CORE_PRI 0x02BC2008316#define CS35L41_DSP1_XM_AHB_PACK_PL_PRI 0x02BC2010317#define CS35L41_DSP1_XM_AHB_UP_PL_PRI 0x02BC2018318#define CS35L41_DSP1_XM_ACCEL_PL0_PRI 0x02BC2020319#define CS35L41_DSP1_XM_NPL0_PRI 0x02BC2078320#define CS35L41_DSP1_YM_MSTR_EN 0x02BC20C0321#define CS35L41_DSP1_YM_CORE_PRI 0x02BC20C8322#define CS35L41_DSP1_YM_AHB_PACK_PL_PRI 0x02BC20D0323#define CS35L41_DSP1_YM_AHB_UP_PL_PRI 0x02BC20D8324#define CS35L41_DSP1_YM_ACCEL_PL0_PRI 0x02BC20E0325#define CS35L41_DSP1_YM_NPL0_PRI 0x02BC2138326#define CS35L41_DSP1_PM_MSTR_EN 0x02BC2180327#define CS35L41_DSP1_PM_PATCH0_ADDR 0x02BC2188328#define CS35L41_DSP1_PM_PATCH0_EN 0x02BC218C329#define CS35L41_DSP1_PM_PATCH0_DATA_LO 0x02BC2190330#define CS35L41_DSP1_PM_PATCH0_DATA_HI 0x02BC2194331#define CS35L41_DSP1_PM_PATCH1_ADDR 0x02BC2198332#define CS35L41_DSP1_PM_PATCH1_EN 0x02BC219C333#define CS35L41_DSP1_PM_PATCH1_DATA_LO 0x02BC21A0334#define CS35L41_DSP1_PM_PATCH1_DATA_HI 0x02BC21A4335#define CS35L41_DSP1_PM_PATCH2_ADDR 0x02BC21A8336#define CS35L41_DSP1_PM_PATCH2_EN 0x02BC21AC337#define CS35L41_DSP1_PM_PATCH2_DATA_LO 0x02BC21B0338#define CS35L41_DSP1_PM_PATCH2_DATA_HI 0x02BC21B4339#define CS35L41_DSP1_PM_PATCH3_ADDR 0x02BC21B8340#define CS35L41_DSP1_PM_PATCH3_EN 0x02BC21BC341#define CS35L41_DSP1_PM_PATCH3_DATA_LO 0x02BC21C0342#define CS35L41_DSP1_PM_PATCH3_DATA_HI 0x02BC21C4343#define CS35L41_DSP1_PM_PATCH4_ADDR 0x02BC21C8344#define CS35L41_DSP1_PM_PATCH4_EN 0x02BC21CC345#define CS35L41_DSP1_PM_PATCH4_DATA_LO 0x02BC21D0346#define CS35L41_DSP1_PM_PATCH4_DATA_HI 0x02BC21D4347#define CS35L41_DSP1_PM_PATCH5_ADDR 0x02BC21D8348#define CS35L41_DSP1_PM_PATCH5_EN 0x02BC21DC349#define CS35L41_DSP1_PM_PATCH5_DATA_LO 0x02BC21E0350#define CS35L41_DSP1_PM_PATCH5_DATA_HI 0x02BC21E4351#define CS35L41_DSP1_PM_PATCH6_ADDR 0x02BC21E8352#define CS35L41_DSP1_PM_PATCH6_EN 0x02BC21EC353#define CS35L41_DSP1_PM_PATCH6_DATA_LO 0x02BC21F0354#define CS35L41_DSP1_PM_PATCH6_DATA_HI 0x02BC21F4355#define CS35L41_DSP1_PM_PATCH7_ADDR 0x02BC21F8356#define CS35L41_DSP1_PM_PATCH7_EN 0x02BC21FC357#define CS35L41_DSP1_PM_PATCH7_DATA_LO 0x02BC2200358#define CS35L41_DSP1_PM_PATCH7_DATA_HI 0x02BC2204359#define CS35L41_DSP1_MPU_XM_ACCESS0 0x02BC3000360#define CS35L41_DSP1_MPU_YM_ACCESS0 0x02BC3004361#define CS35L41_DSP1_MPU_WNDW_ACCESS0 0x02BC3008362#define CS35L41_DSP1_MPU_XREG_ACCESS0 0x02BC300C363#define CS35L41_DSP1_MPU_YREG_ACCESS0 0x02BC3014364#define CS35L41_DSP1_MPU_XM_ACCESS1 0x02BC3018365#define CS35L41_DSP1_MPU_YM_ACCESS1 0x02BC301C366#define CS35L41_DSP1_MPU_WNDW_ACCESS1 0x02BC3020367#define CS35L41_DSP1_MPU_XREG_ACCESS1 0x02BC3024368#define CS35L41_DSP1_MPU_YREG_ACCESS1 0x02BC302C369#define CS35L41_DSP1_MPU_XM_ACCESS2 0x02BC3030370#define CS35L41_DSP1_MPU_YM_ACCESS2 0x02BC3034371#define CS35L41_DSP1_MPU_WNDW_ACCESS2 0x02BC3038372#define CS35L41_DSP1_MPU_XREG_ACCESS2 0x02BC303C373#define CS35L41_DSP1_MPU_YREG_ACCESS2 0x02BC3044374#define CS35L41_DSP1_MPU_XM_ACCESS3 0x02BC3048375#define CS35L41_DSP1_MPU_YM_ACCESS3 0x02BC304C376#define CS35L41_DSP1_MPU_WNDW_ACCESS3 0x02BC3050377#define CS35L41_DSP1_MPU_XREG_ACCESS3 0x02BC3054378#define CS35L41_DSP1_MPU_YREG_ACCESS3 0x02BC305C379#define CS35L41_DSP1_MPU_XM_VIO_ADDR 0x02BC3100380#define CS35L41_DSP1_MPU_XM_VIO_STATUS 0x02BC3104381#define CS35L41_DSP1_MPU_YM_VIO_ADDR 0x02BC3108382#define CS35L41_DSP1_MPU_YM_VIO_STATUS 0x02BC310C383#define CS35L41_DSP1_MPU_PM_VIO_ADDR 0x02BC3110384#define CS35L41_DSP1_MPU_PM_VIO_STATUS 0x02BC3114385#define CS35L41_DSP1_MPU_LOCK_CONFIG 0x02BC3140386#define CS35L41_DSP1_MPU_WDT_RST_CTRL 0x02BC3180387#define CS35L41_DSP1_STRMARB_MSTR0_CFG0 0x02BC5000388#define CS35L41_DSP1_STRMARB_MSTR0_CFG1 0x02BC5004389#define CS35L41_DSP1_STRMARB_MSTR0_CFG2 0x02BC5008390#define CS35L41_DSP1_STRMARB_MSTR1_CFG0 0x02BC5010391#define CS35L41_DSP1_STRMARB_MSTR1_CFG1 0x02BC5014392#define CS35L41_DSP1_STRMARB_MSTR1_CFG2 0x02BC5018393#define CS35L41_DSP1_STRMARB_MSTR2_CFG0 0x02BC5020394#define CS35L41_DSP1_STRMARB_MSTR2_CFG1 0x02BC5024395#define CS35L41_DSP1_STRMARB_MSTR2_CFG2 0x02BC5028396#define CS35L41_DSP1_STRMARB_MSTR3_CFG0 0x02BC5030397#define CS35L41_DSP1_STRMARB_MSTR3_CFG1 0x02BC5034398#define CS35L41_DSP1_STRMARB_MSTR3_CFG2 0x02BC5038399#define CS35L41_DSP1_STRMARB_MSTR4_CFG0 0x02BC5040400#define CS35L41_DSP1_STRMARB_MSTR4_CFG1 0x02BC5044401#define CS35L41_DSP1_STRMARB_MSTR4_CFG2 0x02BC5048402#define CS35L41_DSP1_STRMARB_MSTR5_CFG0 0x02BC5050403#define CS35L41_DSP1_STRMARB_MSTR5_CFG1 0x02BC5054404#define CS35L41_DSP1_STRMARB_MSTR5_CFG2 0x02BC5058405#define CS35L41_DSP1_STRMARB_MSTR6_CFG0 0x02BC5060406#define CS35L41_DSP1_STRMARB_MSTR6_CFG1 0x02BC5064407#define CS35L41_DSP1_STRMARB_MSTR6_CFG2 0x02BC5068408#define CS35L41_DSP1_STRMARB_MSTR7_CFG0 0x02BC5070409#define CS35L41_DSP1_STRMARB_MSTR7_CFG1 0x02BC5074410#define CS35L41_DSP1_STRMARB_MSTR7_CFG2 0x02BC5078411#define CS35L41_DSP1_STRMARB_TX0_CFG0 0x02BC5200412#define CS35L41_DSP1_STRMARB_TX0_CFG1 0x02BC5204413#define CS35L41_DSP1_STRMARB_TX1_CFG0 0x02BC5208414#define CS35L41_DSP1_STRMARB_TX1_CFG1 0x02BC520C415#define CS35L41_DSP1_STRMARB_TX2_CFG0 0x02BC5210416#define CS35L41_DSP1_STRMARB_TX2_CFG1 0x02BC5214417#define CS35L41_DSP1_STRMARB_TX3_CFG0 0x02BC5218418#define CS35L41_DSP1_STRMARB_TX3_CFG1 0x02BC521C419#define CS35L41_DSP1_STRMARB_TX4_CFG0 0x02BC5220420#define CS35L41_DSP1_STRMARB_TX4_CFG1 0x02BC5224421#define CS35L41_DSP1_STRMARB_TX5_CFG0 0x02BC5228422#define CS35L41_DSP1_STRMARB_TX5_CFG1 0x02BC522C423#define CS35L41_DSP1_STRMARB_TX6_CFG0 0x02BC5230424#define CS35L41_DSP1_STRMARB_TX6_CFG1 0x02BC5234425#define CS35L41_DSP1_STRMARB_TX7_CFG0 0x02BC5238426#define CS35L41_DSP1_STRMARB_TX7_CFG1 0x02BC523C427#define CS35L41_DSP1_STRMARB_RX0_CFG0 0x02BC5400428#define CS35L41_DSP1_STRMARB_RX0_CFG1 0x02BC5404429#define CS35L41_DSP1_STRMARB_RX1_CFG0 0x02BC5408430#define CS35L41_DSP1_STRMARB_RX1_CFG1 0x02BC540C431#define CS35L41_DSP1_STRMARB_RX2_CFG0 0x02BC5410432#define CS35L41_DSP1_STRMARB_RX2_CFG1 0x02BC5414433#define CS35L41_DSP1_STRMARB_RX3_CFG0 0x02BC5418434#define CS35L41_DSP1_STRMARB_RX3_CFG1 0x02BC541C435#define CS35L41_DSP1_STRMARB_RX4_CFG0 0x02BC5420436#define CS35L41_DSP1_STRMARB_RX4_CFG1 0x02BC5424437#define CS35L41_DSP1_STRMARB_RX5_CFG0 0x02BC5428438#define CS35L41_DSP1_STRMARB_RX5_CFG1 0x02BC542C439#define CS35L41_DSP1_STRMARB_RX6_CFG0 0x02BC5430440#define CS35L41_DSP1_STRMARB_RX6_CFG1 0x02BC5434441#define CS35L41_DSP1_STRMARB_RX7_CFG0 0x02BC5438442#define CS35L41_DSP1_STRMARB_RX7_CFG1 0x02BC543C443#define CS35L41_DSP1_STRMARB_IRQ0_CFG0 0x02BC5600444#define CS35L41_DSP1_STRMARB_IRQ0_CFG1 0x02BC5604445#define CS35L41_DSP1_STRMARB_IRQ0_CFG2 0x02BC5608446#define CS35L41_DSP1_STRMARB_IRQ1_CFG0 0x02BC5610447#define CS35L41_DSP1_STRMARB_IRQ1_CFG1 0x02BC5614448#define CS35L41_DSP1_STRMARB_IRQ1_CFG2 0x02BC5618449#define CS35L41_DSP1_STRMARB_IRQ2_CFG0 0x02BC5620450#define CS35L41_DSP1_STRMARB_IRQ2_CFG1 0x02BC5624451#define CS35L41_DSP1_STRMARB_IRQ2_CFG2 0x02BC5628452#define CS35L41_DSP1_STRMARB_IRQ3_CFG0 0x02BC5630453#define CS35L41_DSP1_STRMARB_IRQ3_CFG1 0x02BC5634454#define CS35L41_DSP1_STRMARB_IRQ3_CFG2 0x02BC5638455#define CS35L41_DSP1_STRMARB_IRQ4_CFG0 0x02BC5640456#define CS35L41_DSP1_STRMARB_IRQ4_CFG1 0x02BC5644457#define CS35L41_DSP1_STRMARB_IRQ4_CFG2 0x02BC5648458#define CS35L41_DSP1_STRMARB_IRQ5_CFG0 0x02BC5650459#define CS35L41_DSP1_STRMARB_IRQ5_CFG1 0x02BC5654460#define CS35L41_DSP1_STRMARB_IRQ5_CFG2 0x02BC5658461#define CS35L41_DSP1_STRMARB_IRQ6_CFG0 0x02BC5660462#define CS35L41_DSP1_STRMARB_IRQ6_CFG1 0x02BC5664463#define CS35L41_DSP1_STRMARB_IRQ6_CFG2 0x02BC5668464#define CS35L41_DSP1_STRMARB_IRQ7_CFG0 0x02BC5670465#define CS35L41_DSP1_STRMARB_IRQ7_CFG1 0x02BC5674466#define CS35L41_DSP1_STRMARB_IRQ7_CFG2 0x02BC5678467#define CS35L41_DSP1_STRMARB_RESYNC_MSK 0x02BC5A00468#define CS35L41_DSP1_STRMARB_ERR_STATUS 0x02BC5A08469#define CS35L41_DSP1_INTPCTL_RES_STATIC 0x02BC6000470#define CS35L41_DSP1_INTPCTL_RES_DYN 0x02BC6004471#define CS35L41_DSP1_INTPCTL_NMI_CTRL 0x02BC6008472#define CS35L41_DSP1_INTPCTL_IRQ_INV 0x02BC6010473#define CS35L41_DSP1_INTPCTL_IRQ_MODE 0x02BC6014474#define CS35L41_DSP1_INTPCTL_IRQ_EN 0x02BC6018475#define CS35L41_DSP1_INTPCTL_IRQ_MSK 0x02BC601C476#define CS35L41_DSP1_INTPCTL_IRQ_FLUSH 0x02BC6020477#define CS35L41_DSP1_INTPCTL_IRQ_MSKCLR 0x02BC6024478#define CS35L41_DSP1_INTPCTL_IRQ_FRC 0x02BC6028479#define CS35L41_DSP1_INTPCTL_IRQ_MSKSET 0x02BC602C480#define CS35L41_DSP1_INTPCTL_IRQ_ERR 0x02BC6030481#define CS35L41_DSP1_INTPCTL_IRQ_PEND 0x02BC6034482#define CS35L41_DSP1_INTPCTL_IRQ_GEN 0x02BC6038483#define CS35L41_DSP1_INTPCTL_TESTBITS 0x02BC6040484#define CS35L41_DSP1_WDT_CONTROL 0x02BC7000485#define CS35L41_DSP1_WDT_STATUS 0x02BC7008486#define CS35L41_DSP1_YMEM_PACK_0 0x02C00000487#define CS35L41_DSP1_YMEM_PACK_1532 0x02C017F0488#define CS35L41_DSP1_YMEM_UNPACK32_0 0x03000000489#define CS35L41_DSP1_YMEM_UNPACK32_1022 0x03000FF8490#define CS35L41_DSP1_YMEM_UNPACK24_0 0x03400000491#define CS35L41_DSP1_YMEM_UNPACK24_2045 0x03401FF4492#define CS35L41_DSP1_PMEM_0 0x03800000493#define CS35L41_DSP1_PMEM_5114 0x03804FE8494 495/*test regs for emulation bringup*/496#define CS35L41_PLL_OVR 0x00003018497#define CS35L41_BST_TEST_DUTY 0x00003900498#define CS35L41_DIGPWM_IOCTRL 0x0000706C499 500/*registers populated by OTP*/501#define CS35L41_OTP_TRIM_1 0x0000208c502#define CS35L41_OTP_TRIM_2 0x00002090503#define CS35L41_OTP_TRIM_3 0x00003010504#define CS35L41_OTP_TRIM_4 0x0000300C505#define CS35L41_OTP_TRIM_5 0x0000394C506#define CS35L41_OTP_TRIM_6 0x00003950507#define CS35L41_OTP_TRIM_7 0x00003954508#define CS35L41_OTP_TRIM_8 0x00003958509#define CS35L41_OTP_TRIM_9 0x0000395C510#define CS35L41_OTP_TRIM_10 0x0000416C511#define CS35L41_OTP_TRIM_11 0x00004160512#define CS35L41_OTP_TRIM_12 0x00004170513#define CS35L41_OTP_TRIM_13 0x00004360514#define CS35L41_OTP_TRIM_14 0x00004448515#define CS35L41_OTP_TRIM_15 0x0000444C516#define CS35L41_OTP_TRIM_16 0x00006E30517#define CS35L41_OTP_TRIM_17 0x00006E34518#define CS35L41_OTP_TRIM_18 0x00006E38519#define CS35L41_OTP_TRIM_19 0x00006E3C520#define CS35L41_OTP_TRIM_20 0x00006E40521#define CS35L41_OTP_TRIM_21 0x00006E44522#define CS35L41_OTP_TRIM_22 0x00006E48523#define CS35L41_OTP_TRIM_23 0x00006E4C524#define CS35L41_OTP_TRIM_24 0x00006E50525#define CS35L41_OTP_TRIM_25 0x00006E54526#define CS35L41_OTP_TRIM_26 0x00006E58527#define CS35L41_OTP_TRIM_27 0x00006E5C528#define CS35L41_OTP_TRIM_28 0x00006E60529#define CS35L41_OTP_TRIM_29 0x00006E64530#define CS35L41_OTP_TRIM_30 0x00007418531#define CS35L41_OTP_TRIM_31 0x0000741C532#define CS35L41_OTP_TRIM_32 0x00007434533#define CS35L41_OTP_TRIM_33 0x00007068534#define CS35L41_OTP_TRIM_34 0x0000410C535#define CS35L41_OTP_TRIM_35 0x0000400C536#define CS35L41_OTP_TRIM_36 0x00002030537 538#define CS35L41_MAX_CACHE_REG 36539#define CS35L41_OTP_SIZE_WORDS 32540 541#define CS35L41_NUM_SUPPLIES 2542 543#define CS35L41_SCLK_MSTR_MASK 0x10544#define CS35L41_SCLK_MSTR_SHIFT 4545#define CS35L41_LRCLK_MSTR_MASK 0x01546#define CS35L41_LRCLK_MSTR_SHIFT 0547#define CS35L41_SCLK_INV_MASK 0x40548#define CS35L41_SCLK_INV_SHIFT 6549#define CS35L41_LRCLK_INV_MASK 0x04550#define CS35L41_LRCLK_INV_SHIFT 2551#define CS35L41_SCLK_FRC_MASK 0x20552#define CS35L41_SCLK_FRC_SHIFT 5553#define CS35L41_LRCLK_FRC_MASK 0x02554#define CS35L41_LRCLK_FRC_SHIFT 1555 556#define CS35L41_AMP_GAIN_PCM_MASK 0x3E0557#define CS35L41_AMP_GAIN_PCM_SHIFT 5558#define CS35L41_AMP_GAIN_PDM_MASK 0x1F559#define CS35L41_AMP_GAIN_PDM_SHIFT 0560#define CS35L41_AMP_GAIN_PCM_MAX 20561#define CS35L41_AMP_GAIN_PDM_MAX 20562#define CS35L41_AMP_GAIN_ZC_MASK 0x0400563#define CS35L41_AMP_GAIN_ZC_SHIFT 10564 565#define CS35L41_BST_CTL_MASK 0xFF566#define CS35L41_BST_CTL_SEL_MASK 0x03567#define CS35L41_BST_CTL_SEL_REG 0x00568#define CS35L41_BST_CTL_SEL_CLASSH 0x01569#define CS35L41_BST_IPK_MASK 0x7F570#define CS35L41_BST_IPK_SHIFT 0571#define CS35L41_BST_LIM_MASK 0x4572#define CS35L41_BST_LIM_SHIFT 2573#define CS35L41_BST_K1_MASK 0x000000FF574#define CS35L41_BST_K1_SHIFT 0575#define CS35L41_BST_K2_MASK 0x0000FF00576#define CS35L41_BST_K2_SHIFT 8577#define CS35L41_BST_SLOPE_MASK 0x0000FF00578#define CS35L41_BST_SLOPE_SHIFT 8579#define CS35L41_BST_LBST_VAL_MASK 0x00000003580#define CS35L41_BST_LBST_VAL_SHIFT 0581 582#define CS35L41_TEMP_THLD_MASK 0x03583#define CS35L41_VMON_IMON_VOL_MASK 0x07FF07FF584#define CS35L41_PDM_MODE_MASK 0x01585#define CS35L41_PDM_MODE_SHIFT 0586 587#define CS35L41_CH_MEM_DEPTH_MASK 0x07588#define CS35L41_CH_MEM_DEPTH_SHIFT 0589#define CS35L41_CH_HDRM_CTL_MASK 0x007F0000590#define CS35L41_CH_HDRM_CTL_SHIFT 16591#define CS35L41_CH_REL_RATE_MASK 0xFF00592#define CS35L41_CH_REL_RATE_SHIFT 8593#define CS35L41_CH_WKFET_DLY_MASK 0x001C594#define CS35L41_CH_WKFET_DLY_SHIFT 2595#define CS35L41_CH_WKFET_THLD_MASK 0x0F00596#define CS35L41_CH_WKFET_THLD_SHIFT 8597 598#define CS35L41_HW_NG_SEL_MASK 0x3F00599#define CS35L41_HW_NG_SEL_SHIFT 8600#define CS35L41_HW_NG_DLY_MASK 0x0070601#define CS35L41_HW_NG_DLY_SHIFT 4602#define CS35L41_HW_NG_THLD_MASK 0x0007603#define CS35L41_HW_NG_THLD_SHIFT 0604 605#define CS35L41_DSP_NG_ENABLE_MASK 0x00010000606#define CS35L41_DSP_NG_ENABLE_SHIFT 16607#define CS35L41_DSP_NG_THLD_MASK 0x7608#define CS35L41_DSP_NG_THLD_SHIFT 0609#define CS35L41_DSP_NG_DELAY_MASK 0x0F00610#define CS35L41_DSP_NG_DELAY_SHIFT 8611 612#define CS35L41_ASP_FMT_MASK 0x0700613#define CS35L41_ASP_FMT_SHIFT 8614#define CS35L41_ASP_DOUT_HIZ_MASK 0x03615#define CS35L41_ASP_DOUT_HIZ_SHIFT 0616#define CS35L41_ASP_WIDTH_16 0x10617#define CS35L41_ASP_WIDTH_24 0x18618#define CS35L41_ASP_WIDTH_32 0x20619#define CS35L41_ASP_WIDTH_TX_MASK 0xFF0000620#define CS35L41_ASP_WIDTH_TX_SHIFT 16621#define CS35L41_ASP_WIDTH_RX_MASK 0xFF000000622#define CS35L41_ASP_WIDTH_RX_SHIFT 24623#define CS35L41_ASP_RX1_SLOT_MASK 0x3F624#define CS35L41_ASP_RX1_SLOT_SHIFT 0625#define CS35L41_ASP_RX2_SLOT_MASK 0x3F00626#define CS35L41_ASP_RX2_SLOT_SHIFT 8627#define CS35L41_ASP_RX_WL_MASK 0x3F628#define CS35L41_ASP_TX_WL_MASK 0x3F629#define CS35L41_ASP_RX_WL_SHIFT 0630#define CS35L41_ASP_TX_WL_SHIFT 0631#define CS35L41_ASP_SOURCE_MASK 0x7F632 633#define CS35L41_INPUT_SRC_ASPRX1 0x08634#define CS35L41_INPUT_SRC_ASPRX2 0x09635#define CS35L41_INPUT_SRC_VMON 0x18636#define CS35L41_INPUT_SRC_IMON 0x19637#define CS35L41_INPUT_SRC_CLASSH 0x21638#define CS35L41_INPUT_SRC_VPMON 0x28639#define CS35L41_INPUT_SRC_VBSTMON 0x29640#define CS35L41_INPUT_SRC_TEMPMON 0x3A641#define CS35L41_INPUT_SRC_RSVD 0x3B642#define CS35L41_INPUT_DSP_TX1 0x32643#define CS35L41_INPUT_DSP_TX2 0x33644 645#define CS35L41_WR_PEND_STS_MASK 0x2646 647#define CS35L41_PLL_CLK_SEL_MASK 0x07648#define CS35L41_PLL_CLK_SEL_SHIFT 0649#define CS35L41_PLL_CLK_EN_MASK 0x10650#define CS35L41_PLL_CLK_EN_SHIFT 4651#define CS35L41_PLL_OPENLOOP_MASK 0x0800652#define CS35L41_PLL_OPENLOOP_SHIFT 11653#define CS35L41_PLLSRC_SCLK 0654#define CS35L41_PLLSRC_LRCLK 1655#define CS35L41_PLLSRC_SELF 3656#define CS35L41_PLLSRC_PDMCLK 4657#define CS35L41_PLLSRC_MCLK 5658#define CS35L41_PLLSRC_SWIRE 7659#define CS35L41_REFCLK_FREQ_MASK 0x7E0660#define CS35L41_REFCLK_FREQ_SHIFT 5661 662#define CS35L41_GLOBAL_FS_MASK 0x1F663#define CS35L41_GLOBAL_FS_SHIFT 0664 665#define CS35L41_GLOBAL_EN_MASK 0x01666#define CS35L41_GLOBAL_EN_SHIFT 0667#define CS35L41_BST_EN_MASK 0x0030668#define CS35L41_BST_EN_SHIFT 4669#define CS35L41_BST_DIS_FET_OFF 0x00670#define CS35L41_BST_EN_DEFAULT 0x2671#define CS35L41_AMP_EN_SHIFT 0672#define CS35L41_AMP_EN_MASK 1673#define CS35L41_VMON_EN_MASK 0x1000674#define CS35L41_VMON_EN_SHIFT 12675#define CS35L41_IMON_EN_MASK 0x2000676#define CS35L41_IMON_EN_SHIFT 13677 678#define CS35L41_PDN_DONE_MASK 0x00800000679#define CS35L41_PDN_DONE_SHIFT 23680#define CS35L41_PUP_DONE_MASK 0x01000000681#define CS35L41_PUP_DONE_SHIFT 24682 683#define CS35L36_PUP_DONE_IRQ_UNMASK 0x5F684#define CS35L36_PUP_DONE_IRQ_MASK 0xBF685#define CS35L41_SYNC_EN_MASK BIT(8)686 687#define CS35L41_AMP_SHORT_ERR 0x80000000688#define CS35L41_BST_SHORT_ERR 0x0100689#define CS35L41_TEMP_WARN 0x8000690#define CS35L41_TEMP_ERR 0x00020000691#define CS35L41_BST_OVP_ERR 0x40692#define CS35L41_BST_DCM_UVP_ERR 0x80693#define CS35L41_OTP_BOOT_DONE 0x02694#define CS35L41_PLL_UNLOCK 0x10695#define CS35L41_PLL_LOCK BIT(1)696#define CS35L41_OTP_BOOT_ERR 0x80000000697 698#define CS35L41_AMP_SHORT_ERR_RLS 0x02699#define CS35L41_BST_SHORT_ERR_RLS 0x04700#define CS35L41_BST_OVP_ERR_RLS 0x08701#define CS35L41_BST_UVP_ERR_RLS 0x10702#define CS35L41_TEMP_WARN_ERR_RLS 0x20703#define CS35L41_TEMP_ERR_RLS 0x40704 705#define CS35L41_AMP_SHORT_ERR_RLS_SHIFT 1706#define CS35L41_BST_SHORT_ERR_RLS_SHIFT 2707#define CS35L41_BST_OVP_ERR_RLS_SHIFT 3708#define CS35L41_BST_UVP_ERR_RLS_SHIFT 4709#define CS35L41_TEMP_WARN_ERR_RLS_SHIFT 5710#define CS35L41_TEMP_ERR_RLS_SHIFT 6711 712#define CS35L41_INT1_MASK_DEFAULT 0x7FFCFE3F713#define CS35L41_INT1_UNMASK_PUP 0xFEFFFFFF714#define CS35L41_INT1_UNMASK_PDN 0xFF7FFFFF715#define CS35L41_INT3_PLL_LOCK_SHIFT 1716#define CS35L41_INT3_PLL_LOCK_MASK BIT(CS35L41_INT3_PLL_LOCK_SHIFT)717 718#define CS35L41_GPIO_DIR_MASK 0x80000000719#define CS35L41_GPIO_DIR_SHIFT 31720#define CS35L41_GPIO1_CTRL_MASK 0x00030000721#define CS35L41_GPIO1_CTRL_SHIFT 16722#define CS35L41_GPIO2_CTRL_MASK 0x07000000723#define CS35L41_GPIO2_CTRL_SHIFT 24724#define CS35L41_GPIO_LVL_SHIFT 15725#define CS35L41_GPIO_LVL_MASK BIT(CS35L41_GPIO_LVL_SHIFT)726#define CS35L41_GPIO_POL_MASK 0x1000727#define CS35L41_GPIO_POL_SHIFT 12728 729#define CS35L41_AMP_INV_PCM_SHIFT 14730#define CS35L41_AMP_INV_PCM_MASK BIT(CS35L41_AMP_INV_PCM_SHIFT)731#define CS35L41_AMP_PCM_VOL_SHIFT 3732#define CS35L41_AMP_PCM_VOL_MASK (0x7FF << 3)733#define CS35L41_AMP_PCM_VOL_MUTE 0x4CF734 735#define CS35L41_CHIP_ID 0x35a40736#define CS35L41R_CHIP_ID 0x35b40737#define CS35L41_MTLREVID_MASK 0x0F738#define CS35L41_REVID_A0 0xA0739#define CS35L41_REVID_B0 0xB0740#define CS35L41_REVID_B2 0xB2741 742#define CS35L41_HALO_CORE_RESET 0x00000200743#define CS35L41_SOFTWARE_RESET 0x5A000000744 745#define CS35L41_FS1_WINDOW_MASK 0x000007FF746#define CS35L41_FS2_WINDOW_MASK 0x00FFF800747#define CS35L41_FS2_WINDOW_SHIFT 12748 749#define CS35L41_SPI_MAX_FREQ 4000000750#define CS35L41_REGSTRIDE 4751 752enum cs35l41_boost_type {753 CS35L41_INT_BOOST,754 CS35L41_EXT_BOOST,755 CS35L41_SHD_BOOST_ACTV,756 CS35L41_SHD_BOOST_PASS,757 758 // Not present in Binding Documentation, so no system should use this value.759 // This value is only used in CLSA0100 Laptop760 CS35L41_EXT_BOOST_NO_VSPK_SWITCH,761};762 763enum cs35l41_clk_ids {764 CS35L41_CLKID_SCLK = 0,765 CS35L41_CLKID_LRCLK = 1,766 CS35L41_CLKID_MCLK = 4,767};768 769enum cs35l41_gpio1_func {770 CS35L41_GPIO1_HIZ,771 CS35L41_GPIO1_GPIO,772 CS35L41_GPIO1_MDSYNC,773 CS35L41_GPIO1_MCLK,774 CS35L41_GPIO1_PDM_CLK,775 CS35L41_GPIO1_PDM_DATA,776};777 778enum cs35l41_gpio2_func {779 CS35L41_GPIO2_HIZ,780 CS35L41_GPIO2_GPIO,781 CS35L41_GPIO2_INT_OPEN_DRAIN,782 CS35L41_GPIO2_MCLK,783 CS35L41_GPIO2_INT_PUSH_PULL_LOW,784 CS35L41_GPIO2_INT_PUSH_PULL_HIGH,785 CS35L41_GPIO2_PDM_CLK,786 CS35L41_GPIO2_PDM_DATA,787};788 789struct cs35l41_gpio_cfg {790 bool valid;791 bool pol_inv;792 bool out_en;793 unsigned int func;794};795 796struct cs35l41_hw_cfg {797 bool valid;798 int bst_ind;799 int bst_ipk;800 int bst_cap;801 int dout_hiz;802 struct cs35l41_gpio_cfg gpio1;803 struct cs35l41_gpio_cfg gpio2;804 unsigned int spk_pos;805 806 enum cs35l41_boost_type bst_type;807};808 809struct cs35l41_otp_packed_element_t {810 u32 reg;811 u8 shift;812 u8 size;813};814 815struct cs35l41_otp_map_element_t {816 u32 id;817 u32 num_elements;818 const struct cs35l41_otp_packed_element_t *map;819 u32 bit_offset;820 u32 word_offset;821};822 823enum cs35l41_cspl_mbox_status {824 CSPL_MBOX_STS_ERROR = U32_MAX,825 CSPL_MBOX_STS_ERROR2 = 0x00ffffff, // firmware not always sign-extending 24-bit value826 CSPL_MBOX_STS_RUNNING = 0,827 CSPL_MBOX_STS_PAUSED = 1,828 CSPL_MBOX_STS_RDY_FOR_REINIT = 2,829};830 831enum cs35l41_cspl_mbox_cmd {832 CSPL_MBOX_CMD_NONE = 0,833 CSPL_MBOX_CMD_PAUSE = 1,834 CSPL_MBOX_CMD_RESUME = 2,835 CSPL_MBOX_CMD_REINIT = 3,836 CSPL_MBOX_CMD_STOP_PRE_REINIT = 4,837 CSPL_MBOX_CMD_HIBERNATE = 5,838 CSPL_MBOX_CMD_OUT_OF_HIBERNATE = 6,839 CSPL_MBOX_CMD_SPK_OUT_ENABLE = 7,840 CSPL_MBOX_CMD_UNKNOWN_CMD = -1,841 CSPL_MBOX_CMD_INVALID_SEQUENCE = -2,842};843 844/*845 * IRQs846 */847#define CS35L41_IRQ(_irq, _name, _hand) \848 { \849 .irq = CS35L41_ ## _irq ## _IRQ,\850 .name = _name, \851 .handler = _hand, \852 }853 854struct cs35l41_irq {855 int irq;856 const char *name;857 irqreturn_t (*handler)(int irq, void *data);858};859 860#define CS35L41_REG_IRQ(_reg, _irq) \861 [CS35L41_ ## _irq ## _IRQ] = { \862 .reg_offset = (CS35L41_ ## _reg) - CS35L41_IRQ1_STATUS1,\863 .mask = CS35L41_ ## _irq ## _MASK \864 }865 866/* (0x0000E010) CS35L41_IRQ1_STATUS1 */867#define CS35L41_BST_OVP_ERR_SHIFT 6868#define CS35L41_BST_OVP_ERR_MASK BIT(CS35L41_BST_OVP_ERR_SHIFT)869#define CS35L41_BST_DCM_UVP_ERR_SHIFT 7870#define CS35L41_BST_DCM_UVP_ERR_MASK BIT(CS35L41_BST_DCM_UVP_ERR_SHIFT)871#define CS35L41_BST_SHORT_ERR_SHIFT 8872#define CS35L41_BST_SHORT_ERR_MASK BIT(CS35L41_BST_SHORT_ERR_SHIFT)873#define CS35L41_TEMP_WARN_SHIFT 15874#define CS35L41_TEMP_WARN_MASK BIT(CS35L41_TEMP_WARN_SHIFT)875#define CS35L41_TEMP_ERR_SHIFT 17876#define CS35L41_TEMP_ERR_MASK BIT(CS35L41_TEMP_ERR_SHIFT)877#define CS35L41_AMP_SHORT_ERR_SHIFT 31878#define CS35L41_AMP_SHORT_ERR_MASK BIT(CS35L41_AMP_SHORT_ERR_SHIFT)879 880enum cs35l41_irq_list {881 CS35L41_BST_OVP_ERR_IRQ,882 CS35L41_BST_DCM_UVP_ERR_IRQ,883 CS35L41_BST_SHORT_ERR_IRQ,884 CS35L41_TEMP_WARN_IRQ,885 CS35L41_TEMP_ERR_IRQ,886 CS35L41_AMP_SHORT_ERR_IRQ,887 888 CS35L41_NUM_IRQ889};890 891extern struct regmap_config cs35l41_regmap_i2c;892extern struct regmap_config cs35l41_regmap_spi;893 894int cs35l41_test_key_unlock(struct device *dev, struct regmap *regmap);895int cs35l41_test_key_lock(struct device *dev, struct regmap *regmap);896int cs35l41_otp_unpack(struct device *dev, struct regmap *regmap);897int cs35l41_register_errata_patch(struct device *dev, struct regmap *reg, unsigned int reg_revid);898int cs35l41_set_channels(struct device *dev, struct regmap *reg,899 unsigned int tx_num, const unsigned int *tx_slot,900 unsigned int rx_num, const unsigned int *rx_slot);901int cs35l41_gpio_config(struct regmap *regmap, struct cs35l41_hw_cfg *hw_cfg);902void cs35l41_configure_cs_dsp(struct device *dev, struct regmap *reg, struct cs_dsp *dsp);903int cs35l41_set_cspl_mbox_cmd(struct device *dev, struct regmap *regmap,904 enum cs35l41_cspl_mbox_cmd cmd);905int cs35l41_write_fs_errata(struct device *dev, struct regmap *regmap);906int cs35l41_enter_hibernate(struct device *dev, struct regmap *regmap,907 enum cs35l41_boost_type b_type);908int cs35l41_exit_hibernate(struct device *dev, struct regmap *regmap);909int cs35l41_init_boost(struct device *dev, struct regmap *regmap,910 struct cs35l41_hw_cfg *hw_cfg);911bool cs35l41_safe_reset(struct regmap *regmap, enum cs35l41_boost_type b_type);912int cs35l41_mdsync_up(struct regmap *regmap);913int cs35l41_global_enable(struct device *dev, struct regmap *regmap, enum cs35l41_boost_type b_type,914 int enable, struct cs_dsp *dsp);915 916#endif /* __CS35L41_H */917