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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * HD-audio controller (Azalia) registers and helpers4 *5 * For traditional reasons, we still use azx_ prefix here6 */7 8#ifndef __SOUND_HDA_REGISTER_H9#define __SOUND_HDA_REGISTER_H10 11#include <linux/io.h>12#include <sound/hdaudio.h>13 14#define AZX_REG_GCAP 0x0015#define AZX_GCAP_64OK (1 << 0) /* 64bit address support */16#define AZX_GCAP_NSDO (3 << 1) /* # of serial data out signals */17#define AZX_GCAP_BSS (31 << 3) /* # of bidirectional streams */18#define AZX_GCAP_ISS (15 << 8) /* # of input streams */19#define AZX_GCAP_OSS (15 << 12) /* # of output streams */20#define AZX_REG_VMIN 0x0221#define AZX_REG_VMAJ 0x0322#define AZX_REG_OUTPAY 0x0423#define AZX_REG_INPAY 0x0624#define AZX_REG_GCTL 0x0825#define AZX_GCTL_RESET (1 << 0) /* controller reset */26#define AZX_GCTL_FCNTRL (1 << 1) /* flush control */27#define AZX_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */28#define AZX_REG_WAKEEN 0x0c29#define AZX_REG_STATESTS 0x0e30#define AZX_REG_GSTS 0x1031#define AZX_GSTS_FSTS (1 << 1) /* flush status */32#define AZX_REG_GCAP2 0x1233#define AZX_REG_LLCH 0x1434#define AZX_REG_OUTSTRMPAY 0x1835#define AZX_REG_INSTRMPAY 0x1A36#define AZX_REG_INTCTL 0x2037#define AZX_REG_INTSTS 0x2438#define AZX_REG_WALLCLK 0x30 /* 24Mhz source */39#define AZX_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */40#define AZX_REG_SSYNC 0x3841#define AZX_REG_CORBLBASE 0x4042#define AZX_REG_CORBUBASE 0x4443#define AZX_REG_CORBWP 0x4844#define AZX_REG_CORBRP 0x4a45#define AZX_CORBRP_RST (1 << 15) /* read pointer reset */46#define AZX_REG_CORBCTL 0x4c47#define AZX_CORBCTL_RUN (1 << 1) /* enable DMA */48#define AZX_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */49#define AZX_REG_CORBSTS 0x4d50#define AZX_CORBSTS_CMEI (1 << 0) /* memory error indication */51#define AZX_REG_CORBSIZE 0x4e52 53#define AZX_REG_RIRBLBASE 0x5054#define AZX_REG_RIRBUBASE 0x5455#define AZX_REG_RIRBWP 0x5856#define AZX_RIRBWP_RST (1 << 15) /* write pointer reset */57#define AZX_REG_RINTCNT 0x5a58#define AZX_REG_RIRBCTL 0x5c59#define AZX_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */60#define AZX_RBCTL_DMA_EN (1 << 1) /* enable DMA */61#define AZX_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */62#define AZX_REG_RIRBSTS 0x5d63#define AZX_RBSTS_IRQ (1 << 0) /* response irq */64#define AZX_RBSTS_OVERRUN (1 << 2) /* overrun irq */65#define AZX_REG_RIRBSIZE 0x5e66 67#define AZX_REG_IC 0x6068#define AZX_REG_IR 0x6469#define AZX_REG_IRS 0x6870#define AZX_IRS_VALID (1<<1)71#define AZX_IRS_BUSY (1<<0)72 73#define AZX_REG_DPLBASE 0x7074#define AZX_REG_DPUBASE 0x7475#define AZX_DPLBASE_ENABLE 0x1 /* Enable position buffer */76 77/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */78enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };79 80/* stream register offsets from stream base */81#define AZX_REG_SD_CTL 0x0082#define AZX_REG_SD_CTL_3B 0x02 /* 3rd byte of SD_CTL register */83#define AZX_REG_SD_STS 0x0384#define AZX_REG_SD_LPIB 0x0485#define AZX_REG_SD_CBL 0x0886#define AZX_REG_SD_LVI 0x0c87#define AZX_REG_SD_FIFOW 0x0e88#define AZX_REG_SD_FIFOSIZE 0x1089#define AZX_REG_SD_FORMAT 0x1290#define AZX_REG_SD_FIFOL 0x1491#define AZX_REG_SD_BDLPL 0x1892#define AZX_REG_SD_BDLPU 0x1c93 94#define AZX_SD_FIFOSIZE_MASK GENMASK(15, 0)95 96/* GTS registers */97#define AZX_REG_LLCH 0x1498 99#define AZX_REG_GTS_BASE 0x520100 101#define AZX_REG_GTSCC (AZX_REG_GTS_BASE + 0x00)102#define AZX_REG_WALFCC (AZX_REG_GTS_BASE + 0x04)103#define AZX_REG_TSCCL (AZX_REG_GTS_BASE + 0x08)104#define AZX_REG_TSCCU (AZX_REG_GTS_BASE + 0x0C)105#define AZX_REG_LLPFOC (AZX_REG_GTS_BASE + 0x14)106#define AZX_REG_LLPCL (AZX_REG_GTS_BASE + 0x18)107#define AZX_REG_LLPCU (AZX_REG_GTS_BASE + 0x1C)108 109/* Haswell/Broadwell display HD-A controller Extended Mode registers */110#define AZX_REG_HSW_EM4 0x100c111#define AZX_REG_HSW_EM5 0x1010112 113/* Skylake/Broxton vendor-specific registers */114#define AZX_REG_VS_EM1 0x1000115#define AZX_REG_VS_INRC 0x1004116#define AZX_REG_VS_OUTRC 0x1008117#define AZX_REG_VS_FIFOTRK 0x100C118#define AZX_REG_VS_FIFOTRK2 0x1010119#define AZX_REG_VS_EM2 0x1030120#define AZX_REG_VS_EM3L 0x1038121#define AZX_REG_VS_EM3U 0x103C122#define AZX_REG_VS_EM4L 0x1040123#define AZX_REG_VS_EM4U 0x1044124#define AZX_REG_VS_LTRP 0x1048125#define AZX_REG_VS_D0I3C 0x104A126#define AZX_REG_VS_PCE 0x104B127#define AZX_REG_VS_L2MAGC 0x1050128#define AZX_REG_VS_L2LAHPT 0x1054129#define AZX_REG_VS_SDXDPIB_XBASE 0x1084130#define AZX_REG_VS_SDXDPIB_XINTERVAL 0x20131#define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094132#define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20133 134#define AZX_REG_VS_LTRP_GB_MASK GENMASK(6, 0)135 136/* PCI space */137#define AZX_PCIREG_TCSEL 0x44138 139/*140 * other constants141 */142 143/* max number of fragments - we may use more if allocating more pages for BDL */144#define BDL_SIZE 4096145#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)146#define AZX_MAX_FRAG 32147/*148 * max buffer size - artificial 4MB limit per stream to avoid big allocations149 * In theory it can be really big, but as it is per stream on systems with many streams memory could150 * be quickly saturated if userspace requests maximum buffer size for each of them.151 */152#define AZX_MAX_BUF_SIZE (4*1024*1024)153 154/* RIRB int mask: overrun[2], response[0] */155#define RIRB_INT_RESPONSE 0x01156#define RIRB_INT_OVERRUN 0x04157#define RIRB_INT_MASK 0x05158 159/* STATESTS int mask: S3,SD2,SD1,SD0 */160#define STATESTS_INT_MASK ((1 << HDA_MAX_CODECS) - 1)161 162/* SD_CTL bits */163#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */164#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */165#define SD_CTL_STRIPE (3 << 16) /* stripe control */166#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */167#define SD_CTL_DIR (1 << 19) /* bi-directional stream */168#define SD_CTL_STREAM_TAG_MASK (0xf << 20)169#define SD_CTL_STREAM_TAG_SHIFT 20170 171/* SD_CTL and SD_STS */172#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */173#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */174#define SD_INT_COMPLETE 0x04 /* completion interrupt */175#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\176 SD_INT_COMPLETE)177#define SD_CTL_STRIPE_MASK 0x3 /* stripe control mask */178 179/* SD_STS */180#define SD_STS_FIFO_READY 0x20 /* FIFO ready */181 182/* INTCTL and INTSTS */183#define AZX_INT_ALL_STREAM 0xff /* all stream interrupts */184#define AZX_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */185#define AZX_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */186 187/* below are so far hardcoded - should read registers in future */188#define AZX_MAX_CORB_ENTRIES 256189#define AZX_MAX_RIRB_ENTRIES 256190 191/* Capability header Structure */192#define AZX_REG_CAP_HDR 0x0193#define AZX_CAP_HDR_VER_OFF 28194#define AZX_CAP_HDR_VER_MASK (0xF << AZX_CAP_HDR_VER_OFF)195#define AZX_CAP_HDR_ID_OFF 16196#define AZX_CAP_HDR_ID_MASK (0xFFF << AZX_CAP_HDR_ID_OFF)197#define AZX_CAP_HDR_NXT_PTR_MASK 0xFFFF198 199/* registers of Software Position Based FIFO Capability Structure */200#define AZX_SPB_CAP_ID 0x4201#define AZX_REG_SPB_BASE_ADDR 0x700202#define AZX_REG_SPB_SPBFCH 0x00203#define AZX_REG_SPB_SPBFCCTL 0x04204/* Base used to calculate the iterating register offset */205#define AZX_SPB_BASE 0x08206/* Interval used to calculate the iterating register offset */207#define AZX_SPB_INTERVAL 0x08208/* SPIB base */209#define AZX_SPB_SPIB 0x00210/* SPIB MAXFIFO base*/211#define AZX_SPB_MAXFIFO 0x04212 213/* registers of Global Time Synchronization Capability Structure */214#define AZX_GTS_CAP_ID 0x1215#define AZX_REG_GTS_GTSCH 0x00216#define AZX_REG_GTS_GTSCD 0x04217#define AZX_REG_GTS_GTSCTLAC 0x0C218#define AZX_GTS_BASE 0x20219#define AZX_GTS_INTERVAL 0x20220 221/* registers for Processing Pipe Capability Structure */222#define AZX_PP_CAP_ID 0x3223#define AZX_REG_PP_PPCH 0x10224#define AZX_REG_PP_PPCTL 0x04225#define AZX_PPCTL_PIE (1<<31)226#define AZX_PPCTL_GPROCEN (1<<30)227/* _X_ = dma engine # and cannot * exceed 29 (per spec max 30 dma engines) */228#define AZX_PPCTL_PROCEN(_X_) (1<<(_X_))229 230#define AZX_REG_PP_PPSTS 0x08231 232#define AZX_PPHC_BASE 0x10233#define AZX_PPHC_INTERVAL 0x10234 235#define AZX_REG_PPHCLLPL 0x0236#define AZX_REG_PPHCLLPU 0x4237#define AZX_REG_PPHCLDPL 0x8238#define AZX_REG_PPHCLDPU 0xC239 240#define AZX_PPLC_BASE 0x10241#define AZX_PPLC_MULTI 0x10242#define AZX_PPLC_INTERVAL 0x10243 244#define AZX_REG_PPLCCTL 0x0245#define AZX_PPLCCTL_STRM_BITS 4246#define AZX_PPLCCTL_STRM_SHIFT 20247#define AZX_REG_MASK(bit_num, offset) \248 (((1 << (bit_num)) - 1) << (offset))249#define AZX_PPLCCTL_STRM_MASK \250 AZX_REG_MASK(AZX_PPLCCTL_STRM_BITS, AZX_PPLCCTL_STRM_SHIFT)251#define AZX_PPLCCTL_RUN (1<<1)252#define AZX_PPLCCTL_STRST (1<<0)253 254#define AZX_REG_PPLCFMT 0x4255#define AZX_REG_PPLCLLPL 0x8256#define AZX_REG_PPLCLLPU 0xC257 258/* registers for Multiple Links Capability Structure */259#define AZX_ML_CAP_ID 0x2260#define AZX_REG_ML_MLCH 0x00261#define AZX_REG_ML_MLCD 0x04262#define AZX_ML_BASE 0x40263#define AZX_ML_INTERVAL 0x40264 265/* HDaudio registers valid for HDaudio and HDaudio extended links */266#define AZX_REG_ML_LCAP 0x00267 268#define AZX_ML_HDA_LCAP_ALT BIT(28)269#define AZX_ML_HDA_LCAP_ALT_HDA 0x0270#define AZX_ML_HDA_LCAP_ALT_HDA_EXT 0x1271 272#define AZX_ML_HDA_LCAP_INTC BIT(27) /* only used if ALT == 1 */273#define AZX_ML_HDA_LCAP_OFLS BIT(26) /* only used if ALT == 1 */274#define AZX_ML_HDA_LCAP_LSS BIT(23) /* only used if ALT == 1 */275#define AZX_ML_HDA_LCAP_SLCOUNT GENMASK(22, 20) /* only used if ALT == 1 */276 277#define AZX_REG_ML_LCTL 0x04278#define AZX_ML_LCTL_INTSTS BIT(31) /* only used if ALT == 1 */279#define AZX_ML_LCTL_CPA BIT(23)280#define AZX_ML_LCTL_CPA_SHIFT 23281#define AZX_ML_LCTL_SPA BIT(16)282#define AZX_ML_LCTL_SPA_SHIFT 16283#define AZX_ML_LCTL_INTEN BIT(5) /* only used if ALT == 1 */284#define AZX_ML_LCTL_OFLEN BIT(4) /* only used if ALT == 1 */285#define AZX_ML_LCTL_SCF GENMASK(3, 0) /* only used if ALT == 0 */286 287#define AZX_REG_ML_LOSIDV 0x08288 289/* bit0 is reserved, with BIT(1) mapping to stream1 */290#define AZX_ML_LOSIDV_STREAM_MASK 0xFFFE291 292#define AZX_REG_ML_LSDIID 0x0C293#define AZX_REG_ML_LSDIID_OFFSET(x) (0x0C + (x) * 0x02) /* only used if ALT == 1 */294 295/* HDaudio registers only valid if LCAP.ALT == 0 */296#define AZX_REG_ML_LPSOO 0x10297#define AZX_REG_ML_LPSIO 0x12298#define AZX_REG_ML_LWALFC 0x18299#define AZX_REG_ML_LOUTPAY 0x20300#define AZX_REG_ML_LINPAY 0x30301 302/* HDaudio Extended link registers only valid if LCAP.ALT == 1 */303#define AZX_REG_ML_LSYNC 0x1C304 305#define AZX_REG_ML_LSYNC_CMDSYNC BIT(24)306#define AZX_REG_ML_LSYNC_CMDSYNC_SHIFT 24307#define AZX_REG_ML_LSYNC_SYNCGO BIT(23)308#define AZX_REG_ML_LSYNC_SYNCPU BIT(20)309#define AZX_REG_ML_LSYNC_SYNCPRD GENMASK(19, 0)310 311#define AZX_REG_ML_LEPTR 0x20312 313#define AZX_REG_ML_LEPTR_ID GENMASK(31, 24)314#define AZX_REG_ML_LEPTR_ID_SHIFT 24315#define AZX_REG_ML_LEPTR_ID_SDW 0x00316#define AZX_REG_ML_LEPTR_ID_INTEL_SSP 0xC0317#define AZX_REG_ML_LEPTR_ID_INTEL_DMIC 0xC1318#define AZX_REG_ML_LEPTR_ID_INTEL_UAOL 0xC2319#define AZX_REG_ML_LEPTR_VER GENMASK(23, 20)320#define AZX_REG_ML_LEPTR_PTR GENMASK(19, 0)321 322/* registers for DMA Resume Capability Structure */323#define AZX_DRSM_CAP_ID 0x5324#define AZX_REG_DRSM_CTL 0x4325/* Base used to calculate the iterating register offset */326#define AZX_DRSM_BASE 0x08327/* Interval used to calculate the iterating register offset */328#define AZX_DRSM_INTERVAL 0x08329 330/* Global time synchronization registers */331#define GTSCC_TSCCD_MASK 0x80000000332#define GTSCC_TSCCD_SHIFT BIT(31)333#define GTSCC_TSCCI_MASK 0x20334#define GTSCC_CDMAS_DMA_DIR_SHIFT 4335 336#define WALFCC_CIF_MASK 0x1FF337#define WALFCC_FN_SHIFT 9338#define HDA_CLK_CYCLES_PER_FRAME 512339 340/*341 * An error occurs near frame "rollover". The clocks in frame value indicates342 * whether this error may have occurred. Here we use the value of 10. Please343 * see the errata for the right number [<10]344 */345#define HDA_MAX_CYCLE_VALUE 499346#define HDA_MAX_CYCLE_OFFSET 10347#define HDA_MAX_CYCLE_READ_RETRY 10348 349#define TSCCU_CCU_SHIFT 32350#define LLPC_CCU_SHIFT 32351 352 353/*354 * helpers to read the stream position355 */356static inline unsigned int357snd_hdac_stream_get_pos_lpib(struct hdac_stream *stream)358{359 return snd_hdac_stream_readl(stream, SD_LPIB);360}361 362static inline unsigned int363snd_hdac_stream_get_pos_posbuf(struct hdac_stream *stream)364{365 return le32_to_cpu(*stream->posbuf);366}367 368#endif /* __SOUND_HDA_REGISTER_H */369