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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * HD-audio core stuff4 */5 6#ifndef __SOUND_HDAUDIO_H7#define __SOUND_HDAUDIO_H8 9#include <linux/device.h>10#include <linux/interrupt.h>11#include <linux/io.h>12#include <linux/io-64-nonatomic-lo-hi.h>13#include <linux/iopoll.h>14#include <linux/pci.h>15#include <linux/pm_runtime.h>16#include <linux/timecounter.h>17#include <sound/core.h>18#include <sound/pcm.h>19#include <sound/memalloc.h>20#include <sound/hda_verbs.h>21#include <drm/intel/i915_component.h>22 23/* codec node id */24typedef u16 hda_nid_t;25 26struct hdac_bus;27struct hdac_stream;28struct hdac_device;29struct hdac_driver;30struct hdac_widget_tree;31struct hda_device_id;32 33/*34 * exported bus type35 */36extern const struct bus_type snd_hda_bus_type;37 38/*39 * generic arrays40 */41struct snd_array {42 unsigned int used;43 unsigned int alloced;44 unsigned int elem_size;45 unsigned int alloc_align;46 void *list;47};48 49/*50 * HD-audio codec base device51 */52struct hdac_device {53 struct device dev;54 int type;55 struct hdac_bus *bus;56 unsigned int addr; /* codec address */57 struct list_head list; /* list point for bus codec_list */58 59 hda_nid_t afg; /* AFG node id */60 hda_nid_t mfg; /* MFG node id */61 62 /* ids */63 unsigned int vendor_id;64 unsigned int subsystem_id;65 unsigned int revision_id;66 unsigned int afg_function_id;67 unsigned int mfg_function_id;68 unsigned int afg_unsol:1;69 unsigned int mfg_unsol:1;70 71 unsigned int power_caps; /* FG power caps */72 73 const char *vendor_name; /* codec vendor name */74 const char *chip_name; /* codec chip name */75 76 /* verb exec op override */77 int (*exec_verb)(struct hdac_device *dev, unsigned int cmd,78 unsigned int flags, unsigned int *res);79 80 /* widgets */81 unsigned int num_nodes;82 hda_nid_t start_nid, end_nid;83 84 /* misc flags */85 atomic_t in_pm; /* suspend/resume being performed */86 87 /* sysfs */88 struct mutex widget_lock;89 struct hdac_widget_tree *widgets;90 91 /* regmap */92 struct regmap *regmap;93 struct mutex regmap_lock;94 struct snd_array vendor_verbs;95 bool lazy_cache:1; /* don't wake up for writes */96 bool caps_overwriting:1; /* caps overwrite being in process */97 bool cache_coef:1; /* cache COEF read/write too */98 unsigned int registered:1; /* codec was registered */99};100 101/* device/driver type used for matching */102enum {103 HDA_DEV_CORE,104 HDA_DEV_LEGACY,105 HDA_DEV_ASOC,106};107 108enum {109 SND_SKL_PCI_BIND_AUTO, /* automatic selection based on pci class */110 SND_SKL_PCI_BIND_LEGACY,/* bind only with legacy driver */111 SND_SKL_PCI_BIND_ASOC /* bind only with ASoC driver */112};113 114/* direction */115enum {116 HDA_INPUT, HDA_OUTPUT117};118 119#define dev_to_hdac_dev(_dev) container_of(_dev, struct hdac_device, dev)120 121int snd_hdac_device_init(struct hdac_device *dev, struct hdac_bus *bus,122 const char *name, unsigned int addr);123void snd_hdac_device_exit(struct hdac_device *dev);124int snd_hdac_device_register(struct hdac_device *codec);125void snd_hdac_device_unregister(struct hdac_device *codec);126int snd_hdac_device_set_chip_name(struct hdac_device *codec, const char *name);127int snd_hdac_codec_modalias(const struct hdac_device *hdac, char *buf, size_t size);128 129int snd_hdac_refresh_widgets(struct hdac_device *codec);130 131int snd_hdac_read(struct hdac_device *codec, hda_nid_t nid,132 unsigned int verb, unsigned int parm, unsigned int *res);133int _snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, int parm,134 unsigned int *res);135int snd_hdac_read_parm_uncached(struct hdac_device *codec, hda_nid_t nid,136 int parm);137int snd_hdac_override_parm(struct hdac_device *codec, hda_nid_t nid,138 unsigned int parm, unsigned int val);139int snd_hdac_get_connections(struct hdac_device *codec, hda_nid_t nid,140 hda_nid_t *conn_list, int max_conns);141int snd_hdac_get_sub_nodes(struct hdac_device *codec, hda_nid_t nid,142 hda_nid_t *start_id);143unsigned int snd_hdac_stream_format_bits(snd_pcm_format_t format, snd_pcm_subformat_t subformat,144 unsigned int maxbits);145unsigned int snd_hdac_stream_format(unsigned int channels, unsigned int bits, unsigned int rate);146unsigned int snd_hdac_spdif_stream_format(unsigned int channels, unsigned int bits,147 unsigned int rate, unsigned short spdif_ctls);148int snd_hdac_query_supported_pcm(struct hdac_device *codec, hda_nid_t nid,149 u32 *ratesp, u64 *formatsp, u32 *subformatsp,150 unsigned int *bpsp);151bool snd_hdac_is_supported_format(struct hdac_device *codec, hda_nid_t nid,152 unsigned int format);153 154int snd_hdac_codec_read(struct hdac_device *hdac, hda_nid_t nid,155 int flags, unsigned int verb, unsigned int parm);156int snd_hdac_codec_write(struct hdac_device *hdac, hda_nid_t nid,157 int flags, unsigned int verb, unsigned int parm);158bool snd_hdac_check_power_state(struct hdac_device *hdac,159 hda_nid_t nid, unsigned int target_state);160unsigned int snd_hdac_sync_power_state(struct hdac_device *hdac,161 hda_nid_t nid, unsigned int target_state);162/**163 * snd_hdac_read_parm - read a codec parameter164 * @codec: the codec object165 * @nid: NID to read a parameter166 * @parm: parameter to read167 *168 * Returns -1 for error. If you need to distinguish the error more169 * strictly, use _snd_hdac_read_parm() directly.170 */171static inline int snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid,172 int parm)173{174 unsigned int val;175 176 return _snd_hdac_read_parm(codec, nid, parm, &val) < 0 ? -1 : val;177}178 179#ifdef CONFIG_PM180int snd_hdac_power_up(struct hdac_device *codec);181int snd_hdac_power_down(struct hdac_device *codec);182int snd_hdac_power_up_pm(struct hdac_device *codec);183int snd_hdac_power_down_pm(struct hdac_device *codec);184int snd_hdac_keep_power_up(struct hdac_device *codec);185 186/* call this at entering into suspend/resume callbacks in codec driver */187static inline void snd_hdac_enter_pm(struct hdac_device *codec)188{189 atomic_inc(&codec->in_pm);190}191 192/* call this at leaving from suspend/resume callbacks in codec driver */193static inline void snd_hdac_leave_pm(struct hdac_device *codec)194{195 atomic_dec(&codec->in_pm);196}197 198static inline bool snd_hdac_is_in_pm(struct hdac_device *codec)199{200 return atomic_read(&codec->in_pm);201}202 203static inline bool snd_hdac_is_power_on(struct hdac_device *codec)204{205 return !pm_runtime_suspended(&codec->dev);206}207#else208static inline int snd_hdac_power_up(struct hdac_device *codec) { return 0; }209static inline int snd_hdac_power_down(struct hdac_device *codec) { return 0; }210static inline int snd_hdac_power_up_pm(struct hdac_device *codec) { return 0; }211static inline int snd_hdac_power_down_pm(struct hdac_device *codec) { return 0; }212static inline int snd_hdac_keep_power_up(struct hdac_device *codec) { return 0; }213static inline void snd_hdac_enter_pm(struct hdac_device *codec) {}214static inline void snd_hdac_leave_pm(struct hdac_device *codec) {}215static inline bool snd_hdac_is_in_pm(struct hdac_device *codec) { return false; }216static inline bool snd_hdac_is_power_on(struct hdac_device *codec) { return true; }217#endif218 219/*220 * HD-audio codec base driver221 */222struct hdac_driver {223 struct device_driver driver;224 int type;225 const struct hda_device_id *id_table;226 int (*match)(struct hdac_device *dev, struct hdac_driver *drv);227 void (*unsol_event)(struct hdac_device *dev, unsigned int event);228 229 /* fields used by ext bus APIs */230 int (*probe)(struct hdac_device *dev);231 int (*remove)(struct hdac_device *dev);232 void (*shutdown)(struct hdac_device *dev);233};234 235#define drv_to_hdac_driver(_drv) container_of(_drv, struct hdac_driver, driver)236 237const struct hda_device_id *238hdac_get_device_id(struct hdac_device *hdev, struct hdac_driver *drv);239 240/*241 * Bus verb operators242 */243struct hdac_bus_ops {244 /* send a single command */245 int (*command)(struct hdac_bus *bus, unsigned int cmd);246 /* get a response from the last command */247 int (*get_response)(struct hdac_bus *bus, unsigned int addr,248 unsigned int *res);249 /* notify of codec link power-up/down */250 void (*link_power)(struct hdac_device *hdev, bool enable);251};252 253/*254 * ops used for ASoC HDA codec drivers255 */256struct hdac_ext_bus_ops {257 int (*hdev_attach)(struct hdac_device *hdev);258 int (*hdev_detach)(struct hdac_device *hdev);259};260 261#define HDA_UNSOL_QUEUE_SIZE 64262#define HDA_MAX_CODECS 8 /* limit by controller side */263 264/*265 * CORB/RIRB266 *267 * Each CORB entry is 4byte, RIRB is 8byte268 */269struct hdac_rb {270 __le32 *buf; /* virtual address of CORB/RIRB buffer */271 dma_addr_t addr; /* physical address of CORB/RIRB buffer */272 unsigned short rp, wp; /* RIRB read/write pointers */273 int cmds[HDA_MAX_CODECS]; /* number of pending requests */274 u32 res[HDA_MAX_CODECS]; /* last read value */275};276 277/*278 * HD-audio bus base driver279 *280 * @ppcap: pp capabilities pointer281 * @spbcap: SPIB capabilities pointer282 * @mlcap: MultiLink capabilities pointer283 * @gtscap: gts capabilities pointer284 * @drsmcap: dma resume capabilities pointer285 * @num_streams: streams supported286 * @idx: HDA link index287 * @hlink_list: link list of HDA links288 * @lock: lock for link and display power mgmt289 * @cmd_dma_state: state of cmd DMAs: CORB and RIRB290 */291struct hdac_bus {292 struct device *dev;293 const struct hdac_bus_ops *ops;294 const struct hdac_ext_bus_ops *ext_ops;295 296 /* h/w resources */297 unsigned long addr;298 void __iomem *remap_addr;299 int irq;300 301 void __iomem *ppcap;302 void __iomem *spbcap;303 void __iomem *mlcap;304 void __iomem *gtscap;305 void __iomem *drsmcap;306 307 /* codec linked list */308 struct list_head codec_list;309 unsigned int num_codecs;310 311 /* link caddr -> codec */312 struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1];313 314 /* unsolicited event queue */315 u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */316 unsigned int unsol_rp, unsol_wp;317 struct work_struct unsol_work;318 319 /* bit flags of detected codecs */320 unsigned long codec_mask;321 322 /* bit flags of powered codecs */323 unsigned long codec_powered;324 325 /* CORB/RIRB */326 struct hdac_rb corb;327 struct hdac_rb rirb;328 unsigned int last_cmd[HDA_MAX_CODECS]; /* last sent command */329 wait_queue_head_t rirb_wq;330 331 /* CORB/RIRB and position buffers */332 struct snd_dma_buffer rb;333 struct snd_dma_buffer posbuf;334 int dma_type; /* SNDRV_DMA_TYPE_XXX for CORB/RIRB */335 336 /* hdac_stream linked list */337 struct list_head stream_list;338 339 /* operation state */340 bool chip_init:1; /* h/w initialized */341 342 /* behavior flags */343 bool aligned_mmio:1; /* aligned MMIO access */344 bool sync_write:1; /* sync after verb write */345 bool use_posbuf:1; /* use position buffer */346 bool snoop:1; /* enable snooping */347 bool align_bdle_4k:1; /* BDLE align 4K boundary */348 bool reverse_assign:1; /* assign devices in reverse order */349 bool corbrp_self_clear:1; /* CORBRP clears itself after reset */350 bool polling_mode:1;351 bool needs_damn_long_delay:1;352 bool not_use_interrupts:1; /* prohibiting the RIRB IRQ */353 bool access_sdnctl_in_dword:1; /* accessing the sdnctl register by dword */354 bool use_pio_for_commands:1; /* Use PIO instead of CORB for commands */355 356 int poll_count;357 358 int bdl_pos_adj; /* BDL position adjustment */359 360 /* delay time in us for dma stop */361 unsigned int dma_stop_delay;362 363 /* locks */364 spinlock_t reg_lock;365 struct mutex cmd_mutex;366 struct mutex lock;367 368 /* DRM component interface */369 struct drm_audio_component *audio_component;370 long display_power_status;371 unsigned long display_power_active;372 373 /* parameters required for enhanced capabilities */374 int num_streams;375 int idx;376 377 /* link management */378 struct list_head hlink_list;379 bool cmd_dma_state;380 381 /* factor used to derive STRIPE control value */382 unsigned int sdo_limit;383};384 385int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev,386 const struct hdac_bus_ops *ops);387void snd_hdac_bus_exit(struct hdac_bus *bus);388int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr,389 unsigned int cmd, unsigned int *res);390 391void snd_hdac_codec_link_up(struct hdac_device *codec);392void snd_hdac_codec_link_down(struct hdac_device *codec);393 394int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val);395int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,396 unsigned int *res);397int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus);398 399bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset);400void snd_hdac_bus_stop_chip(struct hdac_bus *bus);401void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus);402void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus);403void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus);404void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus);405int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset);406void snd_hdac_bus_link_power(struct hdac_device *hdev, bool enable);407 408void snd_hdac_bus_update_rirb(struct hdac_bus *bus);409int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,410 void (*ack)(struct hdac_bus *,411 struct hdac_stream *));412 413int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus);414void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus);415 416#ifdef CONFIG_SND_HDA_ALIGNED_MMIO417unsigned int snd_hdac_aligned_read(void __iomem *addr, unsigned int mask);418void snd_hdac_aligned_write(unsigned int val, void __iomem *addr,419 unsigned int mask);420#define snd_hdac_aligned_mmio(bus) (bus)->aligned_mmio421#else422#define snd_hdac_aligned_mmio(bus) false423#define snd_hdac_aligned_read(addr, mask) 0424#define snd_hdac_aligned_write(val, addr, mask) do {} while (0)425#endif426 427static inline void snd_hdac_reg_writeb(struct hdac_bus *bus, void __iomem *addr,428 u8 val)429{430 if (snd_hdac_aligned_mmio(bus))431 snd_hdac_aligned_write(val, addr, 0xff);432 else433 writeb(val, addr);434}435 436static inline void snd_hdac_reg_writew(struct hdac_bus *bus, void __iomem *addr,437 u16 val)438{439 if (snd_hdac_aligned_mmio(bus))440 snd_hdac_aligned_write(val, addr, 0xffff);441 else442 writew(val, addr);443}444 445static inline u8 snd_hdac_reg_readb(struct hdac_bus *bus, void __iomem *addr)446{447 return snd_hdac_aligned_mmio(bus) ?448 snd_hdac_aligned_read(addr, 0xff) : readb(addr);449}450 451static inline u16 snd_hdac_reg_readw(struct hdac_bus *bus, void __iomem *addr)452{453 return snd_hdac_aligned_mmio(bus) ?454 snd_hdac_aligned_read(addr, 0xffff) : readw(addr);455}456 457#define snd_hdac_reg_writel(bus, addr, val) writel(val, addr)458#define snd_hdac_reg_readl(bus, addr) readl(addr)459#define snd_hdac_reg_writeq(bus, addr, val) writeq(val, addr)460#define snd_hdac_reg_readq(bus, addr) readq(addr)461 462/*463 * macros for easy use464 */465#define _snd_hdac_chip_writeb(chip, reg, value) \466 snd_hdac_reg_writeb(chip, (chip)->remap_addr + (reg), value)467#define _snd_hdac_chip_readb(chip, reg) \468 snd_hdac_reg_readb(chip, (chip)->remap_addr + (reg))469#define _snd_hdac_chip_writew(chip, reg, value) \470 snd_hdac_reg_writew(chip, (chip)->remap_addr + (reg), value)471#define _snd_hdac_chip_readw(chip, reg) \472 snd_hdac_reg_readw(chip, (chip)->remap_addr + (reg))473#define _snd_hdac_chip_writel(chip, reg, value) \474 snd_hdac_reg_writel(chip, (chip)->remap_addr + (reg), value)475#define _snd_hdac_chip_readl(chip, reg) \476 snd_hdac_reg_readl(chip, (chip)->remap_addr + (reg))477 478/* read/write a register, pass without AZX_REG_ prefix */479#define snd_hdac_chip_writel(chip, reg, value) \480 _snd_hdac_chip_writel(chip, AZX_REG_ ## reg, value)481#define snd_hdac_chip_writew(chip, reg, value) \482 _snd_hdac_chip_writew(chip, AZX_REG_ ## reg, value)483#define snd_hdac_chip_writeb(chip, reg, value) \484 _snd_hdac_chip_writeb(chip, AZX_REG_ ## reg, value)485#define snd_hdac_chip_readl(chip, reg) \486 _snd_hdac_chip_readl(chip, AZX_REG_ ## reg)487#define snd_hdac_chip_readw(chip, reg) \488 _snd_hdac_chip_readw(chip, AZX_REG_ ## reg)489#define snd_hdac_chip_readb(chip, reg) \490 _snd_hdac_chip_readb(chip, AZX_REG_ ## reg)491 492/* update a register, pass without AZX_REG_ prefix */493#define snd_hdac_chip_updatel(chip, reg, mask, val) \494 snd_hdac_chip_writel(chip, reg, \495 (snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val))496#define snd_hdac_chip_updatew(chip, reg, mask, val) \497 snd_hdac_chip_writew(chip, reg, \498 (snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val))499#define snd_hdac_chip_updateb(chip, reg, mask, val) \500 snd_hdac_chip_writeb(chip, reg, \501 (snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val))502 503/* update register macro */504#define snd_hdac_updatel(addr, reg, mask, val) \505 writel(((readl(addr + reg) & ~(mask)) | (val)), addr + reg)506 507#define snd_hdac_updatew(addr, reg, mask, val) \508 writew(((readw(addr + reg) & ~(mask)) | (val)), addr + reg)509 510/*511 * HD-audio stream512 */513struct hdac_stream {514 struct hdac_bus *bus;515 struct snd_dma_buffer bdl; /* BDL buffer */516 __le32 *posbuf; /* position buffer pointer */517 int direction; /* playback / capture (SNDRV_PCM_STREAM_*) */518 519 unsigned int bufsize; /* size of the play buffer in bytes */520 unsigned int period_bytes; /* size of the period in bytes */521 unsigned int frags; /* number for period in the play buffer */522 unsigned int fifo_size; /* FIFO size */523 524 void __iomem *sd_addr; /* stream descriptor pointer */525 526 void __iomem *spib_addr; /* software position in buffers stream pointer */527 void __iomem *fifo_addr; /* software position Max fifos stream pointer */528 529 void __iomem *dpibr_addr; /* DMA position in buffer resume pointer */530 u32 dpib; /* DMA position in buffer */531 u32 lpib; /* Linear position in buffer */532 533 u32 sd_int_sta_mask; /* stream int status mask */534 535 /* pcm support */536 struct snd_pcm_substream *substream; /* assigned substream,537 * set in PCM open538 */539 struct snd_compr_stream *cstream;540 unsigned int format_val; /* format value to be set in the541 * controller and the codec542 */543 unsigned char stream_tag; /* assigned stream */544 unsigned char index; /* stream index */545 int assigned_key; /* last device# key assigned to */546 547 bool opened:1;548 bool running:1;549 bool prepared:1;550 bool no_period_wakeup:1;551 bool locked:1;552 bool stripe:1; /* apply stripe control */553 554 u64 curr_pos;555 /* timestamp */556 unsigned long start_wallclk; /* start + minimum wallclk */557 unsigned long period_wallclk; /* wallclk for period */558 struct timecounter tc;559 struct cyclecounter cc;560 int delay_negative_threshold;561 562 struct list_head list;563#ifdef CONFIG_SND_HDA_DSP_LOADER564 /* DSP access mutex */565 struct mutex dsp_mutex;566#endif567};568 569void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,570 int idx, int direction, int tag);571struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,572 struct snd_pcm_substream *substream);573void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev);574void snd_hdac_stream_release(struct hdac_stream *azx_dev);575struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,576 int dir, int stream_tag);577 578int snd_hdac_stream_setup(struct hdac_stream *azx_dev, bool code_loading);579void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev);580int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev);581int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,582 unsigned int format_val);583void snd_hdac_stream_start(struct hdac_stream *azx_dev);584void snd_hdac_stream_stop(struct hdac_stream *azx_dev);585void snd_hdac_stop_streams(struct hdac_bus *bus);586void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus);587void snd_hdac_stream_reset(struct hdac_stream *azx_dev);588void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,589 unsigned int streams, unsigned int reg);590void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,591 unsigned int streams);592void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,593 unsigned int streams, bool start);594int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,595 struct snd_pcm_substream *substream);596 597void snd_hdac_stream_spbcap_enable(struct hdac_bus *chip,598 bool enable, int index);599int snd_hdac_stream_set_spib(struct hdac_bus *bus,600 struct hdac_stream *azx_dev, u32 value);601int snd_hdac_stream_get_spbmaxfifo(struct hdac_bus *bus,602 struct hdac_stream *azx_dev);603void snd_hdac_stream_drsm_enable(struct hdac_bus *bus,604 bool enable, int index);605int snd_hdac_stream_wait_drsm(struct hdac_stream *azx_dev);606int snd_hdac_stream_set_dpibr(struct hdac_bus *bus,607 struct hdac_stream *azx_dev, u32 value);608int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value);609 610/*611 * macros for easy use612 */613/* read/write a register, pass without AZX_REG_ prefix */614#define snd_hdac_stream_writel(dev, reg, value) \615 snd_hdac_reg_writel((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value)616#define snd_hdac_stream_writew(dev, reg, value) \617 snd_hdac_reg_writew((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value)618#define snd_hdac_stream_writeb(dev, reg, value) \619 snd_hdac_reg_writeb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value)620#define snd_hdac_stream_readl(dev, reg) \621 snd_hdac_reg_readl((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)622#define snd_hdac_stream_readw(dev, reg) \623 snd_hdac_reg_readw((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)624#define snd_hdac_stream_readb(dev, reg) \625 snd_hdac_reg_readb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)626#define snd_hdac_stream_readb_poll(dev, reg, val, cond, delay_us, timeout_us) \627 read_poll_timeout_atomic(snd_hdac_reg_readb, val, cond, delay_us, timeout_us, \628 false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)629#define snd_hdac_stream_readw_poll(dev, reg, val, cond, delay_us, timeout_us) \630 read_poll_timeout_atomic(snd_hdac_reg_readw, val, cond, delay_us, timeout_us, \631 false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)632#define snd_hdac_stream_readl_poll(dev, reg, val, cond, delay_us, timeout_us) \633 read_poll_timeout_atomic(snd_hdac_reg_readl, val, cond, delay_us, timeout_us, \634 false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)635 636/* update a register, pass without AZX_REG_ prefix */637#define snd_hdac_stream_updatel(dev, reg, mask, val) \638 snd_hdac_stream_writel(dev, reg, \639 (snd_hdac_stream_readl(dev, reg) & \640 ~(mask)) | (val))641#define snd_hdac_stream_updatew(dev, reg, mask, val) \642 snd_hdac_stream_writew(dev, reg, \643 (snd_hdac_stream_readw(dev, reg) & \644 ~(mask)) | (val))645#define snd_hdac_stream_updateb(dev, reg, mask, val) \646 snd_hdac_stream_writeb(dev, reg, \647 (snd_hdac_stream_readb(dev, reg) & \648 ~(mask)) | (val))649 650#ifdef CONFIG_SND_HDA_DSP_LOADER651/* DSP lock helpers */652#define snd_hdac_dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)653#define snd_hdac_dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)654#define snd_hdac_dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)655#define snd_hdac_stream_is_locked(dev) ((dev)->locked)656/* DSP loader helpers */657int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,658 unsigned int byte_size, struct snd_dma_buffer *bufp);659void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start);660void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,661 struct snd_dma_buffer *dmab);662#else /* CONFIG_SND_HDA_DSP_LOADER */663#define snd_hdac_dsp_lock_init(dev) do {} while (0)664#define snd_hdac_dsp_lock(dev) do {} while (0)665#define snd_hdac_dsp_unlock(dev) do {} while (0)666#define snd_hdac_stream_is_locked(dev) 0667 668static inline int669snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,670 unsigned int byte_size, struct snd_dma_buffer *bufp)671{672 return 0;673}674 675static inline void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)676{677}678 679static inline void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,680 struct snd_dma_buffer *dmab)681{682}683#endif /* CONFIG_SND_HDA_DSP_LOADER */684 685 686/*687 * generic array helpers688 */689void *snd_array_new(struct snd_array *array);690void snd_array_free(struct snd_array *array);691static inline void snd_array_init(struct snd_array *array, unsigned int size,692 unsigned int align)693{694 array->elem_size = size;695 array->alloc_align = align;696}697 698static inline void *snd_array_elem(struct snd_array *array, unsigned int idx)699{700 return array->list + idx * array->elem_size;701}702 703static inline unsigned int snd_array_index(struct snd_array *array, void *ptr)704{705 return (unsigned long)(ptr - array->list) / array->elem_size;706}707 708/* a helper macro to iterate for each snd_array element */709#define snd_array_for_each(array, idx, ptr) \710 for ((idx) = 0, (ptr) = (array)->list; (idx) < (array)->used; \711 (ptr) = snd_array_elem(array, ++(idx)))712 713/*714 * Device matching715 */716 717#define HDA_CONTROLLER_IS_HSW(pci) (pci_match_id((struct pci_device_id []){ \718 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_0) }, \719 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_2) }, \720 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_3) }, \721 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_BDW) }, \722 { } \723 }, pci))724 725#define HDA_CONTROLLER_IS_APL(pci) (pci_match_id((struct pci_device_id []){ \726 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_APL) }, \727 { } \728 }, pci))729 730#define HDA_CONTROLLER_IN_GPU(pci) (pci_match_id((struct pci_device_id []){ \731 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG1) }, \732 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_0) }, \733 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_1) }, \734 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_2) }, \735 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_BMG) }, \736 { } \737 }, pci) || HDA_CONTROLLER_IS_HSW(pci))738 739#endif /* __SOUND_HDAUDIO_H */740