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1/*2 * Copyright (C) 2013 Red Hat3 * Author: Rob Clark <robdclark@gmail.com>4 *5 * Permission is hereby granted, free of charge, to any person obtaining a6 * copy of this software and associated documentation files (the "Software"),7 * to deal in the Software without restriction, including without limitation8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,9 * and/or sell copies of the Software, and to permit persons to whom the10 * Software is furnished to do so, subject to the following conditions:11 *12 * The above copyright notice and this permission notice (including the next13 * paragraph) shall be included in all copies or substantial portions of the14 * Software.15 *16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE22 * SOFTWARE.23 */24 25#ifndef __MSM_DRM_H__26#define __MSM_DRM_H__27 28#include "drm.h"29 30#if defined(__cplusplus)31extern "C" {32#endif33 34/* Please note that modifications to all structs defined here are35 * subject to backwards-compatibility constraints:36 * 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit37 * user/kernel compatibility38 * 2) Keep fields aligned to their size39 * 3) Because of how drm_ioctl() works, we can add new fields at40 * the end of an ioctl if some care is taken: drm_ioctl() will41 * zero out the new fields at the tail of the ioctl, so a zero42 * value should have a backwards compatible meaning. And for43 * output params, userspace won't see the newly added output44 * fields.. so that has to be somehow ok.45 */46 47#define MSM_PIPE_NONE 0x0048#define MSM_PIPE_2D0 0x0149#define MSM_PIPE_2D1 0x0250#define MSM_PIPE_3D0 0x1051 52/* The pipe-id just uses the lower bits, so can be OR'd with flags in53 * the upper 16 bits (which could be extended further, if needed, maybe54 * we extend/overload the pipe-id some day to deal with multiple rings,55 * but even then I don't think we need the full lower 16 bits).56 */57#define MSM_PIPE_ID_MASK 0xffff58#define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK)59#define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK)60 61/* timeouts are specified in clock-monotonic absolute times (to simplify62 * restarting interrupted ioctls). The following struct is logically the63 * same as 'struct timespec' but 32/64b ABI safe.64 */65struct drm_msm_timespec {66 __s64 tv_sec; /* seconds */67 __s64 tv_nsec; /* nanoseconds */68};69 70/* Below "RO" indicates a read-only param, "WO" indicates write-only, and71 * "RW" indicates a param that can be both read (GET_PARAM) and written72 * (SET_PARAM)73 */74#define MSM_PARAM_GPU_ID 0x01 /* RO */75#define MSM_PARAM_GMEM_SIZE 0x02 /* RO */76#define MSM_PARAM_CHIP_ID 0x03 /* RO */77#define MSM_PARAM_MAX_FREQ 0x04 /* RO */78#define MSM_PARAM_TIMESTAMP 0x05 /* RO */79#define MSM_PARAM_GMEM_BASE 0x06 /* RO */80#define MSM_PARAM_PRIORITIES 0x07 /* RO: The # of priority levels */81#define MSM_PARAM_PP_PGTABLE 0x08 /* RO: Deprecated, always returns zero */82#define MSM_PARAM_FAULTS 0x09 /* RO */83#define MSM_PARAM_SUSPENDS 0x0a /* RO */84#define MSM_PARAM_SYSPROF 0x0b /* WO: 1 preserves perfcntrs, 2 also disables suspend */85#define MSM_PARAM_COMM 0x0c /* WO: override for task->comm */86#define MSM_PARAM_CMDLINE 0x0d /* WO: override for task cmdline */87#define MSM_PARAM_VA_START 0x0e /* RO: start of valid GPU iova range */88#define MSM_PARAM_VA_SIZE 0x0f /* RO: size of valid GPU iova range (bytes) */89#define MSM_PARAM_HIGHEST_BANK_BIT 0x10 /* RO */90#define MSM_PARAM_RAYTRACING 0x11 /* RO */91#define MSM_PARAM_UBWC_SWIZZLE 0x12 /* RO */92#define MSM_PARAM_MACROTILE_MODE 0x13 /* RO */93 94/* For backwards compat. The original support for preemption was based on95 * a single ring per priority level so # of priority levels equals the #96 * of rings. With drm/scheduler providing additional levels of priority,97 * the number of priorities is greater than the # of rings. The param is98 * renamed to better reflect this.99 */100#define MSM_PARAM_NR_RINGS MSM_PARAM_PRIORITIES101 102struct drm_msm_param {103 __u32 pipe; /* in, MSM_PIPE_x */104 __u32 param; /* in, MSM_PARAM_x */105 __u64 value; /* out (get_param) or in (set_param) */106 __u32 len; /* zero for non-pointer params */107 __u32 pad; /* must be zero */108};109 110/*111 * GEM buffers:112 */113 114#define MSM_BO_SCANOUT 0x00000001 /* scanout capable */115#define MSM_BO_GPU_READONLY 0x00000002116#define MSM_BO_CACHE_MASK 0x000f0000117/* cache modes */118#define MSM_BO_CACHED 0x00010000119#define MSM_BO_WC 0x00020000120#define MSM_BO_UNCACHED 0x00040000 /* deprecated, use MSM_BO_WC */121#define MSM_BO_CACHED_COHERENT 0x080000122 123#define MSM_BO_FLAGS (MSM_BO_SCANOUT | \124 MSM_BO_GPU_READONLY | \125 MSM_BO_CACHE_MASK)126 127struct drm_msm_gem_new {128 __u64 size; /* in */129 __u32 flags; /* in, mask of MSM_BO_x */130 __u32 handle; /* out */131};132 133/* Get or set GEM buffer info. The requested value can be passed134 * directly in 'value', or for data larger than 64b 'value' is a135 * pointer to userspace buffer, with 'len' specifying the number of136 * bytes copied into that buffer. For info returned by pointer,137 * calling the GEM_INFO ioctl with null 'value' will return the138 * required buffer size in 'len'139 */140#define MSM_INFO_GET_OFFSET 0x00 /* get mmap() offset, returned by value */141#define MSM_INFO_GET_IOVA 0x01 /* get iova, returned by value */142#define MSM_INFO_SET_NAME 0x02 /* set the debug name (by pointer) */143#define MSM_INFO_GET_NAME 0x03 /* get debug name, returned by pointer */144#define MSM_INFO_SET_IOVA 0x04 /* set the iova, passed by value */145#define MSM_INFO_GET_FLAGS 0x05 /* get the MSM_BO_x flags */146#define MSM_INFO_SET_METADATA 0x06 /* set userspace metadata */147#define MSM_INFO_GET_METADATA 0x07 /* get userspace metadata */148 149struct drm_msm_gem_info {150 __u32 handle; /* in */151 __u32 info; /* in - one of MSM_INFO_* */152 __u64 value; /* in or out */153 __u32 len; /* in or out */154 __u32 pad;155};156 157#define MSM_PREP_READ 0x01158#define MSM_PREP_WRITE 0x02159#define MSM_PREP_NOSYNC 0x04160#define MSM_PREP_BOOST 0x08161 162#define MSM_PREP_FLAGS (MSM_PREP_READ | \163 MSM_PREP_WRITE | \164 MSM_PREP_NOSYNC | \165 MSM_PREP_BOOST | \166 0)167 168struct drm_msm_gem_cpu_prep {169 __u32 handle; /* in */170 __u32 op; /* in, mask of MSM_PREP_x */171 struct drm_msm_timespec timeout; /* in */172};173 174struct drm_msm_gem_cpu_fini {175 __u32 handle; /* in */176};177 178/*179 * Cmdstream Submission:180 */181 182/* The value written into the cmdstream is logically:183 *184 * ((relocbuf->gpuaddr + reloc_offset) << shift) | or185 *186 * When we have GPU's w/ >32bit ptrs, it should be possible to deal187 * with this by emit'ing two reloc entries with appropriate shift188 * values. Or a new MSM_SUBMIT_CMD_x type would also be an option.189 *190 * NOTE that reloc's must be sorted by order of increasing submit_offset,191 * otherwise EINVAL.192 */193struct drm_msm_gem_submit_reloc {194 __u32 submit_offset; /* in, offset from submit_bo */195#ifdef __cplusplus196 __u32 _or; /* in, value OR'd with result */197#else198 __u32 or; /* in, value OR'd with result */199#endif200 __s32 shift; /* in, amount of left shift (can be negative) */201 __u32 reloc_idx; /* in, index of reloc_bo buffer */202 __u64 reloc_offset; /* in, offset from start of reloc_bo */203};204 205/* submit-types:206 * BUF - this cmd buffer is executed normally.207 * IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are208 * processed normally, but the kernel does not setup an IB to209 * this buffer in the first-level ringbuffer210 * CTX_RESTORE_BUF - only executed if there has been a GPU context211 * switch since the last SUBMIT ioctl212 */213#define MSM_SUBMIT_CMD_BUF 0x0001214#define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002215#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003216struct drm_msm_gem_submit_cmd {217 __u32 type; /* in, one of MSM_SUBMIT_CMD_x */218 __u32 submit_idx; /* in, index of submit_bo cmdstream buffer */219 __u32 submit_offset; /* in, offset into submit_bo */220 __u32 size; /* in, cmdstream size */221 __u32 pad;222 __u32 nr_relocs; /* in, number of submit_reloc's */223 __u64 relocs; /* in, ptr to array of submit_reloc's */224};225 226/* Each buffer referenced elsewhere in the cmdstream submit (ie. the227 * cmdstream buffer(s) themselves or reloc entries) has one (and only228 * one) entry in the submit->bos[] table.229 *230 * As a optimization, the current buffer (gpu virtual address) can be231 * passed back through the 'presumed' field. If on a subsequent reloc,232 * userspace passes back a 'presumed' address that is still valid,233 * then patching the cmdstream for this entry is skipped. This can234 * avoid kernel needing to map/access the cmdstream bo in the common235 * case.236 */237#define MSM_SUBMIT_BO_READ 0x0001238#define MSM_SUBMIT_BO_WRITE 0x0002239#define MSM_SUBMIT_BO_DUMP 0x0004240#define MSM_SUBMIT_BO_NO_IMPLICIT 0x0008241 242#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | \243 MSM_SUBMIT_BO_WRITE | \244 MSM_SUBMIT_BO_DUMP | \245 MSM_SUBMIT_BO_NO_IMPLICIT)246 247struct drm_msm_gem_submit_bo {248 __u32 flags; /* in, mask of MSM_SUBMIT_BO_x */249 __u32 handle; /* in, GEM handle */250 __u64 presumed; /* in/out, presumed buffer address */251};252 253/* Valid submit ioctl flags: */254#define MSM_SUBMIT_NO_IMPLICIT 0x80000000 /* disable implicit sync */255#define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */256#define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */257#define MSM_SUBMIT_SUDO 0x10000000 /* run submitted cmds from RB */258#define MSM_SUBMIT_SYNCOBJ_IN 0x08000000 /* enable input syncobj */259#define MSM_SUBMIT_SYNCOBJ_OUT 0x04000000 /* enable output syncobj */260#define MSM_SUBMIT_FENCE_SN_IN 0x02000000 /* userspace passes in seqno fence */261#define MSM_SUBMIT_FLAGS ( \262 MSM_SUBMIT_NO_IMPLICIT | \263 MSM_SUBMIT_FENCE_FD_IN | \264 MSM_SUBMIT_FENCE_FD_OUT | \265 MSM_SUBMIT_SUDO | \266 MSM_SUBMIT_SYNCOBJ_IN | \267 MSM_SUBMIT_SYNCOBJ_OUT | \268 MSM_SUBMIT_FENCE_SN_IN | \269 0)270 271#define MSM_SUBMIT_SYNCOBJ_RESET 0x00000001 /* Reset syncobj after wait. */272#define MSM_SUBMIT_SYNCOBJ_FLAGS ( \273 MSM_SUBMIT_SYNCOBJ_RESET | \274 0)275 276struct drm_msm_gem_submit_syncobj {277 __u32 handle; /* in, syncobj handle. */278 __u32 flags; /* in, from MSM_SUBMIT_SYNCOBJ_FLAGS */279 __u64 point; /* in, timepoint for timeline syncobjs. */280};281 282/* Each cmdstream submit consists of a table of buffers involved, and283 * one or more cmdstream buffers. This allows for conditional execution284 * (context-restore), and IB buffers needed for per tile/bin draw cmds.285 */286struct drm_msm_gem_submit {287 __u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */288 __u32 fence; /* out (or in with MSM_SUBMIT_FENCE_SN_IN flag) */289 __u32 nr_bos; /* in, number of submit_bo's */290 __u32 nr_cmds; /* in, number of submit_cmd's */291 __u64 bos; /* in, ptr to array of submit_bo's */292 __u64 cmds; /* in, ptr to array of submit_cmd's */293 __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */294 __u32 queueid; /* in, submitqueue id */295 __u64 in_syncobjs; /* in, ptr to array of drm_msm_gem_submit_syncobj */296 __u64 out_syncobjs; /* in, ptr to array of drm_msm_gem_submit_syncobj */297 __u32 nr_in_syncobjs; /* in, number of entries in in_syncobj */298 __u32 nr_out_syncobjs; /* in, number of entries in out_syncobj. */299 __u32 syncobj_stride; /* in, stride of syncobj arrays. */300 __u32 pad; /*in, reserved for future use, always 0. */301 302};303 304#define MSM_WAIT_FENCE_BOOST 0x00000001305#define MSM_WAIT_FENCE_FLAGS ( \306 MSM_WAIT_FENCE_BOOST | \307 0)308 309/* The normal way to synchronize with the GPU is just to CPU_PREP on310 * a buffer if you need to access it from the CPU (other cmdstream311 * submission from same or other contexts, PAGE_FLIP ioctl, etc, all312 * handle the required synchronization under the hood). This ioctl313 * mainly just exists as a way to implement the gallium pipe_fence314 * APIs without requiring a dummy bo to synchronize on.315 */316struct drm_msm_wait_fence {317 __u32 fence; /* in */318 __u32 flags; /* in, bitmask of MSM_WAIT_FENCE_x */319 struct drm_msm_timespec timeout; /* in */320 __u32 queueid; /* in, submitqueue id */321};322 323/* madvise provides a way to tell the kernel in case a buffers contents324 * can be discarded under memory pressure, which is useful for userspace325 * bo cache where we want to optimistically hold on to buffer allocate326 * and potential mmap, but allow the pages to be discarded under memory327 * pressure.328 *329 * Typical usage would involve madvise(DONTNEED) when buffer enters BO330 * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache.331 * In the WILLNEED case, 'retained' indicates to userspace whether the332 * backing pages still exist.333 */334#define MSM_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */335#define MSM_MADV_DONTNEED 1 /* backing pages not needed */336#define __MSM_MADV_PURGED 2 /* internal state */337 338struct drm_msm_gem_madvise {339 __u32 handle; /* in, GEM handle */340 __u32 madv; /* in, MSM_MADV_x */341 __u32 retained; /* out, whether backing store still exists */342};343 344/*345 * Draw queues allow the user to set specific submission parameter. Command346 * submissions specify a specific submitqueue to use. ID 0 is reserved for347 * backwards compatibility as a "default" submitqueue348 */349 350#define MSM_SUBMITQUEUE_FLAGS (0)351 352/*353 * The submitqueue priority should be between 0 and MSM_PARAM_PRIORITIES-1,354 * a lower numeric value is higher priority.355 */356struct drm_msm_submitqueue {357 __u32 flags; /* in, MSM_SUBMITQUEUE_x */358 __u32 prio; /* in, Priority level */359 __u32 id; /* out, identifier */360};361 362#define MSM_SUBMITQUEUE_PARAM_FAULTS 0363 364struct drm_msm_submitqueue_query {365 __u64 data;366 __u32 id;367 __u32 param;368 __u32 len;369 __u32 pad;370};371 372#define DRM_MSM_GET_PARAM 0x00373#define DRM_MSM_SET_PARAM 0x01374#define DRM_MSM_GEM_NEW 0x02375#define DRM_MSM_GEM_INFO 0x03376#define DRM_MSM_GEM_CPU_PREP 0x04377#define DRM_MSM_GEM_CPU_FINI 0x05378#define DRM_MSM_GEM_SUBMIT 0x06379#define DRM_MSM_WAIT_FENCE 0x07380#define DRM_MSM_GEM_MADVISE 0x08381/* placeholder:382#define DRM_MSM_GEM_SVM_NEW 0x09383 */384#define DRM_MSM_SUBMITQUEUE_NEW 0x0A385#define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B386#define DRM_MSM_SUBMITQUEUE_QUERY 0x0C387 388#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)389#define DRM_IOCTL_MSM_SET_PARAM DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SET_PARAM, struct drm_msm_param)390#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)391#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)392#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)393#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)394#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)395#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)396#define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)397#define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue)398#define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32)399#define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query)400 401#if defined(__cplusplus)402}403#endif404 405#endif /* __MSM_DRM_H__ */406