242 lines · c
1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */2/* Do not edit directly, auto-generated from: */3/* Documentation/netlink/specs/dpll.yaml */4/* YNL-GEN uapi header */5 6#ifndef _UAPI_LINUX_DPLL_H7#define _UAPI_LINUX_DPLL_H8 9#define DPLL_FAMILY_NAME "dpll"10#define DPLL_FAMILY_VERSION 111 12/**13 * enum dpll_mode - working modes a dpll can support, differentiates if and how14 * dpll selects one of its inputs to syntonize with it, valid values for15 * DPLL_A_MODE attribute16 * @DPLL_MODE_MANUAL: input can be only selected by sending a request to dpll17 * @DPLL_MODE_AUTOMATIC: highest prio input pin auto selected by dpll18 */19enum dpll_mode {20 DPLL_MODE_MANUAL = 1,21 DPLL_MODE_AUTOMATIC,22 23 /* private: */24 __DPLL_MODE_MAX,25 DPLL_MODE_MAX = (__DPLL_MODE_MAX - 1)26};27 28/**29 * enum dpll_lock_status - provides information of dpll device lock status,30 * valid values for DPLL_A_LOCK_STATUS attribute31 * @DPLL_LOCK_STATUS_UNLOCKED: dpll was not yet locked to any valid input (or32 * forced by setting DPLL_A_MODE to DPLL_MODE_DETACHED)33 * @DPLL_LOCK_STATUS_LOCKED: dpll is locked to a valid signal, but no holdover34 * available35 * @DPLL_LOCK_STATUS_LOCKED_HO_ACQ: dpll is locked and holdover acquired36 * @DPLL_LOCK_STATUS_HOLDOVER: dpll is in holdover state - lost a valid lock or37 * was forced by disconnecting all the pins (latter possible only when dpll38 * lock-state was already DPLL_LOCK_STATUS_LOCKED_HO_ACQ, if dpll lock-state39 * was not DPLL_LOCK_STATUS_LOCKED_HO_ACQ, the dpll's lock-state shall remain40 * DPLL_LOCK_STATUS_UNLOCKED)41 */42enum dpll_lock_status {43 DPLL_LOCK_STATUS_UNLOCKED = 1,44 DPLL_LOCK_STATUS_LOCKED,45 DPLL_LOCK_STATUS_LOCKED_HO_ACQ,46 DPLL_LOCK_STATUS_HOLDOVER,47 48 /* private: */49 __DPLL_LOCK_STATUS_MAX,50 DPLL_LOCK_STATUS_MAX = (__DPLL_LOCK_STATUS_MAX - 1)51};52 53/**54 * enum dpll_lock_status_error - if previous status change was done due to a55 * failure, this provides information of dpll device lock status error. Valid56 * values for DPLL_A_LOCK_STATUS_ERROR attribute57 * @DPLL_LOCK_STATUS_ERROR_NONE: dpll device lock status was changed without58 * any error59 * @DPLL_LOCK_STATUS_ERROR_UNDEFINED: dpll device lock status was changed due60 * to undefined error. Driver fills this value up in case it is not able to61 * obtain suitable exact error type.62 * @DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN: dpll device lock status was changed63 * because of associated media got down. This may happen for example if dpll64 * device was previously locked on an input pin of type65 * PIN_TYPE_SYNCE_ETH_PORT.66 * @DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH: the FFO67 * (Fractional Frequency Offset) between the RX and TX symbol rate on the68 * media got too high. This may happen for example if dpll device was69 * previously locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.70 */71enum dpll_lock_status_error {72 DPLL_LOCK_STATUS_ERROR_NONE = 1,73 DPLL_LOCK_STATUS_ERROR_UNDEFINED,74 DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN,75 DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH,76 77 /* private: */78 __DPLL_LOCK_STATUS_ERROR_MAX,79 DPLL_LOCK_STATUS_ERROR_MAX = (__DPLL_LOCK_STATUS_ERROR_MAX - 1)80};81 82#define DPLL_TEMP_DIVIDER 100083 84/**85 * enum dpll_type - type of dpll, valid values for DPLL_A_TYPE attribute86 * @DPLL_TYPE_PPS: dpll produces Pulse-Per-Second signal87 * @DPLL_TYPE_EEC: dpll drives the Ethernet Equipment Clock88 */89enum dpll_type {90 DPLL_TYPE_PPS = 1,91 DPLL_TYPE_EEC,92 93 /* private: */94 __DPLL_TYPE_MAX,95 DPLL_TYPE_MAX = (__DPLL_TYPE_MAX - 1)96};97 98/**99 * enum dpll_pin_type - defines possible types of a pin, valid values for100 * DPLL_A_PIN_TYPE attribute101 * @DPLL_PIN_TYPE_MUX: aggregates another layer of selectable pins102 * @DPLL_PIN_TYPE_EXT: external input103 * @DPLL_PIN_TYPE_SYNCE_ETH_PORT: ethernet port PHY's recovered clock104 * @DPLL_PIN_TYPE_INT_OSCILLATOR: device internal oscillator105 * @DPLL_PIN_TYPE_GNSS: GNSS recovered clock106 */107enum dpll_pin_type {108 DPLL_PIN_TYPE_MUX = 1,109 DPLL_PIN_TYPE_EXT,110 DPLL_PIN_TYPE_SYNCE_ETH_PORT,111 DPLL_PIN_TYPE_INT_OSCILLATOR,112 DPLL_PIN_TYPE_GNSS,113 114 /* private: */115 __DPLL_PIN_TYPE_MAX,116 DPLL_PIN_TYPE_MAX = (__DPLL_PIN_TYPE_MAX - 1)117};118 119/**120 * enum dpll_pin_direction - defines possible direction of a pin, valid values121 * for DPLL_A_PIN_DIRECTION attribute122 * @DPLL_PIN_DIRECTION_INPUT: pin used as a input of a signal123 * @DPLL_PIN_DIRECTION_OUTPUT: pin used to output the signal124 */125enum dpll_pin_direction {126 DPLL_PIN_DIRECTION_INPUT = 1,127 DPLL_PIN_DIRECTION_OUTPUT,128 129 /* private: */130 __DPLL_PIN_DIRECTION_MAX,131 DPLL_PIN_DIRECTION_MAX = (__DPLL_PIN_DIRECTION_MAX - 1)132};133 134#define DPLL_PIN_FREQUENCY_1_HZ 1135#define DPLL_PIN_FREQUENCY_10_KHZ 10000136#define DPLL_PIN_FREQUENCY_77_5_KHZ 77500137#define DPLL_PIN_FREQUENCY_10_MHZ 10000000138 139/**140 * enum dpll_pin_state - defines possible states of a pin, valid values for141 * DPLL_A_PIN_STATE attribute142 * @DPLL_PIN_STATE_CONNECTED: pin connected, active input of phase locked loop143 * @DPLL_PIN_STATE_DISCONNECTED: pin disconnected, not considered as a valid144 * input145 * @DPLL_PIN_STATE_SELECTABLE: pin enabled for automatic input selection146 */147enum dpll_pin_state {148 DPLL_PIN_STATE_CONNECTED = 1,149 DPLL_PIN_STATE_DISCONNECTED,150 DPLL_PIN_STATE_SELECTABLE,151 152 /* private: */153 __DPLL_PIN_STATE_MAX,154 DPLL_PIN_STATE_MAX = (__DPLL_PIN_STATE_MAX - 1)155};156 157/**158 * enum dpll_pin_capabilities - defines possible capabilities of a pin, valid159 * flags on DPLL_A_PIN_CAPABILITIES attribute160 * @DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE: pin direction can be changed161 * @DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE: pin priority can be changed162 * @DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE: pin state can be changed163 */164enum dpll_pin_capabilities {165 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE = 1,166 DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE = 2,167 DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE = 4,168};169 170#define DPLL_PHASE_OFFSET_DIVIDER 1000171 172enum dpll_a {173 DPLL_A_ID = 1,174 DPLL_A_MODULE_NAME,175 DPLL_A_PAD,176 DPLL_A_CLOCK_ID,177 DPLL_A_MODE,178 DPLL_A_MODE_SUPPORTED,179 DPLL_A_LOCK_STATUS,180 DPLL_A_TEMP,181 DPLL_A_TYPE,182 DPLL_A_LOCK_STATUS_ERROR,183 184 __DPLL_A_MAX,185 DPLL_A_MAX = (__DPLL_A_MAX - 1)186};187 188enum dpll_a_pin {189 DPLL_A_PIN_ID = 1,190 DPLL_A_PIN_PARENT_ID,191 DPLL_A_PIN_MODULE_NAME,192 DPLL_A_PIN_PAD,193 DPLL_A_PIN_CLOCK_ID,194 DPLL_A_PIN_BOARD_LABEL,195 DPLL_A_PIN_PANEL_LABEL,196 DPLL_A_PIN_PACKAGE_LABEL,197 DPLL_A_PIN_TYPE,198 DPLL_A_PIN_DIRECTION,199 DPLL_A_PIN_FREQUENCY,200 DPLL_A_PIN_FREQUENCY_SUPPORTED,201 DPLL_A_PIN_FREQUENCY_MIN,202 DPLL_A_PIN_FREQUENCY_MAX,203 DPLL_A_PIN_PRIO,204 DPLL_A_PIN_STATE,205 DPLL_A_PIN_CAPABILITIES,206 DPLL_A_PIN_PARENT_DEVICE,207 DPLL_A_PIN_PARENT_PIN,208 DPLL_A_PIN_PHASE_ADJUST_MIN,209 DPLL_A_PIN_PHASE_ADJUST_MAX,210 DPLL_A_PIN_PHASE_ADJUST,211 DPLL_A_PIN_PHASE_OFFSET,212 DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET,213 DPLL_A_PIN_ESYNC_FREQUENCY,214 DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED,215 DPLL_A_PIN_ESYNC_PULSE,216 217 __DPLL_A_PIN_MAX,218 DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)219};220 221enum dpll_cmd {222 DPLL_CMD_DEVICE_ID_GET = 1,223 DPLL_CMD_DEVICE_GET,224 DPLL_CMD_DEVICE_SET,225 DPLL_CMD_DEVICE_CREATE_NTF,226 DPLL_CMD_DEVICE_DELETE_NTF,227 DPLL_CMD_DEVICE_CHANGE_NTF,228 DPLL_CMD_PIN_ID_GET,229 DPLL_CMD_PIN_GET,230 DPLL_CMD_PIN_SET,231 DPLL_CMD_PIN_CREATE_NTF,232 DPLL_CMD_PIN_DELETE_NTF,233 DPLL_CMD_PIN_CHANGE_NTF,234 235 __DPLL_CMD_MAX,236 DPLL_CMD_MAX = (__DPLL_CMD_MAX - 1)237};238 239#define DPLL_MCGRP_MONITOR "monitor"240 241#endif /* _UAPI_LINUX_DPLL_H */242