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1/* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */2/*3 * SyncLink Multiprotocol Serial Adapter Driver4 *5 * $Id: synclink.h,v 3.14 2006/07/17 20:15:43 paulkf Exp $6 *7 * Copyright (C) 1998-2000 by Microgate Corporation8 *9 * Redistribution of this file is permitted under10 * the terms of the GNU Public License (GPL)11 */12 13#ifndef _UAPI_SYNCLINK_H_14#define _UAPI_SYNCLINK_H_15#define SYNCLINK_H_VERSION 3.616 17#include <linux/types.h>18 19#define BIT0 0x000120#define BIT1 0x000221#define BIT2 0x000422#define BIT3 0x000823#define BIT4 0x001024#define BIT5 0x002025#define BIT6 0x004026#define BIT7 0x008027#define BIT8 0x010028#define BIT9 0x020029#define BIT10 0x040030#define BIT11 0x080031#define BIT12 0x100032#define BIT13 0x200033#define BIT14 0x400034#define BIT15 0x800035#define BIT16 0x0001000036#define BIT17 0x0002000037#define BIT18 0x0004000038#define BIT19 0x0008000039#define BIT20 0x0010000040#define BIT21 0x0020000041#define BIT22 0x0040000042#define BIT23 0x0080000043#define BIT24 0x0100000044#define BIT25 0x0200000045#define BIT26 0x0400000046#define BIT27 0x0800000047#define BIT28 0x1000000048#define BIT29 0x2000000049#define BIT30 0x4000000050#define BIT31 0x8000000051 52 53#define HDLC_MAX_FRAME_SIZE 6553554#define MAX_ASYNC_TRANSMIT 409655#define MAX_ASYNC_BUFFER_SIZE 409656 57#define ASYNC_PARITY_NONE 058#define ASYNC_PARITY_EVEN 159#define ASYNC_PARITY_ODD 260#define ASYNC_PARITY_SPACE 361 62#define HDLC_FLAG_UNDERRUN_ABORT7 0x000063#define HDLC_FLAG_UNDERRUN_ABORT15 0x000164#define HDLC_FLAG_UNDERRUN_FLAG 0x000265#define HDLC_FLAG_UNDERRUN_CRC 0x000466#define HDLC_FLAG_SHARE_ZERO 0x001067#define HDLC_FLAG_AUTO_CTS 0x002068#define HDLC_FLAG_AUTO_DCD 0x004069#define HDLC_FLAG_AUTO_RTS 0x008070#define HDLC_FLAG_RXC_DPLL 0x010071#define HDLC_FLAG_RXC_BRG 0x020072#define HDLC_FLAG_RXC_TXCPIN 0x800073#define HDLC_FLAG_RXC_RXCPIN 0x000074#define HDLC_FLAG_TXC_DPLL 0x040075#define HDLC_FLAG_TXC_BRG 0x080076#define HDLC_FLAG_TXC_TXCPIN 0x000077#define HDLC_FLAG_TXC_RXCPIN 0x000878#define HDLC_FLAG_DPLL_DIV8 0x100079#define HDLC_FLAG_DPLL_DIV16 0x200080#define HDLC_FLAG_DPLL_DIV32 0x000081#define HDLC_FLAG_HDLC_LOOPMODE 0x400082 83#define HDLC_CRC_NONE 084#define HDLC_CRC_16_CCITT 185#define HDLC_CRC_32_CCITT 286#define HDLC_CRC_MASK 0x00ff87#define HDLC_CRC_RETURN_EX 0x800088 89#define RX_OK 090#define RX_CRC_ERROR 191 92#define HDLC_TXIDLE_FLAGS 093#define HDLC_TXIDLE_ALT_ZEROS_ONES 194#define HDLC_TXIDLE_ZEROS 295#define HDLC_TXIDLE_ONES 396#define HDLC_TXIDLE_ALT_MARK_SPACE 497#define HDLC_TXIDLE_SPACE 598#define HDLC_TXIDLE_MARK 699#define HDLC_TXIDLE_CUSTOM_8 0x10000000100#define HDLC_TXIDLE_CUSTOM_16 0x20000000101 102#define HDLC_ENCODING_NRZ 0103#define HDLC_ENCODING_NRZB 1104#define HDLC_ENCODING_NRZI_MARK 2105#define HDLC_ENCODING_NRZI_SPACE 3106#define HDLC_ENCODING_NRZI HDLC_ENCODING_NRZI_SPACE107#define HDLC_ENCODING_BIPHASE_MARK 4108#define HDLC_ENCODING_BIPHASE_SPACE 5109#define HDLC_ENCODING_BIPHASE_LEVEL 6110#define HDLC_ENCODING_DIFF_BIPHASE_LEVEL 7111 112#define HDLC_PREAMBLE_LENGTH_8BITS 0113#define HDLC_PREAMBLE_LENGTH_16BITS 1114#define HDLC_PREAMBLE_LENGTH_32BITS 2115#define HDLC_PREAMBLE_LENGTH_64BITS 3116 117#define HDLC_PREAMBLE_PATTERN_NONE 0118#define HDLC_PREAMBLE_PATTERN_ZEROS 1119#define HDLC_PREAMBLE_PATTERN_FLAGS 2120#define HDLC_PREAMBLE_PATTERN_10 3121#define HDLC_PREAMBLE_PATTERN_01 4122#define HDLC_PREAMBLE_PATTERN_ONES 5123 124#define MGSL_MODE_ASYNC 1125#define MGSL_MODE_HDLC 2126#define MGSL_MODE_MONOSYNC 3127#define MGSL_MODE_BISYNC 4128#define MGSL_MODE_RAW 6129#define MGSL_MODE_BASE_CLOCK 7130#define MGSL_MODE_XSYNC 8131 132#define MGSL_BUS_TYPE_ISA 1133#define MGSL_BUS_TYPE_EISA 2134#define MGSL_BUS_TYPE_PCI 5135 136#define MGSL_INTERFACE_MASK 0xf137#define MGSL_INTERFACE_DISABLE 0138#define MGSL_INTERFACE_RS232 1139#define MGSL_INTERFACE_V35 2140#define MGSL_INTERFACE_RS422 3141#define MGSL_INTERFACE_RTS_EN 0x10142#define MGSL_INTERFACE_LL 0x20143#define MGSL_INTERFACE_RL 0x40144#define MGSL_INTERFACE_MSB_FIRST 0x80145 146typedef struct _MGSL_PARAMS147{148 /* Common */149 150 unsigned long mode; /* Asynchronous or HDLC */151 unsigned char loopback; /* internal loopback mode */152 153 /* HDLC Only */154 155 unsigned short flags;156 unsigned char encoding; /* NRZ, NRZI, etc. */157 unsigned long clock_speed; /* external clock speed in bits per second */158 unsigned char addr_filter; /* receive HDLC address filter, 0xFF = disable */159 unsigned short crc_type; /* None, CRC16-CCITT, or CRC32-CCITT */160 unsigned char preamble_length;161 unsigned char preamble;162 163 /* Async Only */164 165 unsigned long data_rate; /* bits per second */166 unsigned char data_bits; /* 7 or 8 data bits */167 unsigned char stop_bits; /* 1 or 2 stop bits */168 unsigned char parity; /* none, even, or odd */169 170} MGSL_PARAMS, *PMGSL_PARAMS;171 172#define MICROGATE_VENDOR_ID 0x13c0173#define SYNCLINK_DEVICE_ID 0x0010174#define MGSCC_DEVICE_ID 0x0020175#define SYNCLINK_SCA_DEVICE_ID 0x0030176#define SYNCLINK_GT_DEVICE_ID 0x0070177#define SYNCLINK_GT4_DEVICE_ID 0x0080178#define SYNCLINK_AC_DEVICE_ID 0x0090179#define SYNCLINK_GT2_DEVICE_ID 0x00A0180#define MGSL_MAX_SERIAL_NUMBER 30181 182/*183** device diagnostics status184*/185 186#define DiagStatus_OK 0187#define DiagStatus_AddressFailure 1188#define DiagStatus_AddressConflict 2189#define DiagStatus_IrqFailure 3190#define DiagStatus_IrqConflict 4191#define DiagStatus_DmaFailure 5192#define DiagStatus_DmaConflict 6193#define DiagStatus_PciAdapterNotFound 7194#define DiagStatus_CantAssignPciResources 8195#define DiagStatus_CantAssignPciMemAddr 9196#define DiagStatus_CantAssignPciIoAddr 10197#define DiagStatus_CantAssignPciIrq 11198#define DiagStatus_MemoryError 12199 200#define SerialSignal_DCD 0x01 /* Data Carrier Detect */201#define SerialSignal_TXD 0x02 /* Transmit Data */202#define SerialSignal_RI 0x04 /* Ring Indicator */203#define SerialSignal_RXD 0x08 /* Receive Data */204#define SerialSignal_CTS 0x10 /* Clear to Send */205#define SerialSignal_RTS 0x20 /* Request to Send */206#define SerialSignal_DSR 0x40 /* Data Set Ready */207#define SerialSignal_DTR 0x80 /* Data Terminal Ready */208 209 210/*211 * Counters of the input lines (CTS, DSR, RI, CD) interrupts212 */213struct mgsl_icount {214 __u32 cts, dsr, rng, dcd, tx, rx;215 __u32 frame, parity, overrun, brk;216 __u32 buf_overrun;217 __u32 txok;218 __u32 txunder;219 __u32 txabort;220 __u32 txtimeout;221 __u32 rxshort;222 __u32 rxlong;223 __u32 rxabort;224 __u32 rxover;225 __u32 rxcrc;226 __u32 rxok;227 __u32 exithunt;228 __u32 rxidle;229};230 231struct gpio_desc {232 __u32 state;233 __u32 smask;234 __u32 dir;235 __u32 dmask;236};237 238#define DEBUG_LEVEL_DATA 1239#define DEBUG_LEVEL_ERROR 2240#define DEBUG_LEVEL_INFO 3241#define DEBUG_LEVEL_BH 4242#define DEBUG_LEVEL_ISR 5243 244/*245** Event bit flags for use with MgslWaitEvent246*/247 248#define MgslEvent_DsrActive 0x0001249#define MgslEvent_DsrInactive 0x0002250#define MgslEvent_Dsr 0x0003251#define MgslEvent_CtsActive 0x0004252#define MgslEvent_CtsInactive 0x0008253#define MgslEvent_Cts 0x000c254#define MgslEvent_DcdActive 0x0010255#define MgslEvent_DcdInactive 0x0020256#define MgslEvent_Dcd 0x0030257#define MgslEvent_RiActive 0x0040258#define MgslEvent_RiInactive 0x0080259#define MgslEvent_Ri 0x00c0260#define MgslEvent_ExitHuntMode 0x0100261#define MgslEvent_IdleReceived 0x0200262 263/* Private IOCTL codes:264 *265 * MGSL_IOCSPARAMS set MGSL_PARAMS structure values266 * MGSL_IOCGPARAMS get current MGSL_PARAMS structure values267 * MGSL_IOCSTXIDLE set current transmit idle mode268 * MGSL_IOCGTXIDLE get current transmit idle mode269 * MGSL_IOCTXENABLE enable or disable transmitter270 * MGSL_IOCRXENABLE enable or disable receiver271 * MGSL_IOCTXABORT abort transmitting frame (HDLC)272 * MGSL_IOCGSTATS return current statistics273 * MGSL_IOCWAITEVENT wait for specified event to occur274 * MGSL_LOOPTXDONE transmit in HDLC LoopMode done275 * MGSL_IOCSIF set the serial interface type276 * MGSL_IOCGIF get the serial interface type277 */278#define MGSL_MAGIC_IOC 'm'279#define MGSL_IOCSPARAMS _IOW(MGSL_MAGIC_IOC,0,struct _MGSL_PARAMS)280#define MGSL_IOCGPARAMS _IOR(MGSL_MAGIC_IOC,1,struct _MGSL_PARAMS)281#define MGSL_IOCSTXIDLE _IO(MGSL_MAGIC_IOC,2)282#define MGSL_IOCGTXIDLE _IO(MGSL_MAGIC_IOC,3)283#define MGSL_IOCTXENABLE _IO(MGSL_MAGIC_IOC,4)284#define MGSL_IOCRXENABLE _IO(MGSL_MAGIC_IOC,5)285#define MGSL_IOCTXABORT _IO(MGSL_MAGIC_IOC,6)286#define MGSL_IOCGSTATS _IO(MGSL_MAGIC_IOC,7)287#define MGSL_IOCWAITEVENT _IOWR(MGSL_MAGIC_IOC,8,int)288#define MGSL_IOCCLRMODCOUNT _IO(MGSL_MAGIC_IOC,15)289#define MGSL_IOCLOOPTXDONE _IO(MGSL_MAGIC_IOC,9)290#define MGSL_IOCSIF _IO(MGSL_MAGIC_IOC,10)291#define MGSL_IOCGIF _IO(MGSL_MAGIC_IOC,11)292#define MGSL_IOCSGPIO _IOW(MGSL_MAGIC_IOC,16,struct gpio_desc)293#define MGSL_IOCGGPIO _IOR(MGSL_MAGIC_IOC,17,struct gpio_desc)294#define MGSL_IOCWAITGPIO _IOWR(MGSL_MAGIC_IOC,18,struct gpio_desc)295#define MGSL_IOCSXSYNC _IO(MGSL_MAGIC_IOC, 19)296#define MGSL_IOCGXSYNC _IO(MGSL_MAGIC_IOC, 20)297#define MGSL_IOCSXCTRL _IO(MGSL_MAGIC_IOC, 21)298#define MGSL_IOCGXCTRL _IO(MGSL_MAGIC_IOC, 22)299 300 301#endif /* _UAPI_SYNCLINK_H_ */302