971 lines · c
1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */2/*3 * V4L2 DV timings header.4 *5 * Copyright (C) 2012-2016 Hans Verkuil <hans.verkuil@cisco.com>6 */7 8#ifndef _V4L2_DV_TIMINGS_H9#define _V4L2_DV_TIMINGS_H10 11#if __GNUC__ < 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ < 6))12/* Sadly gcc versions older than 4.6 have a bug in how they initialize13 anonymous unions where they require additional curly brackets.14 This violates the C1x standard. This workaround adds the curly brackets15 if needed. */16#define V4L2_INIT_BT_TIMINGS(_width, args...) \17 { .bt = { _width , ## args } }18#else19#define V4L2_INIT_BT_TIMINGS(_width, args...) \20 .bt = { _width , ## args }21#endif22 23/* CEA-861-F timings (i.e. standard HDTV timings) */24 25#define V4L2_DV_BT_CEA_640X480P59_94 { \26 .type = V4L2_DV_BT_656_1120, \27 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \28 25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, \29 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \30 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 1) \31}32 33/* Note: these are the nominal timings, for HDMI links this format is typically34 * double-clocked to meet the minimum pixelclock requirements. */35#define V4L2_DV_BT_CEA_720X480I59_94 { \36 .type = V4L2_DV_BT_656_1120, \37 V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \38 13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \39 V4L2_DV_BT_STD_CEA861, \40 V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \41 V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \42 { 4, 3 }, 6) \43}44 45#define V4L2_DV_BT_CEA_720X480P59_94 { \46 .type = V4L2_DV_BT_656_1120, \47 V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \48 27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \49 V4L2_DV_BT_STD_CEA861, \50 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \51 V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 2) \52}53 54/* Note: these are the nominal timings, for HDMI links this format is typically55 * double-clocked to meet the minimum pixelclock requirements. */56#define V4L2_DV_BT_CEA_720X576I50 { \57 .type = V4L2_DV_BT_656_1120, \58 V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \59 13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \60 V4L2_DV_BT_STD_CEA861, \61 V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \62 V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \63 { 4, 3 }, 21) \64}65 66#define V4L2_DV_BT_CEA_720X576P50 { \67 .type = V4L2_DV_BT_656_1120, \68 V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \69 27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \70 V4L2_DV_BT_STD_CEA861, \71 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \72 V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 17) \73}74 75#define V4L2_DV_BT_CEA_1280X720P24 { \76 .type = V4L2_DV_BT_656_1120, \77 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \78 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \79 59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \80 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \81 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 60) \82}83 84#define V4L2_DV_BT_CEA_1280X720P25 { \85 .type = V4L2_DV_BT_656_1120, \86 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \87 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \88 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \89 V4L2_DV_BT_STD_CEA861, \90 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 61) \91}92 93#define V4L2_DV_BT_CEA_1280X720P30 { \94 .type = V4L2_DV_BT_656_1120, \95 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \96 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \97 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \98 V4L2_DV_BT_STD_CEA861, \99 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \100 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 62) \101}102 103#define V4L2_DV_BT_CEA_1280X720P50 { \104 .type = V4L2_DV_BT_656_1120, \105 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \106 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \107 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \108 V4L2_DV_BT_STD_CEA861, \109 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 19) \110}111 112#define V4L2_DV_BT_CEA_1280X720P60 { \113 .type = V4L2_DV_BT_656_1120, \114 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \115 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \116 74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \117 V4L2_DV_BT_STD_CEA861, \118 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \119 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 4) \120}121 122#define V4L2_DV_BT_CEA_1920X1080P24 { \123 .type = V4L2_DV_BT_656_1120, \124 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \125 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \126 74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \127 V4L2_DV_BT_STD_CEA861, \128 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \129 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 32) \130}131 132#define V4L2_DV_BT_CEA_1920X1080P25 { \133 .type = V4L2_DV_BT_656_1120, \134 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \135 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \136 74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \137 V4L2_DV_BT_STD_CEA861, \138 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 33) \139}140 141#define V4L2_DV_BT_CEA_1920X1080P30 { \142 .type = V4L2_DV_BT_656_1120, \143 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \144 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \145 74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \146 V4L2_DV_BT_STD_CEA861, \147 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \148 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 34) \149}150 151#define V4L2_DV_BT_CEA_1920X1080I50 { \152 .type = V4L2_DV_BT_656_1120, \153 V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \154 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \155 74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \156 V4L2_DV_BT_STD_CEA861, \157 V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \158 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 20) \159}160 161#define V4L2_DV_BT_CEA_1920X1080P50 { \162 .type = V4L2_DV_BT_656_1120, \163 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \164 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \165 148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \166 V4L2_DV_BT_STD_CEA861, \167 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 31) \168}169 170#define V4L2_DV_BT_CEA_1920X1080I60 { \171 .type = V4L2_DV_BT_656_1120, \172 V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \173 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \174 74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \175 V4L2_DV_BT_STD_CEA861, \176 V4L2_DV_FL_CAN_REDUCE_FPS | \177 V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \178 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 5) \179}180 181#define V4L2_DV_BT_CEA_1920X1080P60 { \182 .type = V4L2_DV_BT_656_1120, \183 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \184 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \185 148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \186 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \187 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \188 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 16) \189}190 191#define V4L2_DV_BT_CEA_3840X2160P24 { \192 .type = V4L2_DV_BT_656_1120, \193 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \194 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \195 297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \196 V4L2_DV_BT_STD_CEA861, \197 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \198 V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \199 { 0, 0 }, 93, 3) \200}201 202#define V4L2_DV_BT_CEA_3840X2160P25 { \203 .type = V4L2_DV_BT_656_1120, \204 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \205 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \206 297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \207 V4L2_DV_BT_STD_CEA861, \208 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC | \209 V4L2_DV_FL_HAS_HDMI_VIC, { 0, 0 }, 94, 2) \210}211 212#define V4L2_DV_BT_CEA_3840X2160P30 { \213 .type = V4L2_DV_BT_656_1120, \214 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \215 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \216 297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \217 V4L2_DV_BT_STD_CEA861, \218 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \219 V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \220 { 0, 0 }, 95, 1) \221}222 223#define V4L2_DV_BT_CEA_3840X2160P50 { \224 .type = V4L2_DV_BT_656_1120, \225 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \226 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \227 594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \228 V4L2_DV_BT_STD_CEA861, \229 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 96) \230}231 232#define V4L2_DV_BT_CEA_3840X2160P60 { \233 .type = V4L2_DV_BT_656_1120, \234 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \235 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \236 594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \237 V4L2_DV_BT_STD_CEA861, \238 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \239 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 97) \240}241 242#define V4L2_DV_BT_CEA_4096X2160P24 { \243 .type = V4L2_DV_BT_656_1120, \244 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \245 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \246 297000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \247 V4L2_DV_BT_STD_CEA861, \248 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \249 V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \250 { 0, 0 }, 98, 4) \251}252 253#define V4L2_DV_BT_CEA_4096X2160P25 { \254 .type = V4L2_DV_BT_656_1120, \255 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \256 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \257 297000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \258 V4L2_DV_BT_STD_CEA861, \259 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 99) \260}261 262#define V4L2_DV_BT_CEA_4096X2160P30 { \263 .type = V4L2_DV_BT_656_1120, \264 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \265 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \266 297000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \267 V4L2_DV_BT_STD_CEA861, \268 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \269 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 100) \270}271 272#define V4L2_DV_BT_CEA_4096X2160P50 { \273 .type = V4L2_DV_BT_656_1120, \274 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \275 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \276 594000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \277 V4L2_DV_BT_STD_CEA861, \278 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 101) \279}280 281#define V4L2_DV_BT_CEA_4096X2160P60 { \282 .type = V4L2_DV_BT_656_1120, \283 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \284 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \285 594000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \286 V4L2_DV_BT_STD_CEA861, \287 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \288 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 102) \289}290 291 292/* VESA Discrete Monitor Timings as per version 1.0, revision 12 */293 294#define V4L2_DV_BT_DMT_640X350P85 { \295 .type = V4L2_DV_BT_656_1120, \296 V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \297 31500000, 32, 64, 96, 32, 3, 60, 0, 0, 0, \298 V4L2_DV_BT_STD_DMT, 0) \299}300 301#define V4L2_DV_BT_DMT_640X400P85 { \302 .type = V4L2_DV_BT_656_1120, \303 V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \304 31500000, 32, 64, 96, 1, 3, 41, 0, 0, 0, \305 V4L2_DV_BT_STD_DMT, 0) \306}307 308#define V4L2_DV_BT_DMT_720X400P85 { \309 .type = V4L2_DV_BT_656_1120, \310 V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \311 35500000, 36, 72, 108, 1, 3, 42, 0, 0, 0, \312 V4L2_DV_BT_STD_DMT, 0) \313}314 315/* VGA resolutions */316#define V4L2_DV_BT_DMT_640X480P60 V4L2_DV_BT_CEA_640X480P59_94317 318#define V4L2_DV_BT_DMT_640X480P72 { \319 .type = V4L2_DV_BT_656_1120, \320 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \321 31500000, 24, 40, 128, 9, 3, 28, 0, 0, 0, \322 V4L2_DV_BT_STD_DMT, 0) \323}324 325#define V4L2_DV_BT_DMT_640X480P75 { \326 .type = V4L2_DV_BT_656_1120, \327 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \328 31500000, 16, 64, 120, 1, 3, 16, 0, 0, 0, \329 V4L2_DV_BT_STD_DMT, 0) \330}331 332#define V4L2_DV_BT_DMT_640X480P85 { \333 .type = V4L2_DV_BT_656_1120, \334 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \335 36000000, 56, 56, 80, 1, 3, 25, 0, 0, 0, \336 V4L2_DV_BT_STD_DMT, 0) \337}338 339/* SVGA resolutions */340#define V4L2_DV_BT_DMT_800X600P56 { \341 .type = V4L2_DV_BT_656_1120, \342 V4L2_INIT_BT_TIMINGS(800, 600, 0, \343 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \344 36000000, 24, 72, 128, 1, 2, 22, 0, 0, 0, \345 V4L2_DV_BT_STD_DMT, 0) \346}347 348#define V4L2_DV_BT_DMT_800X600P60 { \349 .type = V4L2_DV_BT_656_1120, \350 V4L2_INIT_BT_TIMINGS(800, 600, 0, \351 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \352 40000000, 40, 128, 88, 1, 4, 23, 0, 0, 0, \353 V4L2_DV_BT_STD_DMT, 0) \354}355 356#define V4L2_DV_BT_DMT_800X600P72 { \357 .type = V4L2_DV_BT_656_1120, \358 V4L2_INIT_BT_TIMINGS(800, 600, 0, \359 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \360 50000000, 56, 120, 64, 37, 6, 23, 0, 0, 0, \361 V4L2_DV_BT_STD_DMT, 0) \362}363 364#define V4L2_DV_BT_DMT_800X600P75 { \365 .type = V4L2_DV_BT_656_1120, \366 V4L2_INIT_BT_TIMINGS(800, 600, 0, \367 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \368 49500000, 16, 80, 160, 1, 3, 21, 0, 0, 0, \369 V4L2_DV_BT_STD_DMT, 0) \370}371 372#define V4L2_DV_BT_DMT_800X600P85 { \373 .type = V4L2_DV_BT_656_1120, \374 V4L2_INIT_BT_TIMINGS(800, 600, 0, \375 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \376 56250000, 32, 64, 152, 1, 3, 27, 0, 0, 0, \377 V4L2_DV_BT_STD_DMT, 0) \378}379 380#define V4L2_DV_BT_DMT_800X600P120_RB { \381 .type = V4L2_DV_BT_656_1120, \382 V4L2_INIT_BT_TIMINGS(800, 600, 0, V4L2_DV_HSYNC_POS_POL, \383 73250000, 48, 32, 80, 3, 4, 29, 0, 0, 0, \384 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \385 V4L2_DV_FL_REDUCED_BLANKING) \386}387 388#define V4L2_DV_BT_DMT_848X480P60 { \389 .type = V4L2_DV_BT_656_1120, \390 V4L2_INIT_BT_TIMINGS(848, 480, 0, \391 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \392 33750000, 16, 112, 112, 6, 8, 23, 0, 0, 0, \393 V4L2_DV_BT_STD_DMT, 0) \394}395 396#define V4L2_DV_BT_DMT_1024X768I43 { \397 .type = V4L2_DV_BT_656_1120, \398 V4L2_INIT_BT_TIMINGS(1024, 768, 1, \399 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \400 44900000, 8, 176, 56, 0, 4, 20, 0, 4, 21, \401 V4L2_DV_BT_STD_DMT, 0) \402}403 404/* XGA resolutions */405#define V4L2_DV_BT_DMT_1024X768P60 { \406 .type = V4L2_DV_BT_656_1120, \407 V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \408 65000000, 24, 136, 160, 3, 6, 29, 0, 0, 0, \409 V4L2_DV_BT_STD_DMT, 0) \410}411 412#define V4L2_DV_BT_DMT_1024X768P70 { \413 .type = V4L2_DV_BT_656_1120, \414 V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \415 75000000, 24, 136, 144, 3, 6, 29, 0, 0, 0, \416 V4L2_DV_BT_STD_DMT, 0) \417}418 419#define V4L2_DV_BT_DMT_1024X768P75 { \420 .type = V4L2_DV_BT_656_1120, \421 V4L2_INIT_BT_TIMINGS(1024, 768, 0, \422 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \423 78750000, 16, 96, 176, 1, 3, 28, 0, 0, 0, \424 V4L2_DV_BT_STD_DMT, 0) \425}426 427#define V4L2_DV_BT_DMT_1024X768P85 { \428 .type = V4L2_DV_BT_656_1120, \429 V4L2_INIT_BT_TIMINGS(1024, 768, 0, \430 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \431 94500000, 48, 96, 208, 1, 3, 36, 0, 0, 0, \432 V4L2_DV_BT_STD_DMT, 0) \433}434 435#define V4L2_DV_BT_DMT_1024X768P120_RB { \436 .type = V4L2_DV_BT_656_1120, \437 V4L2_INIT_BT_TIMINGS(1024, 768, 0, V4L2_DV_HSYNC_POS_POL, \438 115500000, 48, 32, 80, 3, 4, 38, 0, 0, 0, \439 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \440 V4L2_DV_FL_REDUCED_BLANKING) \441}442 443/* XGA+ resolution */444#define V4L2_DV_BT_DMT_1152X864P75 { \445 .type = V4L2_DV_BT_656_1120, \446 V4L2_INIT_BT_TIMINGS(1152, 864, 0, \447 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \448 108000000, 64, 128, 256, 1, 3, 32, 0, 0, 0, \449 V4L2_DV_BT_STD_DMT, 0) \450}451 452#define V4L2_DV_BT_DMT_1280X720P60 V4L2_DV_BT_CEA_1280X720P60453 454/* WXGA resolutions */455#define V4L2_DV_BT_DMT_1280X768P60_RB { \456 .type = V4L2_DV_BT_656_1120, \457 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \458 68250000, 48, 32, 80, 3, 7, 12, 0, 0, 0, \459 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \460 V4L2_DV_FL_REDUCED_BLANKING) \461}462 463#define V4L2_DV_BT_DMT_1280X768P60 { \464 .type = V4L2_DV_BT_656_1120, \465 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \466 79500000, 64, 128, 192, 3, 7, 20, 0, 0, 0, \467 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \468}469 470#define V4L2_DV_BT_DMT_1280X768P75 { \471 .type = V4L2_DV_BT_656_1120, \472 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \473 102250000, 80, 128, 208, 3, 7, 27, 0, 0, 0, \474 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \475}476 477#define V4L2_DV_BT_DMT_1280X768P85 { \478 .type = V4L2_DV_BT_656_1120, \479 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \480 117500000, 80, 136, 216, 3, 7, 31, 0, 0, 0, \481 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \482}483 484#define V4L2_DV_BT_DMT_1280X768P120_RB { \485 .type = V4L2_DV_BT_656_1120, \486 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \487 140250000, 48, 32, 80, 3, 7, 35, 0, 0, 0, \488 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \489 V4L2_DV_FL_REDUCED_BLANKING) \490}491 492#define V4L2_DV_BT_DMT_1280X800P60_RB { \493 .type = V4L2_DV_BT_656_1120, \494 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \495 71000000, 48, 32, 80, 3, 6, 14, 0, 0, 0, \496 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \497 V4L2_DV_FL_REDUCED_BLANKING) \498}499 500#define V4L2_DV_BT_DMT_1280X800P60 { \501 .type = V4L2_DV_BT_656_1120, \502 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \503 83500000, 72, 128, 200, 3, 6, 22, 0, 0, 0, \504 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \505}506 507#define V4L2_DV_BT_DMT_1280X800P75 { \508 .type = V4L2_DV_BT_656_1120, \509 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \510 106500000, 80, 128, 208, 3, 6, 29, 0, 0, 0, \511 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \512}513 514#define V4L2_DV_BT_DMT_1280X800P85 { \515 .type = V4L2_DV_BT_656_1120, \516 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \517 122500000, 80, 136, 216, 3, 6, 34, 0, 0, 0, \518 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \519}520 521#define V4L2_DV_BT_DMT_1280X800P120_RB { \522 .type = V4L2_DV_BT_656_1120, \523 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \524 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, \525 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \526 V4L2_DV_FL_REDUCED_BLANKING) \527}528 529#define V4L2_DV_BT_DMT_1280X960P60 { \530 .type = V4L2_DV_BT_656_1120, \531 V4L2_INIT_BT_TIMINGS(1280, 960, 0, \532 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \533 108000000, 96, 112, 312, 1, 3, 36, 0, 0, 0, \534 V4L2_DV_BT_STD_DMT, 0) \535}536 537#define V4L2_DV_BT_DMT_1280X960P85 { \538 .type = V4L2_DV_BT_656_1120, \539 V4L2_INIT_BT_TIMINGS(1280, 960, 0, \540 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \541 148500000, 64, 160, 224, 1, 3, 47, 0, 0, 0, \542 V4L2_DV_BT_STD_DMT, 0) \543}544 545#define V4L2_DV_BT_DMT_1280X960P120_RB { \546 .type = V4L2_DV_BT_656_1120, \547 V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \548 175500000, 48, 32, 80, 3, 4, 50, 0, 0, 0, \549 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \550 V4L2_DV_FL_REDUCED_BLANKING) \551}552 553/* SXGA resolutions */554#define V4L2_DV_BT_DMT_1280X1024P60 { \555 .type = V4L2_DV_BT_656_1120, \556 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \557 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \558 108000000, 48, 112, 248, 1, 3, 38, 0, 0, 0, \559 V4L2_DV_BT_STD_DMT, 0) \560}561 562#define V4L2_DV_BT_DMT_1280X1024P75 { \563 .type = V4L2_DV_BT_656_1120, \564 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \565 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \566 135000000, 16, 144, 248, 1, 3, 38, 0, 0, 0, \567 V4L2_DV_BT_STD_DMT, 0) \568}569 570#define V4L2_DV_BT_DMT_1280X1024P85 { \571 .type = V4L2_DV_BT_656_1120, \572 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \573 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \574 157500000, 64, 160, 224, 1, 3, 44, 0, 0, 0, \575 V4L2_DV_BT_STD_DMT, 0) \576}577 578#define V4L2_DV_BT_DMT_1280X1024P120_RB { \579 .type = V4L2_DV_BT_656_1120, \580 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \581 187250000, 48, 32, 80, 3, 7, 50, 0, 0, 0, \582 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \583 V4L2_DV_FL_REDUCED_BLANKING) \584}585 586#define V4L2_DV_BT_DMT_1360X768P60 { \587 .type = V4L2_DV_BT_656_1120, \588 V4L2_INIT_BT_TIMINGS(1360, 768, 0, \589 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \590 85500000, 64, 112, 256, 3, 6, 18, 0, 0, 0, \591 V4L2_DV_BT_STD_DMT, 0) \592}593 594#define V4L2_DV_BT_DMT_1360X768P120_RB { \595 .type = V4L2_DV_BT_656_1120, \596 V4L2_INIT_BT_TIMINGS(1360, 768, 0, V4L2_DV_HSYNC_POS_POL, \597 148250000, 48, 32, 80, 3, 5, 37, 0, 0, 0, \598 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \599 V4L2_DV_FL_REDUCED_BLANKING) \600}601 602#define V4L2_DV_BT_DMT_1366X768P60 { \603 .type = V4L2_DV_BT_656_1120, \604 V4L2_INIT_BT_TIMINGS(1366, 768, 0, \605 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \606 85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \607 V4L2_DV_BT_STD_DMT, 0) \608}609 610#define V4L2_DV_BT_DMT_1366X768P60_RB { \611 .type = V4L2_DV_BT_656_1120, \612 V4L2_INIT_BT_TIMINGS(1366, 768, 0, \613 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \614 72000000, 14, 56, 64, 1, 3, 28, 0, 0, 0, \615 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \616}617 618/* SXGA+ resolutions */619#define V4L2_DV_BT_DMT_1400X1050P60_RB { \620 .type = V4L2_DV_BT_656_1120, \621 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \622 101000000, 48, 32, 80, 3, 4, 23, 0, 0, 0, \623 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \624 V4L2_DV_FL_REDUCED_BLANKING) \625}626 627#define V4L2_DV_BT_DMT_1400X1050P60 { \628 .type = V4L2_DV_BT_656_1120, \629 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \630 121750000, 88, 144, 232, 3, 4, 32, 0, 0, 0, \631 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \632}633 634#define V4L2_DV_BT_DMT_1400X1050P75 { \635 .type = V4L2_DV_BT_656_1120, \636 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \637 156000000, 104, 144, 248, 3, 4, 42, 0, 0, 0, \638 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \639}640 641#define V4L2_DV_BT_DMT_1400X1050P85 { \642 .type = V4L2_DV_BT_656_1120, \643 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \644 179500000, 104, 152, 256, 3, 4, 48, 0, 0, 0, \645 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \646}647 648#define V4L2_DV_BT_DMT_1400X1050P120_RB { \649 .type = V4L2_DV_BT_656_1120, \650 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \651 208000000, 48, 32, 80, 3, 4, 55, 0, 0, 0, \652 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \653 V4L2_DV_FL_REDUCED_BLANKING) \654}655 656/* WXGA+ resolutions */657#define V4L2_DV_BT_DMT_1440X900P60_RB { \658 .type = V4L2_DV_BT_656_1120, \659 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \660 88750000, 48, 32, 80, 3, 6, 17, 0, 0, 0, \661 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \662 V4L2_DV_FL_REDUCED_BLANKING) \663}664 665#define V4L2_DV_BT_DMT_1440X900P60 { \666 .type = V4L2_DV_BT_656_1120, \667 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \668 106500000, 80, 152, 232, 3, 6, 25, 0, 0, 0, \669 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \670}671 672#define V4L2_DV_BT_DMT_1440X900P75 { \673 .type = V4L2_DV_BT_656_1120, \674 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \675 136750000, 96, 152, 248, 3, 6, 33, 0, 0, 0, \676 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \677}678 679#define V4L2_DV_BT_DMT_1440X900P85 { \680 .type = V4L2_DV_BT_656_1120, \681 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \682 157000000, 104, 152, 256, 3, 6, 39, 0, 0, 0, \683 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \684}685 686#define V4L2_DV_BT_DMT_1440X900P120_RB { \687 .type = V4L2_DV_BT_656_1120, \688 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \689 182750000, 48, 32, 80, 3, 6, 44, 0, 0, 0, \690 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \691 V4L2_DV_FL_REDUCED_BLANKING) \692}693 694#define V4L2_DV_BT_DMT_1600X900P60_RB { \695 .type = V4L2_DV_BT_656_1120, \696 V4L2_INIT_BT_TIMINGS(1600, 900, 0, \697 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \698 108000000, 24, 80, 96, 1, 3, 96, 0, 0, 0, \699 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \700}701 702/* UXGA resolutions */703#define V4L2_DV_BT_DMT_1600X1200P60 { \704 .type = V4L2_DV_BT_656_1120, \705 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \706 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \707 162000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \708 V4L2_DV_BT_STD_DMT, 0) \709}710 711#define V4L2_DV_BT_DMT_1600X1200P65 { \712 .type = V4L2_DV_BT_656_1120, \713 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \714 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \715 175500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \716 V4L2_DV_BT_STD_DMT, 0) \717}718 719#define V4L2_DV_BT_DMT_1600X1200P70 { \720 .type = V4L2_DV_BT_656_1120, \721 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \722 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \723 189000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \724 V4L2_DV_BT_STD_DMT, 0) \725}726 727#define V4L2_DV_BT_DMT_1600X1200P75 { \728 .type = V4L2_DV_BT_656_1120, \729 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \730 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \731 202500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \732 V4L2_DV_BT_STD_DMT, 0) \733}734 735#define V4L2_DV_BT_DMT_1600X1200P85 { \736 .type = V4L2_DV_BT_656_1120, \737 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \738 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \739 229500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \740 V4L2_DV_BT_STD_DMT, 0) \741}742 743#define V4L2_DV_BT_DMT_1600X1200P120_RB { \744 .type = V4L2_DV_BT_656_1120, \745 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \746 268250000, 48, 32, 80, 3, 4, 64, 0, 0, 0, \747 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \748 V4L2_DV_FL_REDUCED_BLANKING) \749}750 751/* WSXGA+ resolutions */752#define V4L2_DV_BT_DMT_1680X1050P60_RB { \753 .type = V4L2_DV_BT_656_1120, \754 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \755 119000000, 48, 32, 80, 3, 6, 21, 0, 0, 0, \756 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \757 V4L2_DV_FL_REDUCED_BLANKING) \758}759 760#define V4L2_DV_BT_DMT_1680X1050P60 { \761 .type = V4L2_DV_BT_656_1120, \762 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \763 146250000, 104, 176, 280, 3, 6, 30, 0, 0, 0, \764 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \765}766 767#define V4L2_DV_BT_DMT_1680X1050P75 { \768 .type = V4L2_DV_BT_656_1120, \769 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \770 187000000, 120, 176, 296, 3, 6, 40, 0, 0, 0, \771 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \772}773 774#define V4L2_DV_BT_DMT_1680X1050P85 { \775 .type = V4L2_DV_BT_656_1120, \776 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \777 214750000, 128, 176, 304, 3, 6, 46, 0, 0, 0, \778 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \779}780 781#define V4L2_DV_BT_DMT_1680X1050P120_RB { \782 .type = V4L2_DV_BT_656_1120, \783 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \784 245500000, 48, 32, 80, 3, 6, 53, 0, 0, 0, \785 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \786 V4L2_DV_FL_REDUCED_BLANKING) \787}788 789#define V4L2_DV_BT_DMT_1792X1344P60 { \790 .type = V4L2_DV_BT_656_1120, \791 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \792 204750000, 128, 200, 328, 1, 3, 46, 0, 0, 0, \793 V4L2_DV_BT_STD_DMT, 0) \794}795 796#define V4L2_DV_BT_DMT_1792X1344P75 { \797 .type = V4L2_DV_BT_656_1120, \798 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \799 261000000, 96, 216, 352, 1, 3, 69, 0, 0, 0, \800 V4L2_DV_BT_STD_DMT, 0) \801}802 803#define V4L2_DV_BT_DMT_1792X1344P120_RB { \804 .type = V4L2_DV_BT_656_1120, \805 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_HSYNC_POS_POL, \806 333250000, 48, 32, 80, 3, 4, 72, 0, 0, 0, \807 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \808 V4L2_DV_FL_REDUCED_BLANKING) \809}810 811#define V4L2_DV_BT_DMT_1856X1392P60 { \812 .type = V4L2_DV_BT_656_1120, \813 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \814 218250000, 96, 224, 352, 1, 3, 43, 0, 0, 0, \815 V4L2_DV_BT_STD_DMT, 0) \816}817 818#define V4L2_DV_BT_DMT_1856X1392P75 { \819 .type = V4L2_DV_BT_656_1120, \820 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \821 288000000, 128, 224, 352, 1, 3, 104, 0, 0, 0, \822 V4L2_DV_BT_STD_DMT, 0) \823}824 825#define V4L2_DV_BT_DMT_1856X1392P120_RB { \826 .type = V4L2_DV_BT_656_1120, \827 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_HSYNC_POS_POL, \828 356500000, 48, 32, 80, 3, 4, 75, 0, 0, 0, \829 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \830 V4L2_DV_FL_REDUCED_BLANKING) \831}832 833#define V4L2_DV_BT_DMT_1920X1080P60 V4L2_DV_BT_CEA_1920X1080P60834 835/* WUXGA resolutions */836#define V4L2_DV_BT_DMT_1920X1200P60_RB { \837 .type = V4L2_DV_BT_656_1120, \838 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \839 154000000, 48, 32, 80, 3, 6, 26, 0, 0, 0, \840 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \841 V4L2_DV_FL_REDUCED_BLANKING) \842}843 844#define V4L2_DV_BT_DMT_1920X1200P60 { \845 .type = V4L2_DV_BT_656_1120, \846 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \847 193250000, 136, 200, 336, 3, 6, 36, 0, 0, 0, \848 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \849}850 851#define V4L2_DV_BT_DMT_1920X1200P75 { \852 .type = V4L2_DV_BT_656_1120, \853 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \854 245250000, 136, 208, 344, 3, 6, 46, 0, 0, 0, \855 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \856}857 858#define V4L2_DV_BT_DMT_1920X1200P85 { \859 .type = V4L2_DV_BT_656_1120, \860 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \861 281250000, 144, 208, 352, 3, 6, 53, 0, 0, 0, \862 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \863}864 865#define V4L2_DV_BT_DMT_1920X1200P120_RB { \866 .type = V4L2_DV_BT_656_1120, \867 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \868 317000000, 48, 32, 80, 3, 6, 62, 0, 0, 0, \869 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \870 V4L2_DV_FL_REDUCED_BLANKING) \871}872 873#define V4L2_DV_BT_DMT_1920X1440P60 { \874 .type = V4L2_DV_BT_656_1120, \875 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \876 234000000, 128, 208, 344, 1, 3, 56, 0, 0, 0, \877 V4L2_DV_BT_STD_DMT, 0) \878}879 880#define V4L2_DV_BT_DMT_1920X1440P75 { \881 .type = V4L2_DV_BT_656_1120, \882 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \883 297000000, 144, 224, 352, 1, 3, 56, 0, 0, 0, \884 V4L2_DV_BT_STD_DMT, 0) \885}886 887#define V4L2_DV_BT_DMT_1920X1440P120_RB { \888 .type = V4L2_DV_BT_656_1120, \889 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_HSYNC_POS_POL, \890 380500000, 48, 32, 80, 3, 4, 78, 0, 0, 0, \891 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \892 V4L2_DV_FL_REDUCED_BLANKING) \893}894 895#define V4L2_DV_BT_DMT_2048X1152P60_RB { \896 .type = V4L2_DV_BT_656_1120, \897 V4L2_INIT_BT_TIMINGS(2048, 1152, 0, \898 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \899 162000000, 26, 80, 96, 1, 3, 44, 0, 0, 0, \900 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \901}902 903/* WQXGA resolutions */904#define V4L2_DV_BT_DMT_2560X1600P60_RB { \905 .type = V4L2_DV_BT_656_1120, \906 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \907 268500000, 48, 32, 80, 3, 6, 37, 0, 0, 0, \908 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \909 V4L2_DV_FL_REDUCED_BLANKING) \910}911 912#define V4L2_DV_BT_DMT_2560X1600P60 { \913 .type = V4L2_DV_BT_656_1120, \914 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \915 348500000, 192, 280, 472, 3, 6, 49, 0, 0, 0, \916 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \917}918 919#define V4L2_DV_BT_DMT_2560X1600P75 { \920 .type = V4L2_DV_BT_656_1120, \921 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \922 443250000, 208, 280, 488, 3, 6, 63, 0, 0, 0, \923 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \924}925 926#define V4L2_DV_BT_DMT_2560X1600P85 { \927 .type = V4L2_DV_BT_656_1120, \928 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \929 505250000, 208, 280, 488, 3, 6, 73, 0, 0, 0, \930 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \931}932 933#define V4L2_DV_BT_DMT_2560X1600P120_RB { \934 .type = V4L2_DV_BT_656_1120, \935 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \936 552750000, 48, 32, 80, 3, 6, 85, 0, 0, 0, \937 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \938 V4L2_DV_FL_REDUCED_BLANKING) \939}940 941/* 4K resolutions */942#define V4L2_DV_BT_DMT_4096X2160P60_RB { \943 .type = V4L2_DV_BT_656_1120, \944 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \945 556744000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \946 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \947 V4L2_DV_FL_REDUCED_BLANKING) \948}949 950#define V4L2_DV_BT_DMT_4096X2160P59_94_RB { \951 .type = V4L2_DV_BT_656_1120, \952 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \953 556188000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \954 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \955 V4L2_DV_FL_REDUCED_BLANKING) \956}957 958/* SDI timings definitions */959 960/* SMPTE-125M */961#define V4L2_DV_BT_SDI_720X487I60 { \962 .type = V4L2_DV_BT_656_1120, \963 V4L2_INIT_BT_TIMINGS(720, 487, 1, \964 V4L2_DV_HSYNC_POS_POL, \965 13500000, 16, 121, 0, 0, 19, 0, 0, 19, 0, \966 V4L2_DV_BT_STD_SDI, \967 V4L2_DV_FL_FIRST_FIELD_EXTRA_LINE) \968}969 970#endif971