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1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */2/*3 * skl-tplg-interface.h - Intel DSP FW private data interface4 *5 * Copyright (C) 2015 Intel Corp6 * Author: Jeeja KP <jeeja.kp@intel.com>7 * Nilofer, Samreen <samreen.nilofer@intel.com>8 */9 10#ifndef __HDA_TPLG_INTERFACE_H__11#define __HDA_TPLG_INTERFACE_H__12 13#include <linux/types.h>14 15/*16 * Default types range from 0~12. type can range from 0 to 0xff17 * SST types start at higher to avoid any overlapping in future18 */19#define SKL_CONTROL_TYPE_BYTE_TLV 0x10020#define SKL_CONTROL_TYPE_MIC_SELECT 0x10221#define SKL_CONTROL_TYPE_MULTI_IO_SELECT 0x10322#define SKL_CONTROL_TYPE_MULTI_IO_SELECT_DMIC 0x10423 24#define HDA_SST_CFG_MAX 900 /* size of copier cfg*/25#define MAX_IN_QUEUE 826#define MAX_OUT_QUEUE 827 28#define SKL_UUID_STR_SZ 4029/* Event types goes here */30/* Reserve event type 0 for no event handlers */31enum skl_event_types {32 SKL_EVENT_NONE = 0,33 SKL_MIXER_EVENT,34 SKL_MUX_EVENT,35 SKL_VMIXER_EVENT,36 SKL_PGA_EVENT37};38 39/**40 * enum skl_ch_cfg - channel configuration41 *42 * @SKL_CH_CFG_MONO: One channel only43 * @SKL_CH_CFG_STEREO: L & R44 * @SKL_CH_CFG_2_1: L, R & LFE45 * @SKL_CH_CFG_3_0: L, C & R46 * @SKL_CH_CFG_3_1: L, C, R & LFE47 * @SKL_CH_CFG_QUATRO: L, R, Ls & Rs48 * @SKL_CH_CFG_4_0: L, C, R & Cs49 * @SKL_CH_CFG_5_0: L, C, R, Ls & Rs50 * @SKL_CH_CFG_5_1: L, C, R, Ls, Rs & LFE51 * @SKL_CH_CFG_DUAL_MONO: One channel replicated in two52 * @SKL_CH_CFG_I2S_DUAL_STEREO_0: Stereo(L,R) in 4 slots, 1st stream:[ L, R, -, - ]53 * @SKL_CH_CFG_I2S_DUAL_STEREO_1: Stereo(L,R) in 4 slots, 2nd stream:[ -, -, L, R ]54 * @SKL_CH_CFG_INVALID: Invalid55 */56enum skl_ch_cfg {57 SKL_CH_CFG_MONO = 0,58 SKL_CH_CFG_STEREO = 1,59 SKL_CH_CFG_2_1 = 2,60 SKL_CH_CFG_3_0 = 3,61 SKL_CH_CFG_3_1 = 4,62 SKL_CH_CFG_QUATRO = 5,63 SKL_CH_CFG_4_0 = 6,64 SKL_CH_CFG_5_0 = 7,65 SKL_CH_CFG_5_1 = 8,66 SKL_CH_CFG_DUAL_MONO = 9,67 SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10,68 SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11,69 SKL_CH_CFG_7_1 = 12,70 SKL_CH_CFG_4_CHANNEL = SKL_CH_CFG_7_1,71 SKL_CH_CFG_INVALID72};73 74enum skl_module_type {75 SKL_MODULE_TYPE_MIXER = 0,76 SKL_MODULE_TYPE_COPIER,77 SKL_MODULE_TYPE_UPDWMIX,78 SKL_MODULE_TYPE_SRCINT,79 SKL_MODULE_TYPE_ALGO,80 SKL_MODULE_TYPE_BASE_OUTFMT,81 SKL_MODULE_TYPE_KPB,82 SKL_MODULE_TYPE_MIC_SELECT,83};84 85enum skl_core_affinity {86 SKL_AFFINITY_CORE_0 = 0,87 SKL_AFFINITY_CORE_1,88 SKL_AFFINITY_CORE_MAX89};90 91enum skl_pipe_conn_type {92 SKL_PIPE_CONN_TYPE_NONE = 0,93 SKL_PIPE_CONN_TYPE_FE,94 SKL_PIPE_CONN_TYPE_BE95};96 97enum skl_hw_conn_type {98 SKL_CONN_NONE = 0,99 SKL_CONN_SOURCE = 1,100 SKL_CONN_SINK = 2101};102 103enum skl_dev_type {104 SKL_DEVICE_BT = 0x0,105 SKL_DEVICE_DMIC = 0x1,106 SKL_DEVICE_I2S = 0x2,107 SKL_DEVICE_SLIMBUS = 0x3,108 SKL_DEVICE_HDALINK = 0x4,109 SKL_DEVICE_HDAHOST = 0x5,110 SKL_DEVICE_NONE111};112 113/**114 * enum skl_interleaving - interleaving style115 *116 * @SKL_INTERLEAVING_PER_CHANNEL: [s1_ch1...s1_chN,...,sM_ch1...sM_chN]117 * @SKL_INTERLEAVING_PER_SAMPLE: [s1_ch1...sM_ch1,...,s1_chN...sM_chN]118 */119enum skl_interleaving {120 SKL_INTERLEAVING_PER_CHANNEL = 0,121 SKL_INTERLEAVING_PER_SAMPLE = 1,122};123 124enum skl_sample_type {125 SKL_SAMPLE_TYPE_INT_MSB = 0,126 SKL_SAMPLE_TYPE_INT_LSB = 1,127 SKL_SAMPLE_TYPE_INT_SIGNED = 2,128 SKL_SAMPLE_TYPE_INT_UNSIGNED = 3,129 SKL_SAMPLE_TYPE_FLOAT = 4130};131 132enum module_pin_type {133 /* All pins of the module takes same PCM inputs or outputs134 * e.g. mixout135 */136 SKL_PIN_TYPE_HOMOGENEOUS,137 /* All pins of the module takes different PCM inputs or outputs138 * e.g mux139 */140 SKL_PIN_TYPE_HETEROGENEOUS,141};142 143enum skl_module_param_type {144 SKL_PARAM_DEFAULT = 0,145 SKL_PARAM_INIT,146 SKL_PARAM_SET,147 SKL_PARAM_BIND148};149 150struct skl_dfw_algo_data {151 __u32 set_params:2;152 __u32 rsvd:30;153 __u32 param_id;154 __u32 max;155 char params[];156} __packed;157 158enum skl_tkn_dir {159 SKL_DIR_IN,160 SKL_DIR_OUT161};162 163enum skl_tuple_type {164 SKL_TYPE_TUPLE,165 SKL_TYPE_DATA166};167 168#endif169