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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Universal Flash Storage Host controller driver4 * Copyright (C) 2011-2013 Samsung India Software Operations5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.6 *7 * Authors:8 * Santosh Yaraganavi <santosh.sy@samsung.com>9 * Vinayak Holikatti <h.vinayak@samsung.com>10 */11 12#ifndef _UFSHCD_H13#define _UFSHCD_H14 15#include <linux/bitfield.h>16#include <linux/blk-crypto-profile.h>17#include <linux/blk-mq.h>18#include <linux/devfreq.h>19#include <linux/fault-inject.h>20#include <linux/debugfs.h>21#include <linux/msi.h>22#include <linux/pm_runtime.h>23#include <linux/dma-direction.h>24#include <scsi/scsi_device.h>25#include <scsi/scsi_host.h>26#include <ufs/unipro.h>27#include <ufs/ufs.h>28#include <ufs/ufs_quirks.h>29#include <ufs/ufshci.h>30 31#define UFSHCD "ufshcd"32 33struct scsi_device;34struct ufs_hba;35 36enum dev_cmd_type {37 DEV_CMD_TYPE_NOP = 0x0,38 DEV_CMD_TYPE_QUERY = 0x1,39 DEV_CMD_TYPE_RPMB = 0x2,40};41 42enum ufs_event_type {43 /* uic specific errors */44 UFS_EVT_PA_ERR = 0,45 UFS_EVT_DL_ERR,46 UFS_EVT_NL_ERR,47 UFS_EVT_TL_ERR,48 UFS_EVT_DME_ERR,49 50 /* fatal errors */51 UFS_EVT_AUTO_HIBERN8_ERR,52 UFS_EVT_FATAL_ERR,53 UFS_EVT_LINK_STARTUP_FAIL,54 UFS_EVT_RESUME_ERR,55 UFS_EVT_SUSPEND_ERR,56 UFS_EVT_WL_SUSP_ERR,57 UFS_EVT_WL_RES_ERR,58 59 /* abnormal events */60 UFS_EVT_DEV_RESET,61 UFS_EVT_HOST_RESET,62 UFS_EVT_ABORT,63 64 UFS_EVT_CNT,65};66 67/**68 * struct uic_command - UIC command structure69 * @command: UIC command70 * @argument1: UIC command argument 171 * @argument2: UIC command argument 272 * @argument3: UIC command argument 373 * @cmd_active: Indicate if UIC command is outstanding74 * @done: UIC command completion75 */76struct uic_command {77 const u32 command;78 const u32 argument1;79 u32 argument2;80 u32 argument3;81 int cmd_active;82 struct completion done;83};84 85/* Used to differentiate the power management options */86enum ufs_pm_op {87 UFS_RUNTIME_PM,88 UFS_SYSTEM_PM,89 UFS_SHUTDOWN_PM,90};91 92/* Host <-> Device UniPro Link state */93enum uic_link_state {94 UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */95 UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */96 UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */97 UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */98};99 100#define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE)101#define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \102 UIC_LINK_ACTIVE_STATE)103#define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \104 UIC_LINK_HIBERN8_STATE)105#define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \106 UIC_LINK_BROKEN_STATE)107#define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE)108#define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \109 UIC_LINK_ACTIVE_STATE)110#define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \111 UIC_LINK_HIBERN8_STATE)112#define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \113 UIC_LINK_BROKEN_STATE)114 115#define ufshcd_set_ufs_dev_active(h) \116 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)117#define ufshcd_set_ufs_dev_sleep(h) \118 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)119#define ufshcd_set_ufs_dev_poweroff(h) \120 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)121#define ufshcd_set_ufs_dev_deepsleep(h) \122 ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE)123#define ufshcd_is_ufs_dev_active(h) \124 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)125#define ufshcd_is_ufs_dev_sleep(h) \126 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)127#define ufshcd_is_ufs_dev_poweroff(h) \128 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)129#define ufshcd_is_ufs_dev_deepsleep(h) \130 ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE)131 132/*133 * UFS Power management levels.134 * Each level is in increasing order of power savings, except DeepSleep135 * which is lower than PowerDown with power on but not PowerDown with136 * power off.137 */138enum ufs_pm_level {139 UFS_PM_LVL_0,140 UFS_PM_LVL_1,141 UFS_PM_LVL_2,142 UFS_PM_LVL_3,143 UFS_PM_LVL_4,144 UFS_PM_LVL_5,145 UFS_PM_LVL_6,146 UFS_PM_LVL_MAX147};148 149struct ufs_pm_lvl_states {150 enum ufs_dev_pwr_mode dev_state;151 enum uic_link_state link_state;152};153 154/**155 * struct ufshcd_lrb - local reference block156 * @utr_descriptor_ptr: UTRD address of the command157 * @ucd_req_ptr: UCD address of the command158 * @ucd_rsp_ptr: Response UPIU address for this command159 * @ucd_prdt_ptr: PRDT address of the command160 * @utrd_dma_addr: UTRD dma address for debug161 * @ucd_prdt_dma_addr: PRDT dma address for debug162 * @ucd_rsp_dma_addr: UPIU response dma address for debug163 * @ucd_req_dma_addr: UPIU request dma address for debug164 * @cmd: pointer to SCSI command165 * @scsi_status: SCSI status of the command166 * @command_type: SCSI, UFS, Query.167 * @task_tag: Task tag of the command168 * @lun: LUN of the command169 * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation)170 * @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC)171 * @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock)172 * @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC)173 * @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock)174 * @crypto_key_slot: the key slot to use for inline crypto (-1 if none)175 * @data_unit_num: the data unit number for the first block for inline crypto176 * @req_abort_skip: skip request abort task flag177 */178struct ufshcd_lrb {179 struct utp_transfer_req_desc *utr_descriptor_ptr;180 struct utp_upiu_req *ucd_req_ptr;181 struct utp_upiu_rsp *ucd_rsp_ptr;182 struct ufshcd_sg_entry *ucd_prdt_ptr;183 184 dma_addr_t utrd_dma_addr;185 dma_addr_t ucd_req_dma_addr;186 dma_addr_t ucd_rsp_dma_addr;187 dma_addr_t ucd_prdt_dma_addr;188 189 struct scsi_cmnd *cmd;190 int scsi_status;191 192 int command_type;193 int task_tag;194 u8 lun; /* UPIU LUN id field is only 8-bit wide */195 bool intr_cmd;196 ktime_t issue_time_stamp;197 u64 issue_time_stamp_local_clock;198 ktime_t compl_time_stamp;199 u64 compl_time_stamp_local_clock;200#ifdef CONFIG_SCSI_UFS_CRYPTO201 int crypto_key_slot;202 u64 data_unit_num;203#endif204 205 bool req_abort_skip;206};207 208/**209 * struct ufs_query_req - parameters for building a query request210 * @query_func: UPIU header query function211 * @upiu_req: the query request data212 */213struct ufs_query_req {214 u8 query_func;215 struct utp_upiu_query upiu_req;216};217 218/**219 * struct ufs_query_resp - UPIU QUERY220 * @response: device response code221 * @upiu_res: query response data222 */223struct ufs_query_res {224 struct utp_upiu_query upiu_res;225};226 227/**228 * struct ufs_query - holds relevant data structures for query request229 * @request: request upiu and function230 * @descriptor: buffer for sending/receiving descriptor231 * @response: response upiu and response232 */233struct ufs_query {234 struct ufs_query_req request;235 u8 *descriptor;236 struct ufs_query_res response;237};238 239/**240 * struct ufs_dev_cmd - all assosiated fields with device management commands241 * @type: device management command type - Query, NOP OUT242 * @lock: lock to allow one command at a time243 * @complete: internal commands completion244 * @query: Device management query information245 */246struct ufs_dev_cmd {247 enum dev_cmd_type type;248 struct mutex lock;249 struct completion *complete;250 struct ufs_query query;251};252 253/**254 * struct ufs_clk_info - UFS clock related info255 * @list: list headed by hba->clk_list_head256 * @clk: clock node257 * @name: clock name258 * @max_freq: maximum frequency supported by the clock259 * @min_freq: min frequency that can be used for clock scaling260 * @curr_freq: indicates the current frequency that it is set to261 * @keep_link_active: indicates that the clk should not be disabled if262 * link is active263 * @enabled: variable to check against multiple enable/disable264 */265struct ufs_clk_info {266 struct list_head list;267 struct clk *clk;268 const char *name;269 u32 max_freq;270 u32 min_freq;271 u32 curr_freq;272 bool keep_link_active;273 bool enabled;274};275 276enum ufs_notify_change_status {277 PRE_CHANGE,278 POST_CHANGE,279};280 281struct ufs_pa_layer_attr {282 u32 gear_rx;283 u32 gear_tx;284 u32 lane_rx;285 u32 lane_tx;286 u32 pwr_rx;287 u32 pwr_tx;288 u32 hs_rate;289};290 291struct ufs_pwr_mode_info {292 bool is_valid;293 struct ufs_pa_layer_attr info;294};295 296/**297 * struct ufs_hba_variant_ops - variant specific callbacks298 * @name: variant name299 * @max_num_rtt: maximum RTT supported by the host300 * @init: called when the driver is initialized301 * @exit: called to cleanup everything done in init302 * @get_ufs_hci_version: called to get UFS HCI version303 * @clk_scale_notify: notifies that clks are scaled up/down304 * @setup_clocks: called before touching any of the controller registers305 * @hce_enable_notify: called before and after HCE enable bit is set to allow306 * variant specific Uni-Pro initialization.307 * @link_startup_notify: called before and after Link startup is carried out308 * to allow variant specific Uni-Pro initialization.309 * @pwr_change_notify: called before and after a power mode change310 * is carried out to allow vendor spesific capabilities311 * to be set.312 * @setup_xfer_req: called before any transfer request is issued313 * to set some things314 * @setup_task_mgmt: called before any task management request is issued315 * to set some things316 * @hibern8_notify: called around hibern8 enter/exit317 * @apply_dev_quirks: called to apply device specific quirks318 * @fixup_dev_quirks: called to modify device specific quirks319 * @suspend: called during host controller PM callback320 * @resume: called during host controller PM callback321 * @dbg_register_dump: used to dump controller debug information322 * @phy_initialization: used to initialize phys323 * @device_reset: called to issue a reset pulse on the UFS device324 * @config_scaling_param: called to configure clock scaling parameters325 * @program_key: program or evict an inline encryption key326 * @fill_crypto_prdt: initialize crypto-related fields in the PRDT327 * @event_notify: called to notify important events328 * @reinit_notify: called to notify reinit of UFSHCD during max gear switch329 * @mcq_config_resource: called to configure MCQ platform resources330 * @get_hba_mac: reports maximum number of outstanding commands supported by331 * the controller. Should be implemented for UFSHCI 4.0 or later332 * controllers that are not compliant with the UFSHCI 4.0 specification.333 * @op_runtime_config: called to config Operation and runtime regs Pointers334 * @get_outstanding_cqs: called to get outstanding completion queues335 * @config_esi: called to config Event Specific Interrupt336 * @config_scsi_dev: called to configure SCSI device parameters337 */338struct ufs_hba_variant_ops {339 const char *name;340 int max_num_rtt;341 int (*init)(struct ufs_hba *);342 void (*exit)(struct ufs_hba *);343 u32 (*get_ufs_hci_version)(struct ufs_hba *);344 int (*clk_scale_notify)(struct ufs_hba *, bool,345 enum ufs_notify_change_status);346 int (*setup_clocks)(struct ufs_hba *, bool,347 enum ufs_notify_change_status);348 int (*hce_enable_notify)(struct ufs_hba *,349 enum ufs_notify_change_status);350 int (*link_startup_notify)(struct ufs_hba *,351 enum ufs_notify_change_status);352 int (*pwr_change_notify)(struct ufs_hba *,353 enum ufs_notify_change_status status,354 struct ufs_pa_layer_attr *,355 struct ufs_pa_layer_attr *);356 void (*setup_xfer_req)(struct ufs_hba *hba, int tag,357 bool is_scsi_cmd);358 void (*setup_task_mgmt)(struct ufs_hba *, int, u8);359 void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme,360 enum ufs_notify_change_status);361 int (*apply_dev_quirks)(struct ufs_hba *hba);362 void (*fixup_dev_quirks)(struct ufs_hba *hba);363 int (*suspend)(struct ufs_hba *, enum ufs_pm_op,364 enum ufs_notify_change_status);365 int (*resume)(struct ufs_hba *, enum ufs_pm_op);366 void (*dbg_register_dump)(struct ufs_hba *hba);367 int (*phy_initialization)(struct ufs_hba *);368 int (*device_reset)(struct ufs_hba *hba);369 void (*config_scaling_param)(struct ufs_hba *hba,370 struct devfreq_dev_profile *profile,371 struct devfreq_simple_ondemand_data *data);372 int (*program_key)(struct ufs_hba *hba,373 const union ufs_crypto_cfg_entry *cfg, int slot);374 int (*fill_crypto_prdt)(struct ufs_hba *hba,375 const struct bio_crypt_ctx *crypt_ctx,376 void *prdt, unsigned int num_segments);377 void (*event_notify)(struct ufs_hba *hba,378 enum ufs_event_type evt, void *data);379 void (*reinit_notify)(struct ufs_hba *);380 int (*mcq_config_resource)(struct ufs_hba *hba);381 int (*get_hba_mac)(struct ufs_hba *hba);382 int (*op_runtime_config)(struct ufs_hba *hba);383 int (*get_outstanding_cqs)(struct ufs_hba *hba,384 unsigned long *ocqs);385 int (*config_esi)(struct ufs_hba *hba);386};387 388/* clock gating state */389enum clk_gating_state {390 CLKS_OFF,391 CLKS_ON,392 REQ_CLKS_OFF,393 REQ_CLKS_ON,394};395 396/**397 * struct ufs_clk_gating - UFS clock gating related info398 * @gate_work: worker to turn off clocks after some delay as specified in399 * delay_ms400 * @ungate_work: worker to turn on clocks that will be used in case of401 * interrupt context402 * @state: the current clocks state403 * @delay_ms: gating delay in ms404 * @is_suspended: clk gating is suspended when set to 1 which can be used405 * during suspend/resume406 * @delay_attr: sysfs attribute to control delay_attr407 * @enable_attr: sysfs attribute to enable/disable clock gating408 * @is_enabled: Indicates the current status of clock gating409 * @is_initialized: Indicates whether clock gating is initialized or not410 * @active_reqs: number of requests that are pending and should be waited for411 * completion before gating clocks.412 * @clk_gating_workq: workqueue for clock gating work.413 */414struct ufs_clk_gating {415 struct delayed_work gate_work;416 struct work_struct ungate_work;417 enum clk_gating_state state;418 unsigned long delay_ms;419 bool is_suspended;420 struct device_attribute delay_attr;421 struct device_attribute enable_attr;422 bool is_enabled;423 bool is_initialized;424 int active_reqs;425 struct workqueue_struct *clk_gating_workq;426};427 428/**429 * struct ufs_clk_scaling - UFS clock scaling related data430 * @active_reqs: number of requests that are pending. If this is zero when431 * devfreq ->target() function is called then schedule "suspend_work" to432 * suspend devfreq.433 * @tot_busy_t: Total busy time in current polling window434 * @window_start_t: Start time (in jiffies) of the current polling window435 * @busy_start_t: Start time of current busy period436 * @enable_attr: sysfs attribute to enable/disable clock scaling437 * @saved_pwr_info: UFS power mode may also be changed during scaling and this438 * one keeps track of previous power mode.439 * @workq: workqueue to schedule devfreq suspend/resume work440 * @suspend_work: worker to suspend devfreq441 * @resume_work: worker to resume devfreq442 * @target_freq: frequency requested by devfreq framework443 * @min_gear: lowest HS gear to scale down to444 * @is_enabled: tracks if scaling is currently enabled or not, controlled by445 * clkscale_enable sysfs node446 * @is_allowed: tracks if scaling is currently allowed or not, used to block447 * clock scaling which is not invoked from devfreq governor448 * @is_initialized: Indicates whether clock scaling is initialized or not449 * @is_busy_started: tracks if busy period has started or not450 * @is_suspended: tracks if devfreq is suspended or not451 */452struct ufs_clk_scaling {453 int active_reqs;454 unsigned long tot_busy_t;455 ktime_t window_start_t;456 ktime_t busy_start_t;457 struct device_attribute enable_attr;458 struct ufs_pa_layer_attr saved_pwr_info;459 struct workqueue_struct *workq;460 struct work_struct suspend_work;461 struct work_struct resume_work;462 unsigned long target_freq;463 u32 min_gear;464 bool is_enabled;465 bool is_allowed;466 bool is_initialized;467 bool is_busy_started;468 bool is_suspended;469 bool suspend_on_no_request;470};471 472#define UFS_EVENT_HIST_LENGTH 8473/**474 * struct ufs_event_hist - keeps history of errors475 * @pos: index to indicate cyclic buffer position476 * @val: cyclic buffer for registers value477 * @tstamp: cyclic buffer for time stamp478 * @cnt: error counter479 */480struct ufs_event_hist {481 int pos;482 u32 val[UFS_EVENT_HIST_LENGTH];483 u64 tstamp[UFS_EVENT_HIST_LENGTH];484 unsigned long long cnt;485};486 487/**488 * struct ufs_stats - keeps usage/err statistics489 * @last_intr_status: record the last interrupt status.490 * @last_intr_ts: record the last interrupt timestamp.491 * @hibern8_exit_cnt: Counter to keep track of number of exits,492 * reset this after link-startup.493 * @last_hibern8_exit_tstamp: Set time after the hibern8 exit.494 * Clear after the first successful command completion.495 * @event: array with event history.496 */497struct ufs_stats {498 u32 last_intr_status;499 u64 last_intr_ts;500 501 u32 hibern8_exit_cnt;502 u64 last_hibern8_exit_tstamp;503 struct ufs_event_hist event[UFS_EVT_CNT];504};505 506/**507 * enum ufshcd_state - UFS host controller state508 * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command509 * processing.510 * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process511 * SCSI commands.512 * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled.513 * SCSI commands may be submitted to the controller.514 * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail515 * newly submitted SCSI commands with error code DID_BAD_TARGET.516 * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery517 * failed. Fail all SCSI commands with error code DID_ERROR.518 */519enum ufshcd_state {520 UFSHCD_STATE_RESET,521 UFSHCD_STATE_OPERATIONAL,522 UFSHCD_STATE_EH_SCHEDULED_NON_FATAL,523 UFSHCD_STATE_EH_SCHEDULED_FATAL,524 UFSHCD_STATE_ERROR,525};526 527enum ufshcd_quirks {528 /* Interrupt aggregation support is broken */529 UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0,530 531 /*532 * delay before each dme command is required as the unipro533 * layer has shown instabilities534 */535 UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1,536 537 /*538 * If UFS host controller is having issue in processing LCC (Line539 * Control Command) coming from device then enable this quirk.540 * When this quirk is enabled, host controller driver should disable541 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE542 * attribute of device to 0).543 */544 UFSHCD_QUIRK_BROKEN_LCC = 1 << 2,545 546 /*547 * The attribute PA_RXHSUNTERMCAP specifies whether or not the548 * inbound Link supports unterminated line in HS mode. Setting this549 * attribute to 1 fixes moving to HS gear.550 */551 UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3,552 553 /*554 * This quirk needs to be enabled if the host controller only allows555 * accessing the peer dme attributes in AUTO mode (FAST AUTO or556 * SLOW AUTO).557 */558 UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4,559 560 /*561 * This quirk needs to be enabled if the host controller doesn't562 * advertise the correct version in UFS_VER register. If this quirk563 * is enabled, standard UFS host driver will call the vendor specific564 * ops (get_ufs_hci_version) to get the correct version.565 */566 UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5,567 568 /*569 * Clear handling for transfer/task request list is just opposite.570 */571 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6,572 573 /*574 * This quirk needs to be enabled if host controller doesn't allow575 * that the interrupt aggregation timer and counter are reset by s/w.576 */577 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7,578 579 /*580 * This quirks needs to be enabled if host controller cannot be581 * enabled via HCE register.582 */583 UFSHCI_QUIRK_BROKEN_HCE = 1 << 8,584 585 /*586 * This quirk needs to be enabled if the host controller regards587 * resolution of the values of PRDTO and PRDTL in UTRD as byte.588 */589 UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9,590 591 /*592 * This quirk needs to be enabled if the host controller reports593 * OCS FATAL ERROR with device error through sense data594 */595 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10,596 597 /*598 * This quirk needs to be enabled if the host controller has599 * auto-hibernate capability but it doesn't work.600 */601 UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11,602 603 /*604 * This quirk needs to disable manual flush for write booster605 */606 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12,607 608 /*609 * This quirk needs to disable unipro timeout values610 * before power mode change611 */612 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13,613 614 /*615 * This quirk needs to be enabled if the host controller does not616 * support UIC command617 */618 UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15,619 620 /*621 * This quirk needs to be enabled if the host controller cannot622 * support physical host configuration.623 */624 UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16,625 626 /*627 * This quirk needs to be enabled if the host controller has628 * 64-bit addressing supported capability but it doesn't work.629 */630 UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS = 1 << 17,631 632 /*633 * This quirk needs to be enabled if the host controller has634 * auto-hibernate capability but it's FASTAUTO only.635 */636 UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18,637 638 /*639 * This quirk needs to be enabled if the host controller needs640 * to reinit the device after switching to maximum gear.641 */642 UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19,643 644 /*645 * Some host raises interrupt (per queue) in addition to646 * CQES (traditional) when ESI is disabled.647 * Enable this quirk will disable CQES and use per queue interrupt.648 */649 UFSHCD_QUIRK_MCQ_BROKEN_INTR = 1 << 20,650 651 /*652 * Some host does not implement SQ Run Time Command (SQRTC) register653 * thus need this quirk to skip related flow.654 */655 UFSHCD_QUIRK_MCQ_BROKEN_RTC = 1 << 21,656 657 /*658 * This quirk needs to be enabled if the host controller supports inline659 * encryption but it needs to initialize the crypto capabilities in a660 * nonstandard way and/or needs to override blk_crypto_ll_ops. If661 * enabled, the standard code won't initialize the blk_crypto_profile;662 * ufs_hba_variant_ops::init() must do it instead.663 */664 UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE = 1 << 22,665 666 /*667 * This quirk needs to be enabled if the host controller supports inline668 * encryption but does not support the CRYPTO_GENERAL_ENABLE bit, i.e.669 * host controller initialization fails if that bit is set.670 */671 UFSHCD_QUIRK_BROKEN_CRYPTO_ENABLE = 1 << 23,672 673 /*674 * This quirk needs to be enabled if the host controller driver copies675 * cryptographic keys into the PRDT in order to send them to hardware,676 * and therefore the PRDT should be zeroized after each request (as per677 * the standard best practice for managing keys).678 */679 UFSHCD_QUIRK_KEYS_IN_PRDT = 1 << 24,680 681 /*682 * This quirk indicates that the controller reports the value 1 (not683 * supported) in the Legacy Single DoorBell Support (LSDBS) bit of the684 * Controller Capabilities register although it supports the legacy685 * single doorbell mode.686 */687 UFSHCD_QUIRK_BROKEN_LSDBS_CAP = 1 << 25,688};689 690enum ufshcd_caps {691 /* Allow dynamic clk gating */692 UFSHCD_CAP_CLK_GATING = 1 << 0,693 694 /* Allow hiberb8 with clk gating */695 UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1,696 697 /* Allow dynamic clk scaling */698 UFSHCD_CAP_CLK_SCALING = 1 << 2,699 700 /* Allow auto bkops to enabled during runtime suspend */701 UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3,702 703 /*704 * This capability allows host controller driver to use the UFS HCI's705 * interrupt aggregation capability.706 * CAUTION: Enabling this might reduce overall UFS throughput.707 */708 UFSHCD_CAP_INTR_AGGR = 1 << 4,709 710 /*711 * This capability allows the device auto-bkops to be always enabled712 * except during suspend (both runtime and suspend).713 * Enabling this capability means that device will always be allowed714 * to do background operation when it's active but it might degrade715 * the performance of ongoing read/write operations.716 */717 UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5,718 719 /*720 * This capability allows host controller driver to automatically721 * enable runtime power management by itself instead of waiting722 * for userspace to control the power management.723 */724 UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6,725 726 /*727 * This capability allows the host controller driver to turn-on728 * WriteBooster, if the underlying device supports it and is729 * provisioned to be used. This would increase the write performance.730 */731 UFSHCD_CAP_WB_EN = 1 << 7,732 733 /*734 * This capability allows the host controller driver to use the735 * inline crypto engine, if it is present736 */737 UFSHCD_CAP_CRYPTO = 1 << 8,738 739 /*740 * This capability allows the controller regulators to be put into741 * lpm mode aggressively during clock gating.742 * This would increase power savings.743 */744 UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9,745 746 /*747 * This capability allows the host controller driver to use DeepSleep,748 * if it is supported by the UFS device. The host controller driver must749 * support device hardware reset via the hba->device_reset() callback,750 * in order to exit DeepSleep state.751 */752 UFSHCD_CAP_DEEPSLEEP = 1 << 10,753 754 /*755 * This capability allows the host controller driver to use temperature756 * notification if it is supported by the UFS device.757 */758 UFSHCD_CAP_TEMP_NOTIF = 1 << 11,759 760 /*761 * Enable WriteBooster when scaling up the clock and disable762 * WriteBooster when scaling the clock down.763 */764 UFSHCD_CAP_WB_WITH_CLK_SCALING = 1 << 12,765};766 767struct ufs_hba_variant_params {768 struct devfreq_dev_profile devfreq_profile;769 struct devfreq_simple_ondemand_data ondemand_data;770 u16 hba_enable_delay_us;771 u32 wb_flush_threshold;772};773 774struct ufs_hba_monitor {775 unsigned long chunk_size;776 777 unsigned long nr_sec_rw[2];778 ktime_t total_busy[2];779 780 unsigned long nr_req[2];781 /* latencies*/782 ktime_t lat_sum[2];783 ktime_t lat_max[2];784 ktime_t lat_min[2];785 786 u32 nr_queued[2];787 ktime_t busy_start_ts[2];788 789 ktime_t enabled_ts;790 bool enabled;791};792 793/**794 * struct ufshcd_res_info_t - MCQ related resource regions795 *796 * @name: resource name797 * @resource: pointer to resource region798 * @base: register base address799 */800struct ufshcd_res_info {801 const char *name;802 struct resource *resource;803 void __iomem *base;804};805 806enum ufshcd_res {807 RES_UFS,808 RES_MCQ,809 RES_MCQ_SQD,810 RES_MCQ_SQIS,811 RES_MCQ_CQD,812 RES_MCQ_CQIS,813 RES_MCQ_VS,814 RES_MAX,815};816 817/**818 * struct ufshcd_mcq_opr_info_t - Operation and Runtime registers819 *820 * @offset: Doorbell Address Offset821 * @stride: Steps proportional to queue [0...31]822 * @base: base address823 */824struct ufshcd_mcq_opr_info_t {825 unsigned long offset;826 unsigned long stride;827 void __iomem *base;828};829 830enum ufshcd_mcq_opr {831 OPR_SQD,832 OPR_SQIS,833 OPR_CQD,834 OPR_CQIS,835 OPR_MAX,836};837 838/**839 * struct ufs_hba - per adapter private structure840 * @mmio_base: UFSHCI base register address841 * @ucdl_base_addr: UFS Command Descriptor base address842 * @utrdl_base_addr: UTP Transfer Request Descriptor base address843 * @utmrdl_base_addr: UTP Task Management Descriptor base address844 * @ucdl_dma_addr: UFS Command Descriptor DMA address845 * @utrdl_dma_addr: UTRDL DMA address846 * @utmrdl_dma_addr: UTMRDL DMA address847 * @host: Scsi_Host instance of the driver848 * @dev: device handle849 * @ufs_device_wlun: WLUN that controls the entire UFS device.850 * @hwmon_device: device instance registered with the hwmon core.851 * @curr_dev_pwr_mode: active UFS device power mode.852 * @uic_link_state: active state of the link to the UFS device.853 * @rpm_lvl: desired UFS power management level during runtime PM.854 * @spm_lvl: desired UFS power management level during system PM.855 * @pm_op_in_progress: whether or not a PM operation is in progress.856 * @ahit: value of Auto-Hibernate Idle Timer register.857 * @lrb: local reference block858 * @outstanding_tasks: Bits representing outstanding task requests859 * @outstanding_lock: Protects @outstanding_reqs.860 * @outstanding_reqs: Bits representing outstanding transfer requests861 * @capabilities: UFS Controller Capabilities862 * @mcq_capabilities: UFS Multi Circular Queue capabilities863 * @nutrs: Transfer Request Queue depth supported by controller864 * @nortt - Max outstanding RTTs supported by controller865 * @nutmrs: Task Management Queue depth supported by controller866 * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock.867 * @ufs_version: UFS Version to which controller complies868 * @vops: pointer to variant specific operations869 * @vps: pointer to variant specific parameters870 * @priv: pointer to variant specific private data871 * @sg_entry_size: size of struct ufshcd_sg_entry (may include variant fields)872 * @irq: Irq number of the controller873 * @is_irq_enabled: whether or not the UFS controller interrupt is enabled.874 * @dev_ref_clk_freq: reference clock frequency875 * @quirks: bitmask with information about deviations from the UFSHCI standard.876 * @dev_quirks: bitmask with information about deviations from the UFS standard.877 * @tmf_tag_set: TMF tag set.878 * @tmf_queue: Used to allocate TMF tags.879 * @tmf_rqs: array with pointers to TMF requests while these are in progress.880 * @active_uic_cmd: handle of active UIC command881 * @uic_cmd_mutex: mutex for UIC command882 * @uic_async_done: completion used during UIC processing883 * @ufshcd_state: UFSHCD state884 * @eh_flags: Error handling flags885 * @intr_mask: Interrupt Mask Bits886 * @ee_ctrl_mask: Exception event control mask887 * @ee_drv_mask: Exception event mask for driver888 * @ee_usr_mask: Exception event mask for user (set via debugfs)889 * @ee_ctrl_mutex: Used to serialize exception event information.890 * @is_powered: flag to check if HBA is powered891 * @shutting_down: flag to check if shutdown has been invoked892 * @host_sem: semaphore used to serialize concurrent contexts893 * @eh_wq: Workqueue that eh_work works on894 * @eh_work: Worker to handle UFS errors that require s/w attention895 * @eeh_work: Worker to handle exception events896 * @errors: HBA errors897 * @uic_error: UFS interconnect layer error status898 * @saved_err: sticky error mask899 * @saved_uic_err: sticky UIC error mask900 * @ufs_stats: various error counters901 * @force_reset: flag to force eh_work perform a full reset902 * @force_pmc: flag to force a power mode change903 * @silence_err_logs: flag to silence error logs904 * @dev_cmd: ufs device management command information905 * @last_dme_cmd_tstamp: time stamp of the last completed DME command906 * @nop_out_timeout: NOP OUT timeout value907 * @dev_info: information about the UFS device908 * @auto_bkops_enabled: to track whether bkops is enabled in device909 * @vreg_info: UFS device voltage regulator information910 * @clk_list_head: UFS host controller clocks list node head911 * @use_pm_opp: Indicates whether OPP based scaling is used or not912 * @req_abort_count: number of times ufshcd_abort() has been called913 * @lanes_per_direction: number of lanes per data direction between the UFS914 * controller and the UFS device.915 * @pwr_info: holds current power mode916 * @max_pwr_info: keeps the device max valid pwm917 * @clk_gating: information related to clock gating918 * @caps: bitmask with information about UFS controller capabilities919 * @devfreq: frequency scaling information owned by the devfreq core920 * @clk_scaling: frequency scaling information owned by the UFS driver921 * @system_suspending: system suspend has been started and system resume has922 * not yet finished.923 * @is_sys_suspended: UFS device has been suspended because of system suspend924 * @urgent_bkops_lvl: keeps track of urgent bkops level for device925 * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for926 * device is known or not.927 * @wb_mutex: used to serialize devfreq and sysfs write booster toggling928 * @clk_scaling_lock: used to serialize device commands and clock scaling929 * @desc_size: descriptor sizes reported by device930 * @scsi_block_reqs_cnt: reference counting for scsi block requests931 * @bsg_dev: struct device associated with the BSG queue932 * @bsg_queue: BSG queue associated with the UFS controller933 * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power934 * management) after the UFS device has finished a WriteBooster buffer935 * flush or auto BKOP.936 * @monitor: statistics about UFS commands937 * @crypto_capabilities: Content of crypto capabilities register (0x100)938 * @crypto_cap_array: Array of crypto capabilities939 * @crypto_cfg_register: Start of the crypto cfg array940 * @crypto_profile: the crypto profile of this hba (if applicable)941 * @debugfs_root: UFS controller debugfs root directory942 * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay943 * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore944 * ee_ctrl_mask945 * @luns_avail: number of regular and well known LUNs supported by the UFS946 * device947 * @nr_hw_queues: number of hardware queues configured948 * @nr_queues: number of Queues of different queue types949 * @complete_put: whether or not to call ufshcd_rpm_put() from inside950 * ufshcd_resume_complete()951 * @ext_iid_sup: is EXT_IID is supported by UFSHC952 * @mcq_sup: is mcq supported by UFSHC953 * @mcq_enabled: is mcq ready to accept requests954 * @res: array of resource info of MCQ registers955 * @mcq_base: Multi circular queue registers base address956 * @uhq: array of supported hardware queues957 * @dev_cmd_queue: Queue for issuing device management commands958 * @mcq_opr: MCQ operation and runtime registers959 * @ufs_rtc_update_work: A work for UFS RTC periodic update960 * @pm_qos_req: PM QoS request handle961 * @pm_qos_enabled: flag to check if pm qos is enabled962 */963struct ufs_hba {964 void __iomem *mmio_base;965 966 /* Virtual memory reference */967 struct utp_transfer_cmd_desc *ucdl_base_addr;968 struct utp_transfer_req_desc *utrdl_base_addr;969 struct utp_task_req_desc *utmrdl_base_addr;970 971 /* DMA memory reference */972 dma_addr_t ucdl_dma_addr;973 dma_addr_t utrdl_dma_addr;974 dma_addr_t utmrdl_dma_addr;975 976 struct Scsi_Host *host;977 struct device *dev;978 struct scsi_device *ufs_device_wlun;979 980#ifdef CONFIG_SCSI_UFS_HWMON981 struct device *hwmon_device;982#endif983 984 enum ufs_dev_pwr_mode curr_dev_pwr_mode;985 enum uic_link_state uic_link_state;986 /* Desired UFS power management level during runtime PM */987 enum ufs_pm_level rpm_lvl;988 /* Desired UFS power management level during system PM */989 enum ufs_pm_level spm_lvl;990 int pm_op_in_progress;991 992 /* Auto-Hibernate Idle Timer register value */993 u32 ahit;994 995 struct ufshcd_lrb *lrb;996 997 unsigned long outstanding_tasks;998 spinlock_t outstanding_lock;999 unsigned long outstanding_reqs;1000 1001 u32 capabilities;1002 int nutrs;1003 int nortt;1004 u32 mcq_capabilities;1005 int nutmrs;1006 u32 reserved_slot;1007 u32 ufs_version;1008 const struct ufs_hba_variant_ops *vops;1009 struct ufs_hba_variant_params *vps;1010 void *priv;1011#ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE1012 size_t sg_entry_size;1013#endif1014 unsigned int irq;1015 bool is_irq_enabled;1016 enum ufs_ref_clk_freq dev_ref_clk_freq;1017 1018 unsigned int quirks; /* Deviations from standard UFSHCI spec. */1019 1020 /* Device deviations from standard UFS device spec. */1021 unsigned int dev_quirks;1022 1023 struct blk_mq_tag_set tmf_tag_set;1024 struct request_queue *tmf_queue;1025 struct request **tmf_rqs;1026 1027 struct uic_command *active_uic_cmd;1028 struct mutex uic_cmd_mutex;1029 struct completion *uic_async_done;1030 1031 enum ufshcd_state ufshcd_state;1032 u32 eh_flags;1033 u32 intr_mask;1034 u16 ee_ctrl_mask;1035 u16 ee_drv_mask;1036 u16 ee_usr_mask;1037 struct mutex ee_ctrl_mutex;1038 bool is_powered;1039 bool shutting_down;1040 struct semaphore host_sem;1041 1042 /* Work Queues */1043 struct workqueue_struct *eh_wq;1044 struct work_struct eh_work;1045 struct work_struct eeh_work;1046 1047 /* HBA Errors */1048 u32 errors;1049 u32 uic_error;1050 u32 saved_err;1051 u32 saved_uic_err;1052 struct ufs_stats ufs_stats;1053 bool force_reset;1054 bool force_pmc;1055 bool silence_err_logs;1056 1057 /* Device management request data */1058 struct ufs_dev_cmd dev_cmd;1059 ktime_t last_dme_cmd_tstamp;1060 int nop_out_timeout;1061 1062 /* Keeps information of the UFS device connected to this host */1063 struct ufs_dev_info dev_info;1064 bool auto_bkops_enabled;1065 struct ufs_vreg_info vreg_info;1066 struct list_head clk_list_head;1067 bool use_pm_opp;1068 1069 /* Number of requests aborts */1070 int req_abort_count;1071 1072 /* Number of lanes available (1 or 2) for Rx/Tx */1073 u32 lanes_per_direction;1074 struct ufs_pa_layer_attr pwr_info;1075 struct ufs_pwr_mode_info max_pwr_info;1076 1077 struct ufs_clk_gating clk_gating;1078 /* Control to enable/disable host capabilities */1079 u32 caps;1080 1081 struct devfreq *devfreq;1082 struct ufs_clk_scaling clk_scaling;1083 bool system_suspending;1084 bool is_sys_suspended;1085 1086 enum bkops_status urgent_bkops_lvl;1087 bool is_urgent_bkops_lvl_checked;1088 1089 struct mutex wb_mutex;1090 struct rw_semaphore clk_scaling_lock;1091 atomic_t scsi_block_reqs_cnt;1092 1093 struct device bsg_dev;1094 struct request_queue *bsg_queue;1095 struct delayed_work rpm_dev_flush_recheck_work;1096 1097 struct ufs_hba_monitor monitor;1098 1099#ifdef CONFIG_SCSI_UFS_CRYPTO1100 union ufs_crypto_capabilities crypto_capabilities;1101 union ufs_crypto_cap_entry *crypto_cap_array;1102 u32 crypto_cfg_register;1103 struct blk_crypto_profile crypto_profile;1104#endif1105#ifdef CONFIG_DEBUG_FS1106 struct dentry *debugfs_root;1107 struct delayed_work debugfs_ee_work;1108 u32 debugfs_ee_rate_limit_ms;1109#endif1110#ifdef CONFIG_SCSI_UFS_FAULT_INJECTION1111 struct fault_attr trigger_eh_attr;1112 struct fault_attr timeout_attr;1113#endif1114 u32 luns_avail;1115 unsigned int nr_hw_queues;1116 unsigned int nr_queues[HCTX_MAX_TYPES];1117 bool complete_put;1118 bool ext_iid_sup;1119 bool scsi_host_added;1120 bool mcq_sup;1121 bool lsdb_sup;1122 bool mcq_enabled;1123 struct ufshcd_res_info res[RES_MAX];1124 void __iomem *mcq_base;1125 struct ufs_hw_queue *uhq;1126 struct ufs_hw_queue *dev_cmd_queue;1127 struct ufshcd_mcq_opr_info_t mcq_opr[OPR_MAX];1128 1129 struct delayed_work ufs_rtc_update_work;1130 struct pm_qos_request pm_qos_req;1131 bool pm_qos_enabled;1132};1133 1134/**1135 * struct ufs_hw_queue - per hardware queue structure1136 * @mcq_sq_head: base address of submission queue head pointer1137 * @mcq_sq_tail: base address of submission queue tail pointer1138 * @mcq_cq_head: base address of completion queue head pointer1139 * @mcq_cq_tail: base address of completion queue tail pointer1140 * @sqe_base_addr: submission queue entry base address1141 * @sqe_dma_addr: submission queue dma address1142 * @cqe_base_addr: completion queue base address1143 * @cqe_dma_addr: completion queue dma address1144 * @max_entries: max number of slots in this hardware queue1145 * @id: hardware queue ID1146 * @sq_tp_slot: current slot to which SQ tail pointer is pointing1147 * @sq_lock: serialize submission queue access1148 * @cq_tail_slot: current slot to which CQ tail pointer is pointing1149 * @cq_head_slot: current slot to which CQ head pointer is pointing1150 * @cq_lock: Synchronize between multiple polling instances1151 * @sq_mutex: prevent submission queue concurrent access1152 */1153struct ufs_hw_queue {1154 void __iomem *mcq_sq_head;1155 void __iomem *mcq_sq_tail;1156 void __iomem *mcq_cq_head;1157 void __iomem *mcq_cq_tail;1158 1159 struct utp_transfer_req_desc *sqe_base_addr;1160 dma_addr_t sqe_dma_addr;1161 struct cq_entry *cqe_base_addr;1162 dma_addr_t cqe_dma_addr;1163 u32 max_entries;1164 u32 id;1165 u32 sq_tail_slot;1166 spinlock_t sq_lock;1167 u32 cq_tail_slot;1168 u32 cq_head_slot;1169 spinlock_t cq_lock;1170 /* prevent concurrent access to submission queue */1171 struct mutex sq_mutex;1172};1173 1174#define MCQ_QCFG_SIZE 0x401175 1176static inline unsigned int ufshcd_mcq_opr_offset(struct ufs_hba *hba,1177 enum ufshcd_mcq_opr opr, int idx)1178{1179 return hba->mcq_opr[opr].offset + hba->mcq_opr[opr].stride * idx;1180}1181 1182static inline unsigned int ufshcd_mcq_cfg_offset(unsigned int reg, int idx)1183{1184 return reg + MCQ_QCFG_SIZE * idx;1185}1186 1187#ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE1188static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba)1189{1190 return hba->sg_entry_size;1191}1192 1193static inline void ufshcd_set_sg_entry_size(struct ufs_hba *hba, size_t sg_entry_size)1194{1195 WARN_ON_ONCE(sg_entry_size < sizeof(struct ufshcd_sg_entry));1196 hba->sg_entry_size = sg_entry_size;1197}1198#else1199static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba)1200{1201 return sizeof(struct ufshcd_sg_entry);1202}1203 1204#define ufshcd_set_sg_entry_size(hba, sg_entry_size) \1205 ({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); })1206#endif1207 1208static inline size_t ufshcd_get_ucd_size(const struct ufs_hba *hba)1209{1210 return sizeof(struct utp_transfer_cmd_desc) + SG_ALL * ufshcd_sg_entry_size(hba);1211}1212 1213/* Returns true if clocks can be gated. Otherwise false */1214static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba)1215{1216 return hba->caps & UFSHCD_CAP_CLK_GATING;1217}1218static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba)1219{1220 return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;1221}1222static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba)1223{1224 return hba->caps & UFSHCD_CAP_CLK_SCALING;1225}1226static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba)1227{1228 return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND;1229}1230static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba)1231{1232 return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND;1233}1234 1235static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba)1236{1237 return (hba->caps & UFSHCD_CAP_INTR_AGGR) &&1238 !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR);1239}1240 1241static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba)1242{1243 return !!(ufshcd_is_link_hibern8(hba) &&1244 (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE));1245}1246 1247static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba)1248{1249 return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) &&1250 !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8);1251}1252 1253static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba)1254{1255 return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit);1256}1257 1258static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba)1259{1260 return hba->caps & UFSHCD_CAP_WB_EN;1261}1262 1263static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba)1264{1265 return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING;1266}1267 1268#define ufsmcq_writel(hba, val, reg) \1269 writel((val), (hba)->mcq_base + (reg))1270#define ufsmcq_readl(hba, reg) \1271 readl((hba)->mcq_base + (reg))1272 1273#define ufsmcq_writelx(hba, val, reg) \1274 writel_relaxed((val), (hba)->mcq_base + (reg))1275#define ufsmcq_readlx(hba, reg) \1276 readl_relaxed((hba)->mcq_base + (reg))1277 1278#define ufshcd_writel(hba, val, reg) \1279 writel((val), (hba)->mmio_base + (reg))1280#define ufshcd_readl(hba, reg) \1281 readl((hba)->mmio_base + (reg))1282 1283/**1284 * ufshcd_rmwl - perform read/modify/write for a controller register1285 * @hba: per adapter instance1286 * @mask: mask to apply on read value1287 * @val: actual value to write1288 * @reg: register address1289 */1290static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg)1291{1292 u32 tmp;1293 1294 tmp = ufshcd_readl(hba, reg);1295 tmp &= ~mask;1296 tmp |= (val & mask);1297 ufshcd_writel(hba, tmp, reg);1298}1299 1300void ufshcd_enable_irq(struct ufs_hba *hba);1301void ufshcd_disable_irq(struct ufs_hba *hba);1302int ufshcd_alloc_host(struct device *, struct ufs_hba **);1303void ufshcd_dealloc_host(struct ufs_hba *);1304int ufshcd_hba_enable(struct ufs_hba *hba);1305int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int);1306int ufshcd_link_recovery(struct ufs_hba *hba);1307int ufshcd_make_hba_operational(struct ufs_hba *hba);1308void ufshcd_remove(struct ufs_hba *);1309int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);1310int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);1311void ufshcd_delay_us(unsigned long us, unsigned long tolerance);1312void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk);1313void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val);1314void ufshcd_hba_stop(struct ufs_hba *hba);1315void ufshcd_schedule_eh_work(struct ufs_hba *hba);1316void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds);1317unsigned int ufshcd_mcq_queue_cfg_addr(struct ufs_hba *hba);1318u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i);1319void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i);1320unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba,1321 struct ufs_hw_queue *hwq);1322void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba);1323void ufshcd_mcq_enable_esi(struct ufs_hba *hba);1324void ufshcd_mcq_enable(struct ufs_hba *hba);1325void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg);1326 1327int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table,1328 struct dev_pm_opp *opp, void *data,1329 bool scaling_down);1330/**1331 * ufshcd_set_variant - set variant specific data to the hba1332 * @hba: per adapter instance1333 * @variant: pointer to variant specific data1334 */1335static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant)1336{1337 BUG_ON(!hba);1338 hba->priv = variant;1339}1340 1341/**1342 * ufshcd_get_variant - get variant specific data from the hba1343 * @hba: per adapter instance1344 */1345static inline void *ufshcd_get_variant(struct ufs_hba *hba)1346{1347 BUG_ON(!hba);1348 return hba->priv;1349}1350 1351#ifdef CONFIG_PM1352extern int ufshcd_runtime_suspend(struct device *dev);1353extern int ufshcd_runtime_resume(struct device *dev);1354#endif1355#ifdef CONFIG_PM_SLEEP1356extern int ufshcd_system_suspend(struct device *dev);1357extern int ufshcd_system_resume(struct device *dev);1358extern int ufshcd_system_freeze(struct device *dev);1359extern int ufshcd_system_thaw(struct device *dev);1360extern int ufshcd_system_restore(struct device *dev);1361#endif1362 1363extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba,1364 int agreed_gear,1365 int adapt_val);1366extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,1367 u8 attr_set, u32 mib_val, u8 peer);1368extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,1369 u32 *mib_val, u8 peer);1370extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,1371 struct ufs_pa_layer_attr *desired_pwr_mode);1372extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode);1373 1374/* UIC command interfaces for DME primitives */1375#define DME_LOCAL 01376#define DME_PEER 11377#define ATTR_SET_NOR 0 /* NORMAL */1378#define ATTR_SET_ST 1 /* STATIC */1379 1380static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel,1381 u32 mib_val)1382{1383 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,1384 mib_val, DME_LOCAL);1385}1386 1387static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel,1388 u32 mib_val)1389{1390 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,1391 mib_val, DME_LOCAL);1392}1393 1394static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel,1395 u32 mib_val)1396{1397 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,1398 mib_val, DME_PEER);1399}1400 1401static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel,1402 u32 mib_val)1403{1404 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,1405 mib_val, DME_PEER);1406}1407 1408static inline int ufshcd_dme_get(struct ufs_hba *hba,1409 u32 attr_sel, u32 *mib_val)1410{1411 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL);1412}1413 1414static inline int ufshcd_dme_peer_get(struct ufs_hba *hba,1415 u32 attr_sel, u32 *mib_val)1416{1417 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER);1418}1419 1420static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info)1421{1422 return (pwr_info->pwr_rx == FAST_MODE ||1423 pwr_info->pwr_rx == FASTAUTO_MODE) &&1424 (pwr_info->pwr_tx == FAST_MODE ||1425 pwr_info->pwr_tx == FASTAUTO_MODE);1426}1427 1428static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba)1429{1430 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0);1431}1432 1433void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit);1434void ufshcd_fixup_dev_quirks(struct ufs_hba *hba,1435 const struct ufs_dev_quirk *fixups);1436#define SD_ASCII_STD true1437#define SD_RAW false1438int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,1439 u8 **buf, bool ascii);1440 1441void ufshcd_hold(struct ufs_hba *hba);1442void ufshcd_release(struct ufs_hba *hba);1443 1444void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value);1445 1446int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg);1447 1448int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd);1449 1450int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu,1451 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *ehs_req,1452 struct ufs_ehs *ehs_rsp, int sg_cnt,1453 struct scatterlist *sg_list, enum dma_data_direction dir);1454int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable);1455int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable);1456int ufshcd_suspend_prepare(struct device *dev);1457int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm);1458void ufshcd_resume_complete(struct device *dev);1459bool ufshcd_is_hba_active(struct ufs_hba *hba);1460void ufshcd_pm_qos_init(struct ufs_hba *hba);1461void ufshcd_pm_qos_exit(struct ufs_hba *hba);1462 1463/* Wrapper functions for safely calling variant operations */1464static inline int ufshcd_vops_init(struct ufs_hba *hba)1465{1466 if (hba->vops && hba->vops->init)1467 return hba->vops->init(hba);1468 1469 return 0;1470}1471 1472static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba)1473{1474 if (hba->vops && hba->vops->phy_initialization)1475 return hba->vops->phy_initialization(hba);1476 1477 return 0;1478}1479 1480extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[];1481 1482int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,1483 const char *prefix);1484 1485int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask);1486int ufshcd_write_ee_control(struct ufs_hba *hba);1487int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask,1488 const u16 *other_mask, u16 set, u16 clr);1489 1490#endif /* End of Header */1491