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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Universal Flash Storage Host controller driver4 * Copyright (C) 2011-2013 Samsung India Software Operations5 *6 * Authors:7 * Santosh Yaraganavi <santosh.sy@samsung.com>8 * Vinayak Holikatti <h.vinayak@samsung.com>9 */10 11#ifndef _UFSHCI_H12#define _UFSHCI_H13 14#include <linux/types.h>15#include <ufs/ufs.h>16 17enum {18 TASK_REQ_UPIU_SIZE_DWORDS = 8,19 TASK_RSP_UPIU_SIZE_DWORDS = 8,20 ALIGNED_UPIU_SIZE = 512,21};22 23/* UFSHCI Registers */24enum {25 REG_CONTROLLER_CAPABILITIES = 0x00,26 REG_MCQCAP = 0x04,27 REG_UFS_VERSION = 0x08,28 REG_EXT_CONTROLLER_CAPABILITIES = 0x0C,29 REG_CONTROLLER_PID = 0x10,30 REG_CONTROLLER_MID = 0x14,31 REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,32 REG_INTERRUPT_STATUS = 0x20,33 REG_INTERRUPT_ENABLE = 0x24,34 REG_CONTROLLER_STATUS = 0x30,35 REG_CONTROLLER_ENABLE = 0x34,36 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,37 REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,38 REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,39 REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,40 REG_UIC_ERROR_CODE_DME = 0x48,41 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,42 REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,43 REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,44 REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,45 REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,46 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,47 REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,48 REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,49 REG_UTP_TASK_REQ_DOOR_BELL = 0x78,50 REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,51 REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,52 REG_UIC_COMMAND = 0x90,53 REG_UIC_COMMAND_ARG_1 = 0x94,54 REG_UIC_COMMAND_ARG_2 = 0x98,55 REG_UIC_COMMAND_ARG_3 = 0x9C,56 57 UFSHCI_REG_SPACE_SIZE = 0xA0,58 59 REG_UFS_CCAP = 0x100,60 REG_UFS_CRYPTOCAP = 0x104,61 62 REG_UFS_MEM_CFG = 0x300,63 REG_UFS_MCQ_CFG = 0x380,64 REG_UFS_ESILBA = 0x384,65 REG_UFS_ESIUBA = 0x388,66 UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,67};68 69/* Controller capability masks */70enum {71 MASK_TRANSFER_REQUESTS_SLOTS_SDB = 0x0000001F,72 MASK_TRANSFER_REQUESTS_SLOTS_MCQ = 0x000000FF,73 MASK_NUMBER_OUTSTANDING_RTT = 0x0000FF00,74 MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,75 MASK_EHSLUTRD_SUPPORTED = 0x00400000,76 MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,77 MASK_64_ADDRESSING_SUPPORT = 0x01000000,78 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,79 MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,80 MASK_CRYPTO_SUPPORT = 0x10000000,81 MASK_LSDB_SUPPORT = 0x20000000,82 MASK_MCQ_SUPPORT = 0x40000000,83};84 85/* MCQ capability mask */86enum {87 MASK_EXT_IID_SUPPORT = 0x00000400,88};89 90enum {91 REG_SQATTR = 0x0,92 REG_SQLBA = 0x4,93 REG_SQUBA = 0x8,94 REG_SQDAO = 0xC,95 REG_SQISAO = 0x10,96 97 REG_CQATTR = 0x20,98 REG_CQLBA = 0x24,99 REG_CQUBA = 0x28,100 REG_CQDAO = 0x2C,101 REG_CQISAO = 0x30,102};103 104enum {105 REG_SQHP = 0x0,106 REG_SQTP = 0x4,107 REG_SQRTC = 0x8,108 REG_SQCTI = 0xC,109 REG_SQRTS = 0x10,110};111 112enum {113 REG_CQHP = 0x0,114 REG_CQTP = 0x4,115};116 117enum {118 REG_CQIS = 0x0,119 REG_CQIE = 0x4,120};121 122enum {123 SQ_START = 0x0,124 SQ_STOP = 0x1,125 SQ_ICU = 0x2,126};127 128enum {129 SQ_STS = 0x1,130 SQ_CUS = 0x2,131};132 133#define SQ_ICU_ERR_CODE_MASK GENMASK(7, 4)134#define UFS_MASK(mask, offset) ((mask) << (offset))135 136/* UFS Version 08h */137#define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)138#define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)139 140#define UFSHCD_NUM_RESERVED 1141/*142 * Controller UFSHCI version143 * - 2.x and newer use the following scheme:144 * major << 8 + minor << 4145 * - 1.x has been converted to match this in146 * ufshcd_get_ufs_version()147 */148static inline u32 ufshci_version(u32 major, u32 minor)149{150 return (major << 8) + (minor << 4);151}152 153/*154 * HCDDID - Host Controller Identification Descriptor155 * - Device ID and Device Class 10h156 */157#define DEVICE_CLASS UFS_MASK(0xFFFF, 0)158#define DEVICE_ID UFS_MASK(0xFF, 24)159 160/*161 * HCPMID - Host Controller Identification Descriptor162 * - Product/Manufacturer ID 14h163 */164#define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0)165#define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16)166 167/* AHIT - Auto-Hibernate Idle Timer */168#define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0)169#define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10)170#define UFSHCI_AHIBERN8_SCALE_FACTOR 10171#define UFSHCI_AHIBERN8_MAX (1023 * 100000)172 173/*174 * IS - Interrupt Status - 20h175 */176#define UTP_TRANSFER_REQ_COMPL 0x1177#define UIC_DME_END_PT_RESET 0x2178#define UIC_ERROR 0x4179#define UIC_TEST_MODE 0x8180#define UIC_POWER_MODE 0x10181#define UIC_HIBERNATE_EXIT 0x20182#define UIC_HIBERNATE_ENTER 0x40183#define UIC_LINK_LOST 0x80184#define UIC_LINK_STARTUP 0x100185#define UTP_TASK_REQ_COMPL 0x200186#define UIC_COMMAND_COMPL 0x400187#define DEVICE_FATAL_ERROR 0x800188#define CONTROLLER_FATAL_ERROR 0x10000189#define SYSTEM_BUS_FATAL_ERROR 0x20000190#define CRYPTO_ENGINE_FATAL_ERROR 0x40000191#define MCQ_CQ_EVENT_STATUS 0x100000192 193#define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\194 UIC_HIBERNATE_EXIT)195 196#define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\197 UIC_POWER_MODE)198 199#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)200 201#define UFSHCD_ERROR_MASK (UIC_ERROR | INT_FATAL_ERRORS)202 203#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\204 CONTROLLER_FATAL_ERROR |\205 SYSTEM_BUS_FATAL_ERROR |\206 CRYPTO_ENGINE_FATAL_ERROR |\207 UIC_LINK_LOST)208 209/* HCS - Host Controller Status 30h */210#define DEVICE_PRESENT 0x1211#define UTP_TRANSFER_REQ_LIST_READY 0x2212#define UTP_TASK_REQ_LIST_READY 0x4213#define UIC_COMMAND_READY 0x8214#define HOST_ERROR_INDICATOR 0x10215#define DEVICE_ERROR_INDICATOR 0x20216#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)217 218#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\219 UTP_TASK_REQ_LIST_READY |\220 UIC_COMMAND_READY)221 222enum {223 PWR_OK = 0x0,224 PWR_LOCAL = 0x01,225 PWR_REMOTE = 0x02,226 PWR_BUSY = 0x03,227 PWR_ERROR_CAP = 0x04,228 PWR_FATAL_ERROR = 0x05,229};230 231/* HCE - Host Controller Enable 34h */232#define CONTROLLER_ENABLE 0x1233#define CONTROLLER_DISABLE 0x0234#define CRYPTO_GENERAL_ENABLE 0x2235 236/* UECPA - Host UIC Error Code PHY Adapter Layer 38h */237#define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000238#define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F239#define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF240#define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10241 242/* UECDL - Host UIC Error Code Data Link Layer 3Ch */243#define UIC_DATA_LINK_LAYER_ERROR 0x80000000244#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF245#define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2246#define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4247#define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8248#define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20249#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000250#define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001251#define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002252 253/* UECN - Host UIC Error Code Network Layer 40h */254#define UIC_NETWORK_LAYER_ERROR 0x80000000255#define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7256#define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1257#define UIC_NETWORK_BAD_DEVICEID_ENC 0x2258#define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4259 260/* UECT - Host UIC Error Code Transport Layer 44h */261#define UIC_TRANSPORT_LAYER_ERROR 0x80000000262#define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F263#define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1264#define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2265#define UIC_TRANSPORT_NO_CONNECTION_RX 0x4266#define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8267#define UIC_TRANSPORT_BAD_TC 0x10268#define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20269#define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40270 271/* UECDME - Host UIC Error Code DME 48h */272#define UIC_DME_ERROR 0x80000000273#define UIC_DME_ERROR_CODE_MASK 0x1274 275/* UTRIACR - Interrupt Aggregation control register - 0x4Ch */276#define INT_AGGR_TIMEOUT_VAL_MASK 0xFF277#define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)278#define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000279#define INT_AGGR_STATUS_BIT 0x100000280#define INT_AGGR_PARAM_WRITE 0x1000000281#define INT_AGGR_ENABLE 0x80000000282 283/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */284#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1285 286/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */287#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1288 289/* REG_UFS_MEM_CFG - Global Config Registers 300h */290#define MCQ_MODE_SELECT BIT(0)291 292/* CQISy - CQ y Interrupt Status Register */293#define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS 0x1294 295/* UICCMD - UIC Command */296#define COMMAND_OPCODE_MASK 0xFF297#define GEN_SELECTOR_INDEX_MASK 0xFFFF298 299#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)300#define RESET_LEVEL 0xFF301 302#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)303#define CONFIG_RESULT_CODE_MASK 0xFF304#define GENERIC_ERROR_CODE_MASK 0xFF305 306/* GenSelectorIndex calculation macros for M-PHY attributes */307#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)308#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))309 310#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\311 ((sel) & 0xFFFF))312#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)313#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)314#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)315 316/* Link Status*/317enum link_status {318 UFSHCD_LINK_IS_DOWN = 1,319 UFSHCD_LINK_IS_UP = 2,320};321 322/* UIC Commands */323enum uic_cmd_dme {324 UIC_CMD_DME_GET = 0x01,325 UIC_CMD_DME_SET = 0x02,326 UIC_CMD_DME_PEER_GET = 0x03,327 UIC_CMD_DME_PEER_SET = 0x04,328 UIC_CMD_DME_POWERON = 0x10,329 UIC_CMD_DME_POWEROFF = 0x11,330 UIC_CMD_DME_ENABLE = 0x12,331 UIC_CMD_DME_RESET = 0x14,332 UIC_CMD_DME_END_PT_RST = 0x15,333 UIC_CMD_DME_LINK_STARTUP = 0x16,334 UIC_CMD_DME_HIBER_ENTER = 0x17,335 UIC_CMD_DME_HIBER_EXIT = 0x18,336 UIC_CMD_DME_TEST_MODE = 0x1A,337};338 339/* UIC Config result code / Generic error code */340enum {341 UIC_CMD_RESULT_SUCCESS = 0x00,342 UIC_CMD_RESULT_INVALID_ATTR = 0x01,343 UIC_CMD_RESULT_FAILURE = 0x01,344 UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,345 UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,346 UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,347 UIC_CMD_RESULT_BAD_INDEX = 0x05,348 UIC_CMD_RESULT_LOCKED_ATTR = 0x06,349 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,350 UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,351 UIC_CMD_RESULT_BUSY = 0x09,352 UIC_CMD_RESULT_DME_FAILURE = 0x0A,353};354 355#define MASK_UIC_COMMAND_RESULT 0xFF356 357#define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8)358#define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0)359 360/* Interrupt disable masks */361enum {362 /* Interrupt disable mask for UFSHCI v1.1 */363 INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,364 365 /* Interrupt disable mask for UFSHCI v2.1 */366 INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,367};368 369/* CCAP - Crypto Capability 100h */370union ufs_crypto_capabilities {371 __le32 reg_val;372 struct {373 u8 num_crypto_cap;374 u8 config_count;375 u8 reserved;376 u8 config_array_ptr;377 };378};379 380enum ufs_crypto_key_size {381 UFS_CRYPTO_KEY_SIZE_INVALID = 0x0,382 UFS_CRYPTO_KEY_SIZE_128 = 0x1,383 UFS_CRYPTO_KEY_SIZE_192 = 0x2,384 UFS_CRYPTO_KEY_SIZE_256 = 0x3,385 UFS_CRYPTO_KEY_SIZE_512 = 0x4,386};387 388enum ufs_crypto_alg {389 UFS_CRYPTO_ALG_AES_XTS = 0x0,390 UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1,391 UFS_CRYPTO_ALG_AES_ECB = 0x2,392 UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3,393};394 395/* x-CRYPTOCAP - Crypto Capability X */396union ufs_crypto_cap_entry {397 __le32 reg_val;398 struct {399 u8 algorithm_id;400 u8 sdus_mask; /* Supported data unit size mask */401 u8 key_size;402 u8 reserved;403 };404};405 406#define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7)407#define UFS_CRYPTO_KEY_MAX_SIZE 64408/* x-CRYPTOCFG - Crypto Configuration X */409union ufs_crypto_cfg_entry {410 __le32 reg_val[32];411 struct {412 u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE];413 u8 data_unit_size;414 u8 crypto_cap_idx;415 u8 reserved_1;416 u8 config_enable;417 u8 reserved_multi_host;418 u8 reserved_2;419 u8 vsb[2];420 u8 reserved_3[56];421 };422};423 424/*425 * Request Descriptor Definitions426 */427 428/* To accommodate UFS2.0 required Command type */429enum {430 UTP_CMD_TYPE_UFS_STORAGE = 0x1,431};432 433enum {434 UTP_SCSI_COMMAND = 0x00000000,435 UTP_NATIVE_UFS_COMMAND = 0x10000000,436 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,437};438 439/* UTP Transfer Request Data Direction (DD) */440enum utp_data_direction {441 UTP_NO_DATA_TRANSFER = 0,442 UTP_HOST_TO_DEVICE = 1,443 UTP_DEVICE_TO_HOST = 2,444};445 446/* Overall command status values */447enum utp_ocs {448 OCS_SUCCESS = 0x0,449 OCS_INVALID_CMD_TABLE_ATTR = 0x1,450 OCS_INVALID_PRDT_ATTR = 0x2,451 OCS_MISMATCH_DATA_BUF_SIZE = 0x3,452 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,453 OCS_PEER_COMM_FAILURE = 0x5,454 OCS_ABORTED = 0x6,455 OCS_FATAL_ERROR = 0x7,456 OCS_DEVICE_FATAL_ERROR = 0x8,457 OCS_INVALID_CRYPTO_CONFIG = 0x9,458 OCS_GENERAL_CRYPTO_ERROR = 0xA,459 OCS_INVALID_COMMAND_STATUS = 0x0F,460};461 462enum {463 MASK_OCS = 0x0F,464};465 466/* The maximum length of the data byte count field in the PRDT is 256KB */467#define PRDT_DATA_BYTE_COUNT_MAX SZ_256K468/* The granularity of the data byte count field in the PRDT is 32-bit */469#define PRDT_DATA_BYTE_COUNT_PAD 4470 471/**472 * struct ufshcd_sg_entry - UFSHCI PRD Entry473 * @addr: Physical address; DW-0 and DW-1.474 * @reserved: Reserved for future use DW-2475 * @size: size of physical segment DW-3476 */477struct ufshcd_sg_entry {478 __le64 addr;479 __le32 reserved;480 __le32 size;481 /*482 * followed by variant-specific fields if483 * CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE has been defined.484 */485};486 487/**488 * struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD)489 * @command_upiu: Command UPIU Frame address490 * @response_upiu: Response UPIU Frame address491 * @prd_table: Physical Region Descriptor: an array of SG_ALL struct492 * ufshcd_sg_entry's. Variant-specific fields may be present after each.493 */494struct utp_transfer_cmd_desc {495 u8 command_upiu[ALIGNED_UPIU_SIZE];496 u8 response_upiu[ALIGNED_UPIU_SIZE];497 u8 prd_table[];498};499 500/**501 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD502 */503struct request_desc_header {504 u8 cci;505 u8 ehs_length;506#if defined(__BIG_ENDIAN)507 u8 enable_crypto:1;508 u8 reserved2:7;509 510 u8 command_type:4;511 u8 reserved1:1;512 u8 data_direction:2;513 u8 interrupt:1;514#elif defined(__LITTLE_ENDIAN)515 u8 reserved2:7;516 u8 enable_crypto:1;517 518 u8 interrupt:1;519 u8 data_direction:2;520 u8 reserved1:1;521 u8 command_type:4;522#else523#error524#endif525 526 __le32 dunl;527 u8 ocs;528 u8 cds;529 __le16 ldbc;530 __le32 dunu;531};532 533static_assert(sizeof(struct request_desc_header) == 16);534 535/**536 * struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD)537 * @header: UTRD header DW-0 to DW-3538 * @command_desc_base_addr: UCD base address DW 4-5539 * @response_upiu_length: response UPIU length DW-6540 * @response_upiu_offset: response UPIU offset DW-6541 * @prd_table_length: Physical region descriptor length DW-7542 * @prd_table_offset: Physical region descriptor offset DW-7543 */544struct utp_transfer_req_desc {545 546 /* DW 0-3 */547 struct request_desc_header header;548 549 /* DW 4-5*/550 __le64 command_desc_base_addr;551 552 /* DW 6 */553 __le16 response_upiu_length;554 __le16 response_upiu_offset;555 556 /* DW 7 */557 __le16 prd_table_length;558 __le16 prd_table_offset;559};560 561/* MCQ Completion Queue Entry */562struct cq_entry {563 /* DW 0-1 */564 __le64 command_desc_base_addr;565 566 /* DW 2 */567 __le16 response_upiu_length;568 __le16 response_upiu_offset;569 570 /* DW 3 */571 __le16 prd_table_length;572 __le16 prd_table_offset;573 574 /* DW 4 */575 __le32 status;576 577 /* DW 5-7 */578 __le32 reserved[3];579};580 581static_assert(sizeof(struct cq_entry) == 32);582 583/*584 * UTMRD structure.585 */586struct utp_task_req_desc {587 /* DW 0-3 */588 struct request_desc_header header;589 590 /* DW 4-11 - Task request UPIU structure */591 struct {592 struct utp_upiu_header req_header;593 __be32 input_param1;594 __be32 input_param2;595 __be32 input_param3;596 __be32 __reserved1[2];597 } upiu_req;598 599 /* DW 12-19 - Task Management Response UPIU structure */600 struct {601 struct utp_upiu_header rsp_header;602 __be32 output_param1;603 __be32 output_param2;604 __be32 __reserved2[3];605 } upiu_rsp;606};607 608#endif /* End of Header */609