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1/* SPDX-License-Identifier: GPL-2.0 */2/* $Id: aty128.h,v 1.1 1999/10/12 11:00:40 geert Exp $3 * linux/drivers/video/aty128.h4 * Register definitions for ATI Rage128 boards5 *6 * Anthony Tong <atong@uiuc.edu>, 19997 * Brad Douglas <brad@neruo.com>, 20008 */9 10#ifndef REG_RAGE128_H11#define REG_RAGE128_H12 13#define CLOCK_CNTL_INDEX 0x000814#define CLOCK_CNTL_DATA 0x000c15#define BIOS_0_SCRATCH 0x001016#define BUS_CNTL 0x003017#define BUS_CNTL1 0x003418#define GEN_INT_CNTL 0x004019#define CRTC_GEN_CNTL 0x005020#define CRTC_EXT_CNTL 0x005421#define DAC_CNTL 0x005822#define I2C_CNTL_1 0x009423#define PALETTE_INDEX 0x00b024#define PALETTE_DATA 0x00b425#define CNFG_CNTL 0x00e026#define GEN_RESET_CNTL 0x00f027#define CNFG_MEMSIZE 0x00f828#define MEM_CNTL 0x014029#define MEM_POWER_MISC 0x015c30#define AGP_BASE 0x017031#define AGP_CNTL 0x017432#define AGP_APER_OFFSET 0x017833#define PCI_GART_PAGE 0x017c34#define PC_NGUI_MODE 0x018035#define PC_NGUI_CTLSTAT 0x018436#define MPP_TB_CONFIG 0x01C037#define MPP_GP_CONFIG 0x01C838#define VIPH_CONTROL 0x01D039#define CRTC_H_TOTAL_DISP 0x020040#define CRTC_H_SYNC_STRT_WID 0x020441#define CRTC_V_TOTAL_DISP 0x020842#define CRTC_V_SYNC_STRT_WID 0x020c43#define CRTC_VLINE_CRNT_VLINE 0x021044#define CRTC_CRNT_FRAME 0x021445#define CRTC_GUI_TRIG_VLINE 0x021846#define CRTC_OFFSET 0x022447#define CRTC_OFFSET_CNTL 0x022848#define CRTC_PITCH 0x022c49#define OVR_CLR 0x023050#define OVR_WID_LEFT_RIGHT 0x023451#define OVR_WID_TOP_BOTTOM 0x023852#define LVDS_GEN_CNTL 0x02d053#define DDA_CONFIG 0x02e054#define DDA_ON_OFF 0x02e455#define VGA_DDA_CONFIG 0x02e856#define VGA_DDA_ON_OFF 0x02ec57#define CRTC2_H_TOTAL_DISP 0x030058#define CRTC2_H_SYNC_STRT_WID 0x030459#define CRTC2_V_TOTAL_DISP 0x030860#define CRTC2_V_SYNC_STRT_WID 0x030c61#define CRTC2_VLINE_CRNT_VLINE 0x031062#define CRTC2_CRNT_FRAME 0x031463#define CRTC2_GUI_TRIG_VLINE 0x031864#define CRTC2_OFFSET 0x032465#define CRTC2_OFFSET_CNTL 0x032866#define CRTC2_PITCH 0x032c67#define DDA2_CONFIG 0x03e068#define DDA2_ON_OFF 0x03e469#define CRTC2_GEN_CNTL 0x03f870#define CRTC2_STATUS 0x03fc71#define OV0_SCALE_CNTL 0x042072#define SUBPIC_CNTL 0x054073#define PM4_BUFFER_OFFSET 0x070074#define PM4_BUFFER_CNTL 0x070475#define PM4_BUFFER_WM_CNTL 0x070876#define PM4_BUFFER_DL_RPTR_ADDR 0x070c77#define PM4_BUFFER_DL_RPTR 0x071078#define PM4_BUFFER_DL_WPTR 0x071479#define PM4_VC_FPU_SETUP 0x071c80#define PM4_FPU_CNTL 0x072081#define PM4_VC_FORMAT 0x072482#define PM4_VC_CNTL 0x072883#define PM4_VC_I01 0x072c84#define PM4_VC_VLOFF 0x073085#define PM4_VC_VLSIZE 0x073486#define PM4_IW_INDOFF 0x073887#define PM4_IW_INDSIZE 0x073c88#define PM4_FPU_FPX0 0x074089#define PM4_FPU_FPY0 0x074490#define PM4_FPU_FPX1 0x074891#define PM4_FPU_FPY1 0x074c92#define PM4_FPU_FPX2 0x075093#define PM4_FPU_FPY2 0x075494#define PM4_FPU_FPY3 0x075895#define PM4_FPU_FPY4 0x075c96#define PM4_FPU_FPY5 0x076097#define PM4_FPU_FPY6 0x076498#define PM4_FPU_FPR 0x076899#define PM4_FPU_FPG 0x076c100#define PM4_FPU_FPB 0x0770101#define PM4_FPU_FPA 0x0774102#define PM4_FPU_INTXY0 0x0780103#define PM4_FPU_INTXY1 0x0784104#define PM4_FPU_INTXY2 0x0788105#define PM4_FPU_INTARGB 0x078c106#define PM4_FPU_FPTWICEAREA 0x0790107#define PM4_FPU_DMAJOR01 0x0794108#define PM4_FPU_DMAJOR12 0x0798109#define PM4_FPU_DMAJOR02 0x079c110#define PM4_FPU_STAT 0x07a0111#define PM4_STAT 0x07b8112#define PM4_TEST_CNTL 0x07d0113#define PM4_MICROCODE_ADDR 0x07d4114#define PM4_MICROCODE_RADDR 0x07d8115#define PM4_MICROCODE_DATAH 0x07dc116#define PM4_MICROCODE_DATAL 0x07e0117#define PM4_CMDFIFO_ADDR 0x07e4118#define PM4_CMDFIFO_DATAH 0x07e8119#define PM4_CMDFIFO_DATAL 0x07ec120#define PM4_BUFFER_ADDR 0x07f0121#define PM4_BUFFER_DATAH 0x07f4122#define PM4_BUFFER_DATAL 0x07f8123#define PM4_MICRO_CNTL 0x07fc124#define CAP0_TRIG_CNTL 0x0950125#define CAP1_TRIG_CNTL 0x09c0126 127/******************************************************************************128 * GUI Block Memory Mapped Registers *129 * These registers are FIFOed. *130 *****************************************************************************/131#define PM4_FIFO_DATA_EVEN 0x1000132#define PM4_FIFO_DATA_ODD 0x1004133 134#define DST_OFFSET 0x1404135#define DST_PITCH 0x1408136#define DST_WIDTH 0x140c137#define DST_HEIGHT 0x1410138#define SRC_X 0x1414139#define SRC_Y 0x1418140#define DST_X 0x141c141#define DST_Y 0x1420142#define SRC_PITCH_OFFSET 0x1428143#define DST_PITCH_OFFSET 0x142c144#define SRC_Y_X 0x1434145#define DST_Y_X 0x1438146#define DST_HEIGHT_WIDTH 0x143c147#define DP_GUI_MASTER_CNTL 0x146c148#define BRUSH_SCALE 0x1470149#define BRUSH_Y_X 0x1474150#define DP_BRUSH_BKGD_CLR 0x1478151#define DP_BRUSH_FRGD_CLR 0x147c152#define DST_WIDTH_X 0x1588153#define DST_HEIGHT_WIDTH_8 0x158c154#define SRC_X_Y 0x1590155#define DST_X_Y 0x1594156#define DST_WIDTH_HEIGHT 0x1598157#define DST_WIDTH_X_INCY 0x159c158#define DST_HEIGHT_Y 0x15a0159#define DST_X_SUB 0x15a4160#define DST_Y_SUB 0x15a8161#define SRC_OFFSET 0x15ac162#define SRC_PITCH 0x15b0163#define DST_HEIGHT_WIDTH_BW 0x15b4164#define CLR_CMP_CNTL 0x15c0165#define CLR_CMP_CLR_SRC 0x15c4166#define CLR_CMP_CLR_DST 0x15c8167#define CLR_CMP_MASK 0x15cc168#define DP_SRC_FRGD_CLR 0x15d8169#define DP_SRC_BKGD_CLR 0x15dc170#define DST_BRES_ERR 0x1628171#define DST_BRES_INC 0x162c172#define DST_BRES_DEC 0x1630173#define DST_BRES_LNTH 0x1634174#define DST_BRES_LNTH_SUB 0x1638175#define SC_LEFT 0x1640176#define SC_RIGHT 0x1644177#define SC_TOP 0x1648178#define SC_BOTTOM 0x164c179#define SRC_SC_RIGHT 0x1654180#define SRC_SC_BOTTOM 0x165c181#define GUI_DEBUG0 0x16a0182#define GUI_DEBUG1 0x16a4183#define GUI_TIMEOUT 0x16b0184#define GUI_TIMEOUT0 0x16b4185#define GUI_TIMEOUT1 0x16b8186#define GUI_PROBE 0x16bc187#define DP_CNTL 0x16c0188#define DP_DATATYPE 0x16c4189#define DP_MIX 0x16c8190#define DP_WRITE_MASK 0x16cc191#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0192#define DEFAULT_OFFSET 0x16e0193#define DEFAULT_PITCH 0x16e4194#define DEFAULT_SC_BOTTOM_RIGHT 0x16e8195#define SC_TOP_LEFT 0x16ec196#define SC_BOTTOM_RIGHT 0x16f0197#define SRC_SC_BOTTOM_RIGHT 0x16f4198#define WAIT_UNTIL 0x1720199#define CACHE_CNTL 0x1724200#define GUI_STAT 0x1740201#define PC_GUI_MODE 0x1744202#define PC_GUI_CTLSTAT 0x1748203#define PC_DEBUG_MODE 0x1760204#define BRES_DST_ERR_DEC 0x1780205#define TRAIL_BRES_T12_ERR_DEC 0x1784206#define TRAIL_BRES_T12_INC 0x1788207#define DP_T12_CNTL 0x178c208#define DST_BRES_T1_LNTH 0x1790209#define DST_BRES_T2_LNTH 0x1794210#define SCALE_SRC_HEIGHT_WIDTH 0x1994211#define SCALE_OFFSET_0 0x1998212#define SCALE_PITCH 0x199c213#define SCALE_X_INC 0x19a0214#define SCALE_Y_INC 0x19a4215#define SCALE_HACC 0x19a8216#define SCALE_VACC 0x19ac217#define SCALE_DST_X_Y 0x19b0218#define SCALE_DST_HEIGHT_WIDTH 0x19b4219#define SCALE_3D_CNTL 0x1a00220#define SCALE_3D_DATATYPE 0x1a20221#define SETUP_CNTL 0x1bc4222#define SOLID_COLOR 0x1bc8223#define WINDOW_XY_OFFSET 0x1bcc224#define DRAW_LINE_POINT 0x1bd0225#define SETUP_CNTL_PM4 0x1bd4226#define DST_PITCH_OFFSET_C 0x1c80227#define DP_GUI_MASTER_CNTL_C 0x1c84228#define SC_TOP_LEFT_C 0x1c88229#define SC_BOTTOM_RIGHT_C 0x1c8c230 231#define CLR_CMP_MASK_3D 0x1A28232#define MISC_3D_STATE_CNTL_REG 0x1CA0233#define MC_SRC1_CNTL 0x19D8234#define TEX_CNTL 0x1800235 236/* CONSTANTS */237#define GUI_ACTIVE 0x80000000238#define ENGINE_IDLE 0x0239 240#define PLL_WR_EN 0x00000080241 242#define CLK_PIN_CNTL 0x0001243#define PPLL_CNTL 0x0002244#define PPLL_REF_DIV 0x0003245#define PPLL_DIV_0 0x0004246#define PPLL_DIV_1 0x0005247#define PPLL_DIV_2 0x0006248#define PPLL_DIV_3 0x0007249#define VCLK_ECP_CNTL 0x0008250#define HTOTAL_CNTL 0x0009251#define X_MPLL_REF_FB_DIV 0x000a252#define XPLL_CNTL 0x000b253#define XDLL_CNTL 0x000c254#define XCLK_CNTL 0x000d255#define MPLL_CNTL 0x000e256#define MCLK_CNTL 0x000f257#define AGP_PLL_CNTL 0x0010258#define FCP_CNTL 0x0012259#define PLL_TEST_CNTL 0x0013260#define P2PLL_CNTL 0x002a261#define P2PLL_REF_DIV 0x002b262#define P2PLL_DIV_0 0x002b263#define POWER_MANAGEMENT 0x002f264 265#define PPLL_RESET 0x01266#define PPLL_ATOMIC_UPDATE_EN 0x10000267#define PPLL_VGA_ATOMIC_UPDATE_EN 0x20000268#define PPLL_REF_DIV_MASK 0x3FF269#define PPLL_FB3_DIV_MASK 0x7FF270#define PPLL_POST3_DIV_MASK 0x70000271#define PPLL_ATOMIC_UPDATE_R 0x8000272#define PPLL_ATOMIC_UPDATE_W 0x8000273#define MEM_CFG_TYPE_MASK 0x3274#define XCLK_SRC_SEL_MASK 0x7275#define XPLL_FB_DIV_MASK 0xFF00276#define X_MPLL_REF_DIV_MASK 0xFF277 278/* CRTC control values (CRTC_GEN_CNTL) */279#define CRTC_CSYNC_EN 0x00000010280 281#define CRTC2_DBL_SCAN_EN 0x00000001282#define CRTC2_DISPLAY_DIS 0x00800000283#define CRTC2_FIFO_EXTSENSE 0x00200000284#define CRTC2_ICON_EN 0x00100000285#define CRTC2_CUR_EN 0x00010000286#define CRTC2_EN 0x02000000287#define CRTC2_DISP_REQ_EN_B 0x04000000288 289#define CRTC_PIX_WIDTH_MASK 0x00000700290#define CRTC_PIX_WIDTH_4BPP 0x00000100291#define CRTC_PIX_WIDTH_8BPP 0x00000200292#define CRTC_PIX_WIDTH_15BPP 0x00000300293#define CRTC_PIX_WIDTH_16BPP 0x00000400294#define CRTC_PIX_WIDTH_24BPP 0x00000500295#define CRTC_PIX_WIDTH_32BPP 0x00000600296 297/* DAC_CNTL bit constants */298#define DAC_8BIT_EN 0x00000100299#define DAC_MASK 0xFF000000300#define DAC_BLANKING 0x00000004301#define DAC_RANGE_CNTL 0x00000003302#define DAC_CLK_SEL 0x00000010303#define DAC_PALETTE_ACCESS_CNTL 0x00000020304#define DAC_PALETTE2_SNOOP_EN 0x00000040305#define DAC_PDWN 0x00008000306 307/* CRTC_EXT_CNTL */308#define CRT_CRTC_ON 0x00008000309 310/* GEN_RESET_CNTL bit constants */311#define SOFT_RESET_GUI 0x00000001312#define SOFT_RESET_VCLK 0x00000100313#define SOFT_RESET_PCLK 0x00000200314#define SOFT_RESET_ECP 0x00000400315#define SOFT_RESET_DISPENG_XCLK 0x00000800316 317/* PC_GUI_CTLSTAT bit constants */318#define PC_BUSY_INIT 0x10000000319#define PC_BUSY_GUI 0x20000000320#define PC_BUSY_NGUI 0x40000000321#define PC_BUSY 0x80000000322 323#define BUS_MASTER_DIS 0x00000040324#define PM4_BUFFER_CNTL_NONPM4 0x00000000325 326/* DP_DATATYPE bit constants */327#define DST_8BPP 0x00000002328#define DST_15BPP 0x00000003329#define DST_16BPP 0x00000004330#define DST_24BPP 0x00000005331#define DST_32BPP 0x00000006332 333#define BRUSH_SOLIDCOLOR 0x00000d00334 335/* DP_GUI_MASTER_CNTL bit constants */336#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000337#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000338#define GMC_SRC_CLIP_DEFAULT 0x00000000339#define GMC_DST_CLIP_DEFAULT 0x00000000340#define GMC_BRUSH_SOLIDCOLOR 0x000000d0341#define GMC_SRC_DSTCOLOR 0x00003000342#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000343#define GMC_DP_SRC_RECT 0x02000000344#define GMC_3D_FCN_EN_CLR 0x00000000345#define GMC_AUX_CLIP_CLEAR 0x20000000346#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000347#define GMC_WRITE_MASK_SET 0x40000000348#define GMC_DP_CONVERSION_TEMP_6500 0x00000000349 350/* DP_GUI_MASTER_CNTL ROP3 named constants */351#define ROP3_PATCOPY 0x00f00000352#define ROP3_SRCCOPY 0x00cc0000353 354#define SRC_DSTCOLOR 0x00030000355 356/* DP_CNTL bit constants */357#define DST_X_RIGHT_TO_LEFT 0x00000000358#define DST_X_LEFT_TO_RIGHT 0x00000001359#define DST_Y_BOTTOM_TO_TOP 0x00000000360#define DST_Y_TOP_TO_BOTTOM 0x00000002361#define DST_X_MAJOR 0x00000000362#define DST_Y_MAJOR 0x00000004363#define DST_X_TILE 0x00000008364#define DST_Y_TILE 0x00000010365#define DST_LAST_PEL 0x00000020366#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000367#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040368#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000369#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080370#define DST_BRES_SIGN 0x00000100371#define DST_HOST_BIG_ENDIAN_EN 0x00000200372#define DST_POLYLINE_NONLAST 0x00008000373#define DST_RASTER_STALL 0x00010000374#define DST_POLY_EDGE 0x00040000375 376/* DP_MIX bit constants */377#define DP_SRC_RECT 0x00000200378#define DP_SRC_HOST 0x00000300379#define DP_SRC_HOST_BYTEALIGN 0x00000400380 381/* LVDS_GEN_CNTL constants */382#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00383#define LVDS_BL_MOD_LEVEL_SHIFT 8384#define LVDS_BL_MOD_EN 0x00010000385#define LVDS_DIGION 0x00040000386#define LVDS_BLON 0x00080000387#define LVDS_ON 0x00000001388#define LVDS_DISPLAY_DIS 0x00000002389#define LVDS_PANEL_TYPE_2PIX_PER_CLK 0x00000004390#define LVDS_PANEL_24BITS_TFT 0x00000008391#define LVDS_FRAME_MOD_NO 0x00000000392#define LVDS_FRAME_MOD_2_LEVELS 0x00000010393#define LVDS_FRAME_MOD_4_LEVELS 0x00000020394#define LVDS_RST_FM 0x00000040395#define LVDS_EN 0x00000080396 397/* CRTC2_GEN_CNTL constants */398#define CRTC2_EN 0x02000000399 400/* POWER_MANAGEMENT constants */401#define PWR_MGT_ON 0x00000001402#define PWR_MGT_MODE_MASK 0x00000006403#define PWR_MGT_MODE_PIN 0x00000000404#define PWR_MGT_MODE_REGISTER 0x00000002405#define PWR_MGT_MODE_TIMER 0x00000004406#define PWR_MGT_MODE_PCI 0x00000006407#define PWR_MGT_AUTO_PWR_UP_EN 0x00000008408#define PWR_MGT_ACTIVITY_PIN_ON 0x00000010409#define PWR_MGT_STANDBY_POL 0x00000020410#define PWR_MGT_SUSPEND_POL 0x00000040411#define PWR_MGT_SELF_REFRESH 0x00000080412#define PWR_MGT_ACTIVITY_PIN_EN 0x00000100413#define PWR_MGT_KEYBD_SNOOP 0x00000200414#define PWR_MGT_TRISTATE_MEM_EN 0x00000800415#define PWR_MGT_SELW4MS 0x00001000416#define PWR_MGT_SLOWDOWN_MCLK 0x00002000417 418#define PMI_PMSCR_REG 0x60419 420/* used by ATI bug fix for hardware ROM */421#define RAGE128_MPP_TB_CONFIG 0x01c0422 423#endif /* REG_RAGE128_H */424