1995 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef _RADEON_H3#define _RADEON_H4 5 6#define RADEON_REGSIZE 0x40007 8 9#define MM_INDEX 0x000010#define MM_DATA 0x000411#define BUS_CNTL 0x003012#define HI_STAT 0x004C13#define BUS_CNTL1 0x003414#define I2C_CNTL_1 0x009415#define CNFG_CNTL 0x00E016#define CNFG_MEMSIZE 0x00F817#define CNFG_APER_0_BASE 0x010018#define CNFG_APER_1_BASE 0x010419#define CNFG_APER_SIZE 0x010820#define CNFG_REG_1_BASE 0x010C21#define CNFG_REG_APER_SIZE 0x011022#define PAD_AGPINPUT_DELAY 0x016423#define PAD_CTLR_STRENGTH 0x016824#define PAD_CTLR_UPDATE 0x016C25#define PAD_CTLR_MISC 0x0aa026#define AGP_CNTL 0x017427#define BM_STATUS 0x016028#define CAP0_TRIG_CNTL 0x095029#define CAP1_TRIG_CNTL 0x09c030#define VIPH_CONTROL 0x0C4031#define VENDOR_ID 0x0F0032#define DEVICE_ID 0x0F0233#define COMMAND 0x0F0434#define STATUS 0x0F0635#define REVISION_ID 0x0F0836#define REGPROG_INF 0x0F0937#define SUB_CLASS 0x0F0A38#define BASE_CODE 0x0F0B39#define CACHE_LINE 0x0F0C40#define LATENCY 0x0F0D41#define HEADER 0x0F0E42#define BIST 0x0F0F43#define REG_MEM_BASE 0x0F1044#define REG_IO_BASE 0x0F1445#define REG_REG_BASE 0x0F1846#define ADAPTER_ID 0x0F2C47#define BIOS_ROM 0x0F3048#define CAPABILITIES_PTR 0x0F3449#define INTERRUPT_LINE 0x0F3C50#define INTERRUPT_PIN 0x0F3D51#define MIN_GRANT 0x0F3E52#define MAX_LATENCY 0x0F3F53#define ADAPTER_ID_W 0x0F4C54#define PMI_CAP_ID 0x0F5055#define PMI_NXT_CAP_PTR 0x0F5156#define PMI_PMC_REG 0x0F5257#define PM_STATUS 0x0F5458#define PMI_DATA 0x0F5759#define AGP_CAP_ID 0x0F5860#define AGP_STATUS 0x0F5C61#define AGP_COMMAND 0x0F6062#define AIC_CTRL 0x01D063#define AIC_STAT 0x01D464#define AIC_PT_BASE 0x01D865#define AIC_LO_ADDR 0x01DC66#define AIC_HI_ADDR 0x01E067#define AIC_TLB_ADDR 0x01E468#define AIC_TLB_DATA 0x01E869#define DAC_CNTL 0x005870#define DAC_CNTL2 0x007c71#define CRTC_GEN_CNTL 0x005072#define MEM_CNTL 0x014073#define MC_CNTL 0x014074#define EXT_MEM_CNTL 0x014475#define MC_TIMING_CNTL 0x014476#define MC_AGP_LOCATION 0x014C77#define MEM_IO_CNTL_A0 0x017878#define MEM_REFRESH_CNTL 0x017879#define MEM_INIT_LATENCY_TIMER 0x015480#define MC_INIT_GFX_LAT_TIMER 0x015481#define MEM_SDRAM_MODE_REG 0x015882#define AGP_BASE 0x017083#define MEM_IO_CNTL_A1 0x017C84#define MC_READ_CNTL_AB 0x017C85#define MEM_IO_CNTL_B0 0x018086#define MC_INIT_MISC_LAT_TIMER 0x018087#define MEM_IO_CNTL_B1 0x018488#define MC_IOPAD_CNTL 0x018489#define MC_DEBUG 0x018890#define MC_STATUS 0x015091#define MEM_IO_OE_CNTL 0x018C92#define MC_CHIP_IO_OE_CNTL_AB 0x018C93#define MC_FB_LOCATION 0x014894#define HOST_PATH_CNTL 0x013095#define MEM_VGA_WP_SEL 0x003896#define MEM_VGA_RP_SEL 0x003C97#define HDP_DEBUG 0x013898#define SW_SEMAPHORE 0x013C99#define CRTC2_GEN_CNTL 0x03f8100#define CRTC2_DISPLAY_BASE_ADDR 0x033c101#define SURFACE_CNTL 0x0B00102#define SURFACE0_LOWER_BOUND 0x0B04103#define SURFACE1_LOWER_BOUND 0x0B14104#define SURFACE2_LOWER_BOUND 0x0B24105#define SURFACE3_LOWER_BOUND 0x0B34106#define SURFACE4_LOWER_BOUND 0x0B44107#define SURFACE5_LOWER_BOUND 0x0B54108#define SURFACE6_LOWER_BOUND 0x0B64109#define SURFACE7_LOWER_BOUND 0x0B74110#define SURFACE0_UPPER_BOUND 0x0B08111#define SURFACE1_UPPER_BOUND 0x0B18112#define SURFACE2_UPPER_BOUND 0x0B28113#define SURFACE3_UPPER_BOUND 0x0B38114#define SURFACE4_UPPER_BOUND 0x0B48115#define SURFACE5_UPPER_BOUND 0x0B58116#define SURFACE6_UPPER_BOUND 0x0B68117#define SURFACE7_UPPER_BOUND 0x0B78118#define SURFACE0_INFO 0x0B0C119#define SURFACE1_INFO 0x0B1C120#define SURFACE2_INFO 0x0B2C121#define SURFACE3_INFO 0x0B3C122#define SURFACE4_INFO 0x0B4C123#define SURFACE5_INFO 0x0B5C124#define SURFACE6_INFO 0x0B6C125#define SURFACE7_INFO 0x0B7C126#define SURFACE_ACCESS_FLAGS 0x0BF8127#define SURFACE_ACCESS_CLR 0x0BFC128#define GEN_INT_CNTL 0x0040129#define GEN_INT_STATUS 0x0044130#define CRTC_EXT_CNTL 0x0054131#define RB3D_CNTL 0x1C3C132#define WAIT_UNTIL 0x1720133#define ISYNC_CNTL 0x1724134#define RBBM_GUICNTL 0x172C135#define RBBM_STATUS 0x0E40136#define RBBM_STATUS_alt_1 0x1740137#define RBBM_CNTL 0x00EC138#define RBBM_CNTL_alt_1 0x0E44139#define RBBM_SOFT_RESET 0x00F0140#define RBBM_SOFT_RESET_alt_1 0x0E48141#define NQWAIT_UNTIL 0x0E50142#define RBBM_DEBUG 0x0E6C143#define RBBM_CMDFIFO_ADDR 0x0E70144#define RBBM_CMDFIFO_DATAL 0x0E74145#define RBBM_CMDFIFO_DATAH 0x0E78146#define RBBM_CMDFIFO_STAT 0x0E7C147#define CRTC_STATUS 0x005C148#define GPIO_VGA_DDC 0x0060149#define GPIO_DVI_DDC 0x0064150#define GPIO_MONID 0x0068151#define GPIO_CRT2_DDC 0x006c152#define PALETTE_INDEX 0x00B0153#define PALETTE_DATA 0x00B4154#define PALETTE_30_DATA 0x00B8155#define CRTC_H_TOTAL_DISP 0x0200156#define CRTC_H_SYNC_STRT_WID 0x0204157#define CRTC_V_TOTAL_DISP 0x0208158#define CRTC_V_SYNC_STRT_WID 0x020C159#define CRTC_VLINE_CRNT_VLINE 0x0210160#define CRTC_CRNT_FRAME 0x0214161#define CRTC_GUI_TRIG_VLINE 0x0218162#define CRTC_DEBUG 0x021C163#define CRTC_OFFSET_RIGHT 0x0220164#define CRTC_OFFSET 0x0224165#define CRTC_OFFSET_CNTL 0x0228166#define CRTC_PITCH 0x022C167#define OVR_CLR 0x0230168#define OVR_WID_LEFT_RIGHT 0x0234169#define OVR_WID_TOP_BOTTOM 0x0238170#define DISPLAY_BASE_ADDR 0x023C171#define SNAPSHOT_VH_COUNTS 0x0240172#define SNAPSHOT_F_COUNT 0x0244173#define N_VIF_COUNT 0x0248174#define SNAPSHOT_VIF_COUNT 0x024C175#define FP_CRTC_H_TOTAL_DISP 0x0250176#define FP_CRTC_V_TOTAL_DISP 0x0254177#define CRT_CRTC_H_SYNC_STRT_WID 0x0258178#define CRT_CRTC_V_SYNC_STRT_WID 0x025C179#define CUR_OFFSET 0x0260180#define CUR_HORZ_VERT_POSN 0x0264181#define CUR_HORZ_VERT_OFF 0x0268182#define CUR_CLR0 0x026C183#define CUR_CLR1 0x0270184#define FP_HORZ_VERT_ACTIVE 0x0278185#define CRTC_MORE_CNTL 0x027C186#define CRTC_H_CUTOFF_ACTIVE_EN (1<<4)187#define CRTC_V_CUTOFF_ACTIVE_EN (1<<5)188#define DAC_EXT_CNTL 0x0280189#define FP_GEN_CNTL 0x0284190#define FP_HORZ_STRETCH 0x028C191#define FP_VERT_STRETCH 0x0290192#define FP_H_SYNC_STRT_WID 0x02C4193#define FP_V_SYNC_STRT_WID 0x02C8194#define AUX_WINDOW_HORZ_CNTL 0x02D8195#define AUX_WINDOW_VERT_CNTL 0x02DC196//#define DDA_CONFIG 0x02e0197//#define DDA_ON_OFF 0x02e4198#define DVI_I2C_CNTL_1 0x02e4199#define GRPH_BUFFER_CNTL 0x02F0200#define GRPH2_BUFFER_CNTL 0x03F0201#define VGA_BUFFER_CNTL 0x02F4202#define OV0_Y_X_START 0x0400203#define OV0_Y_X_END 0x0404204#define OV0_PIPELINE_CNTL 0x0408205#define OV0_REG_LOAD_CNTL 0x0410206#define OV0_SCALE_CNTL 0x0420207#define OV0_V_INC 0x0424208#define OV0_P1_V_ACCUM_INIT 0x0428209#define OV0_P23_V_ACCUM_INIT 0x042C210#define OV0_P1_BLANK_LINES_AT_TOP 0x0430211#define OV0_P23_BLANK_LINES_AT_TOP 0x0434212#define OV0_BASE_ADDR 0x043C213#define OV0_VID_BUF0_BASE_ADRS 0x0440214#define OV0_VID_BUF1_BASE_ADRS 0x0444215#define OV0_VID_BUF2_BASE_ADRS 0x0448216#define OV0_VID_BUF3_BASE_ADRS 0x044C217#define OV0_VID_BUF4_BASE_ADRS 0x0450218#define OV0_VID_BUF5_BASE_ADRS 0x0454219#define OV0_VID_BUF_PITCH0_VALUE 0x0460220#define OV0_VID_BUF_PITCH1_VALUE 0x0464221#define OV0_AUTO_FLIP_CNTRL 0x0470222#define OV0_DEINTERLACE_PATTERN 0x0474223#define OV0_SUBMIT_HISTORY 0x0478224#define OV0_H_INC 0x0480225#define OV0_STEP_BY 0x0484226#define OV0_P1_H_ACCUM_INIT 0x0488227#define OV0_P23_H_ACCUM_INIT 0x048C228#define OV0_P1_X_START_END 0x0494229#define OV0_P2_X_START_END 0x0498230#define OV0_P3_X_START_END 0x049C231#define OV0_FILTER_CNTL 0x04A0232#define OV0_FOUR_TAP_COEF_0 0x04B0233#define OV0_FOUR_TAP_COEF_1 0x04B4234#define OV0_FOUR_TAP_COEF_2 0x04B8235#define OV0_FOUR_TAP_COEF_3 0x04BC236#define OV0_FOUR_TAP_COEF_4 0x04C0237#define OV0_FLAG_CNTRL 0x04DC238#define OV0_SLICE_CNTL 0x04E0239#define OV0_VID_KEY_CLR_LOW 0x04E4240#define OV0_VID_KEY_CLR_HIGH 0x04E8241#define OV0_GRPH_KEY_CLR_LOW 0x04EC242#define OV0_GRPH_KEY_CLR_HIGH 0x04F0243#define OV0_KEY_CNTL 0x04F4244#define OV0_TEST 0x04F8245#define SUBPIC_CNTL 0x0540246#define SUBPIC_DEFCOLCON 0x0544247#define SUBPIC_Y_X_START 0x054C248#define SUBPIC_Y_X_END 0x0550249#define SUBPIC_V_INC 0x0554250#define SUBPIC_H_INC 0x0558251#define SUBPIC_BUF0_OFFSET 0x055C252#define SUBPIC_BUF1_OFFSET 0x0560253#define SUBPIC_LC0_OFFSET 0x0564254#define SUBPIC_LC1_OFFSET 0x0568255#define SUBPIC_PITCH 0x056C256#define SUBPIC_BTN_HLI_COLCON 0x0570257#define SUBPIC_BTN_HLI_Y_X_START 0x0574258#define SUBPIC_BTN_HLI_Y_X_END 0x0578259#define SUBPIC_PALETTE_INDEX 0x057C260#define SUBPIC_PALETTE_DATA 0x0580261#define SUBPIC_H_ACCUM_INIT 0x0584262#define SUBPIC_V_ACCUM_INIT 0x0588263#define DISP_MISC_CNTL 0x0D00264#define DAC_MACRO_CNTL 0x0D04265#define DISP_PWR_MAN 0x0D08266#define DISP_TEST_DEBUG_CNTL 0x0D10267#define DISP_HW_DEBUG 0x0D14268#define DAC_CRC_SIG1 0x0D18269#define DAC_CRC_SIG2 0x0D1C270#define OV0_LIN_TRANS_A 0x0D20271#define OV0_LIN_TRANS_B 0x0D24272#define OV0_LIN_TRANS_C 0x0D28273#define OV0_LIN_TRANS_D 0x0D2C274#define OV0_LIN_TRANS_E 0x0D30275#define OV0_LIN_TRANS_F 0x0D34276#define OV0_GAMMA_0_F 0x0D40277#define OV0_GAMMA_10_1F 0x0D44278#define OV0_GAMMA_20_3F 0x0D48279#define OV0_GAMMA_40_7F 0x0D4C280#define OV0_GAMMA_380_3BF 0x0D50281#define OV0_GAMMA_3C0_3FF 0x0D54282#define DISP_MERGE_CNTL 0x0D60283#define DISP_OUTPUT_CNTL 0x0D64284#define DISP_LIN_TRANS_GRPH_A 0x0D80285#define DISP_LIN_TRANS_GRPH_B 0x0D84286#define DISP_LIN_TRANS_GRPH_C 0x0D88287#define DISP_LIN_TRANS_GRPH_D 0x0D8C288#define DISP_LIN_TRANS_GRPH_E 0x0D90289#define DISP_LIN_TRANS_GRPH_F 0x0D94290#define DISP_LIN_TRANS_VID_A 0x0D98291#define DISP_LIN_TRANS_VID_B 0x0D9C292#define DISP_LIN_TRANS_VID_C 0x0DA0293#define DISP_LIN_TRANS_VID_D 0x0DA4294#define DISP_LIN_TRANS_VID_E 0x0DA8295#define DISP_LIN_TRANS_VID_F 0x0DAC296#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0297#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4298#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8299#define RMX_HORZ_PHASE 0x0DBC300#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0301#define DAC_BROAD_PULSE 0x0DC4302#define DAC_SKEW_CLKS 0x0DC8303#define DAC_INCR 0x0DCC304#define DAC_NEG_SYNC_LEVEL 0x0DD0305#define DAC_POS_SYNC_LEVEL 0x0DD4306#define DAC_BLANK_LEVEL 0x0DD8307#define CLOCK_CNTL_INDEX 0x0008308#define CLOCK_CNTL_DATA 0x000C309#define CP_RB_CNTL 0x0704310#define CP_RB_BASE 0x0700311#define CP_RB_RPTR_ADDR 0x070C312#define CP_RB_RPTR 0x0710313#define CP_RB_WPTR 0x0714314#define CP_RB_WPTR_DELAY 0x0718315#define CP_IB_BASE 0x0738316#define CP_IB_BUFSZ 0x073C317#define SCRATCH_REG0 0x15E0318#define GUI_SCRATCH_REG0 0x15E0319#define SCRATCH_REG1 0x15E4320#define GUI_SCRATCH_REG1 0x15E4321#define SCRATCH_REG2 0x15E8322#define GUI_SCRATCH_REG2 0x15E8323#define SCRATCH_REG3 0x15EC324#define GUI_SCRATCH_REG3 0x15EC325#define SCRATCH_REG4 0x15F0326#define GUI_SCRATCH_REG4 0x15F0327#define SCRATCH_REG5 0x15F4328#define GUI_SCRATCH_REG5 0x15F4329#define SCRATCH_UMSK 0x0770330#define SCRATCH_ADDR 0x0774331#define DP_BRUSH_FRGD_CLR 0x147C332#define DP_BRUSH_BKGD_CLR 0x1478333#define DST_LINE_START 0x1600334#define DST_LINE_END 0x1604335#define SRC_OFFSET 0x15AC336#define SRC_PITCH 0x15B0337#define SRC_TILE 0x1704338#define SRC_PITCH_OFFSET 0x1428339#define SRC_X 0x1414340#define SRC_Y 0x1418341#define SRC_X_Y 0x1590342#define SRC_Y_X 0x1434343#define DST_Y_X 0x1438344#define DST_WIDTH_HEIGHT 0x1598345#define DST_HEIGHT_WIDTH 0x143c346#define DST_OFFSET 0x1404347#define SRC_CLUT_ADDRESS 0x1780348#define SRC_CLUT_DATA 0x1784349#define SRC_CLUT_DATA_RD 0x1788350#define HOST_DATA0 0x17C0351#define HOST_DATA1 0x17C4352#define HOST_DATA2 0x17C8353#define HOST_DATA3 0x17CC354#define HOST_DATA4 0x17D0355#define HOST_DATA5 0x17D4356#define HOST_DATA6 0x17D8357#define HOST_DATA7 0x17DC358#define HOST_DATA_LAST 0x17E0359#define DP_SRC_ENDIAN 0x15D4360#define DP_SRC_FRGD_CLR 0x15D8361#define DP_SRC_BKGD_CLR 0x15DC362#define SC_LEFT 0x1640363#define SC_RIGHT 0x1644364#define SC_TOP 0x1648365#define SC_BOTTOM 0x164C366#define SRC_SC_RIGHT 0x1654367#define SRC_SC_BOTTOM 0x165C368#define DP_CNTL 0x16C0369#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0370#define DP_DATATYPE 0x16C4371#define DP_MIX 0x16C8372#define DP_WRITE_MSK 0x16CC373#define DP_XOP 0x17F8374#define CLR_CMP_CLR_SRC 0x15C4375#define CLR_CMP_CLR_DST 0x15C8376#define CLR_CMP_CNTL 0x15C0377#define CLR_CMP_MSK 0x15CC378#define DSTCACHE_MODE 0x1710379#define DSTCACHE_CTLSTAT 0x1714380#define DEFAULT_PITCH_OFFSET 0x16E0381#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8382#define DEFAULT_SC_TOP_LEFT 0x16EC383#define SRC_PITCH_OFFSET 0x1428384#define DST_PITCH_OFFSET 0x142C385#define DP_GUI_MASTER_CNTL 0x146C386#define SC_TOP_LEFT 0x16EC387#define SC_BOTTOM_RIGHT 0x16F0388#define SRC_SC_BOTTOM_RIGHT 0x16F4389#define RB2D_DSTCACHE_MODE 0x3428390#define RB2D_DSTCACHE_CTLSTAT_broken 0x342C /* do not use */391#define LVDS_GEN_CNTL 0x02d0392#define LVDS_PLL_CNTL 0x02d4393#define FP2_GEN_CNTL 0x0288394#define TMDS_CNTL 0x0294395#define TMDS_CRC 0x02a0396#define TMDS_TRANSMITTER_CNTL 0x02a4397#define MPP_TB_CONFIG 0x01c0398#define PAMAC0_DLY_CNTL 0x0a94399#define PAMAC1_DLY_CNTL 0x0a98400#define PAMAC2_DLY_CNTL 0x0a9c401#define FW_CNTL 0x0118402#define FCP_CNTL 0x0910403#define VGA_DDA_ON_OFF 0x02ec404#define TV_MASTER_CNTL 0x0800405 406//#define BASE_CODE 0x0f0b407#define BIOS_0_SCRATCH 0x0010408#define BIOS_1_SCRATCH 0x0014409#define BIOS_2_SCRATCH 0x0018410#define BIOS_3_SCRATCH 0x001c411#define BIOS_4_SCRATCH 0x0020412#define BIOS_5_SCRATCH 0x0024413#define BIOS_6_SCRATCH 0x0028414#define BIOS_7_SCRATCH 0x002c415 416#define HDP_SOFT_RESET (1 << 26)417 418#define TV_DAC_CNTL 0x088c419#define GPIOPAD_MASK 0x0198420#define GPIOPAD_A 0x019c421#define GPIOPAD_EN 0x01a0422#define GPIOPAD_Y 0x01a4423#define ZV_LCDPAD_MASK 0x01a8424#define ZV_LCDPAD_A 0x01ac425#define ZV_LCDPAD_EN 0x01b0426#define ZV_LCDPAD_Y 0x01b4427 428/* PLL Registers */429#define CLK_PIN_CNTL 0x0001430#define PPLL_CNTL 0x0002431#define PPLL_REF_DIV 0x0003432#define PPLL_DIV_0 0x0004433#define PPLL_DIV_1 0x0005434#define PPLL_DIV_2 0x0006435#define PPLL_DIV_3 0x0007436#define VCLK_ECP_CNTL 0x0008437#define HTOTAL_CNTL 0x0009438#define M_SPLL_REF_FB_DIV 0x000a439#define AGP_PLL_CNTL 0x000b440#define SPLL_CNTL 0x000c441#define SCLK_CNTL 0x000d442#define MPLL_CNTL 0x000e443#define MDLL_CKO 0x000f444#define MDLL_RDCKA 0x0010445#define MCLK_CNTL 0x0012446#define AGP_PLL_CNTL 0x000b447#define PLL_TEST_CNTL 0x0013448#define CLK_PWRMGT_CNTL 0x0014449#define PLL_PWRMGT_CNTL 0x0015450#define MCLK_MISC 0x001f451#define P2PLL_CNTL 0x002a452#define P2PLL_REF_DIV 0x002b453#define PIXCLKS_CNTL 0x002d454#define SCLK_MORE_CNTL 0x0035455 456/* MCLK_CNTL bit constants */457#define FORCEON_MCLKA (1 << 16)458#define FORCEON_MCLKB (1 << 17)459#define FORCEON_YCLKA (1 << 18)460#define FORCEON_YCLKB (1 << 19)461#define FORCEON_MC (1 << 20)462#define FORCEON_AIC (1 << 21)463 464/* SCLK_CNTL bit constants */465#define DYN_STOP_LAT_MASK 0x00007ff8466#define CP_MAX_DYN_STOP_LAT 0x0008467#define SCLK_FORCEON_MASK 0xffff8000468 469/* SCLK_MORE_CNTL bit constants */470#define SCLK_MORE_FORCEON 0x0700471 472/* BUS_CNTL bit constants */473#define BUS_DBL_RESYNC 0x00000001474#define BUS_MSTR_RESET 0x00000002475#define BUS_FLUSH_BUF 0x00000004476#define BUS_STOP_REQ_DIS 0x00000008477#define BUS_ROTATION_DIS 0x00000010478#define BUS_MASTER_DIS 0x00000040479#define BUS_ROM_WRT_EN 0x00000080480#define BUS_DIS_ROM 0x00001000481#define BUS_PCI_READ_RETRY_EN 0x00002000482#define BUS_AGP_AD_STEPPING_EN 0x00004000483#define BUS_PCI_WRT_RETRY_EN 0x00008000484#define BUS_MSTR_RD_MULT 0x00100000485#define BUS_MSTR_RD_LINE 0x00200000486#define BUS_SUSPEND 0x00400000487#define LAT_16X 0x00800000488#define BUS_RD_DISCARD_EN 0x01000000489#define BUS_RD_ABORT_EN 0x02000000490#define BUS_MSTR_WS 0x04000000491#define BUS_PARKING_DIS 0x08000000492#define BUS_MSTR_DISCONNECT_EN 0x10000000493#define BUS_WRT_BURST 0x20000000494#define BUS_READ_BURST 0x40000000495#define BUS_RDY_READ_DLY 0x80000000496 497/* PIXCLKS_CNTL */498#define PIX2CLK_SRC_SEL_MASK 0x03499#define PIX2CLK_SRC_SEL_CPUCLK 0x00500#define PIX2CLK_SRC_SEL_PSCANCLK 0x01501#define PIX2CLK_SRC_SEL_BYTECLK 0x02502#define PIX2CLK_SRC_SEL_P2PLLCLK 0x03503#define PIX2CLK_ALWAYS_ONb (1<<6)504#define PIX2CLK_DAC_ALWAYS_ONb (1<<7)505#define PIXCLK_TV_SRC_SEL (1 << 8)506#define PIXCLK_LVDS_ALWAYS_ONb (1 << 14)507#define PIXCLK_TMDS_ALWAYS_ONb (1 << 15)508 509 510/* CLOCK_CNTL_INDEX bit constants */511#define PLL_WR_EN 0x00000080512 513/* CNFG_CNTL bit constants */514#define CFG_VGA_RAM_EN 0x00000100515#define CFG_ATI_REV_ID_MASK (0xf << 16)516#define CFG_ATI_REV_A11 (0 << 16)517#define CFG_ATI_REV_A12 (1 << 16)518#define CFG_ATI_REV_A13 (2 << 16)519 520/* CRTC_EXT_CNTL bit constants */521#define VGA_ATI_LINEAR 0x00000008522#define VGA_128KAP_PAGING 0x00000010523#define XCRT_CNT_EN (1 << 6)524#define CRTC_HSYNC_DIS (1 << 8)525#define CRTC_VSYNC_DIS (1 << 9)526#define CRTC_DISPLAY_DIS (1 << 10)527#define CRTC_CRT_ON (1 << 15)528 529 530/* DSTCACHE_CTLSTAT bit constants */531#define RB2D_DC_FLUSH_2D (1 << 0)532#define RB2D_DC_FREE_2D (1 << 2)533#define RB2D_DC_FLUSH_ALL (RB2D_DC_FLUSH_2D | RB2D_DC_FREE_2D)534#define RB2D_DC_BUSY (1 << 31)535 536/* DSTCACHE_MODE bits constants */537#define RB2D_DC_AUTOFLUSH_ENABLE (1 << 8)538#define RB2D_DC_DC_DISABLE_IGNORE_PE (1 << 17)539 540/* CRTC_GEN_CNTL bit constants */541#define CRTC_DBL_SCAN_EN 0x00000001542#define CRTC_CUR_EN 0x00010000543#define CRTC_INTERLACE_EN (1 << 1)544#define CRTC_BYPASS_LUT_EN (1 << 14)545#define CRTC_EXT_DISP_EN (1 << 24)546#define CRTC_EN (1 << 25)547#define CRTC_DISP_REQ_EN_B (1 << 26)548 549/* CRTC_STATUS bit constants */550#define CRTC_VBLANK 0x00000001551 552/* CRTC2_GEN_CNTL bit constants */553#define CRT2_ON (1 << 7)554#define CRTC2_DISPLAY_DIS (1 << 23)555#define CRTC2_EN (1 << 25)556#define CRTC2_DISP_REQ_EN_B (1 << 26)557 558/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */559#define CUR_LOCK 0x80000000560 561/* GPIO bit constants */562#define GPIO_A_0 (1 << 0)563#define GPIO_A_1 (1 << 1)564#define GPIO_Y_0 (1 << 8)565#define GPIO_Y_1 (1 << 9)566#define GPIO_EN_0 (1 << 16)567#define GPIO_EN_1 (1 << 17)568#define GPIO_MASK_0 (1 << 24)569#define GPIO_MASK_1 (1 << 25)570#define VGA_DDC_DATA_OUTPUT GPIO_A_0571#define VGA_DDC_CLK_OUTPUT GPIO_A_1572#define VGA_DDC_DATA_INPUT GPIO_Y_0573#define VGA_DDC_CLK_INPUT GPIO_Y_1574#define VGA_DDC_DATA_OUT_EN GPIO_EN_0575#define VGA_DDC_CLK_OUT_EN GPIO_EN_1576 577 578/* FP bit constants */579#define FP_CRTC_H_TOTAL_MASK 0x000003ff580#define FP_CRTC_H_DISP_MASK 0x01ff0000581#define FP_CRTC_V_TOTAL_MASK 0x00000fff582#define FP_CRTC_V_DISP_MASK 0x0fff0000583#define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8584#define FP_H_SYNC_WID_MASK 0x003f0000585#define FP_V_SYNC_STRT_MASK 0x00000fff586#define FP_V_SYNC_WID_MASK 0x001f0000587#define FP_CRTC_H_TOTAL_SHIFT 0x00000000588#define FP_CRTC_H_DISP_SHIFT 0x00000010589#define FP_CRTC_V_TOTAL_SHIFT 0x00000000590#define FP_CRTC_V_DISP_SHIFT 0x00000010591#define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003592#define FP_H_SYNC_WID_SHIFT 0x00000010593#define FP_V_SYNC_STRT_SHIFT 0x00000000594#define FP_V_SYNC_WID_SHIFT 0x00000010595 596/* FP_GEN_CNTL bit constants */597#define FP_FPON (1 << 0)598#define FP_TMDS_EN (1 << 2)599#define FP_PANEL_FORMAT (1 << 3)600#define FP_EN_TMDS (1 << 7)601#define FP_DETECT_SENSE (1 << 8)602#define R200_FP_SOURCE_SEL_MASK (3 << 10)603#define R200_FP_SOURCE_SEL_CRTC1 (0 << 10)604#define R200_FP_SOURCE_SEL_CRTC2 (1 << 10)605#define R200_FP_SOURCE_SEL_RMX (2 << 10)606#define R200_FP_SOURCE_SEL_TRANS (3 << 10)607#define FP_SEL_CRTC1 (0 << 13)608#define FP_SEL_CRTC2 (1 << 13)609#define FP_USE_VGA_HSYNC (1 << 14)610#define FP_CRTC_DONT_SHADOW_HPAR (1 << 15)611#define FP_CRTC_DONT_SHADOW_VPAR (1 << 16)612#define FP_CRTC_DONT_SHADOW_HEND (1 << 17)613#define FP_CRTC_USE_SHADOW_VEND (1 << 18)614#define FP_RMX_HVSYNC_CONTROL_EN (1 << 20)615#define FP_DFP_SYNC_SEL (1 << 21)616#define FP_CRTC_LOCK_8DOT (1 << 22)617#define FP_CRT_SYNC_SEL (1 << 23)618#define FP_USE_SHADOW_EN (1 << 24)619#define FP_CRT_SYNC_ALT (1 << 26)620 621/* FP2_GEN_CNTL bit constants */622#define FP2_BLANK_EN (1 << 1)623#define FP2_ON (1 << 2)624#define FP2_PANEL_FORMAT (1 << 3)625#define FP2_SOURCE_SEL_MASK (3 << 10)626#define FP2_SOURCE_SEL_CRTC2 (1 << 10)627#define FP2_SRC_SEL_MASK (3 << 13)628#define FP2_SRC_SEL_CRTC2 (1 << 13)629#define FP2_FP_POL (1 << 16)630#define FP2_LP_POL (1 << 17)631#define FP2_SCK_POL (1 << 18)632#define FP2_LCD_CNTL_MASK (7 << 19)633#define FP2_PAD_FLOP_EN (1 << 22)634#define FP2_CRC_EN (1 << 23)635#define FP2_CRC_READ_EN (1 << 24)636#define FP2_DV0_EN (1 << 25)637#define FP2_DV0_RATE_SEL_SDR (1 << 26)638 639 640/* LVDS_GEN_CNTL bit constants */641#define LVDS_ON (1 << 0)642#define LVDS_DISPLAY_DIS (1 << 1)643#define LVDS_PANEL_TYPE (1 << 2)644#define LVDS_PANEL_FORMAT (1 << 3)645#define LVDS_EN (1 << 7)646#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00647#define LVDS_BL_MOD_LEVEL_SHIFT 8648#define LVDS_BL_MOD_EN (1 << 16)649#define LVDS_DIGON (1 << 18)650#define LVDS_BLON (1 << 19)651#define LVDS_SEL_CRTC2 (1 << 23)652#define LVDS_STATE_MASK \653 (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON)654 655/* LVDS_PLL_CNTL bit constatns */656#define HSYNC_DELAY_SHIFT 0x1c657#define HSYNC_DELAY_MASK (0xf << 0x1c)658 659/* TMDS_TRANSMITTER_CNTL bit constants */660#define TMDS_PLL_EN (1 << 0)661#define TMDS_PLLRST (1 << 1)662#define TMDS_RAN_PAT_RST (1 << 7)663#define TMDS_ICHCSEL (1 << 28)664 665/* FP_HORZ_STRETCH bit constants */666#define HORZ_STRETCH_RATIO_MASK 0xffff667#define HORZ_STRETCH_RATIO_MAX 4096668#define HORZ_PANEL_SIZE (0x1ff << 16)669#define HORZ_PANEL_SHIFT 16670#define HORZ_STRETCH_PIXREP (0 << 25)671#define HORZ_STRETCH_BLEND (1 << 26)672#define HORZ_STRETCH_ENABLE (1 << 25)673#define HORZ_AUTO_RATIO (1 << 27)674#define HORZ_FP_LOOP_STRETCH (0x7 << 28)675#define HORZ_AUTO_RATIO_INC (1 << 31)676 677 678/* FP_VERT_STRETCH bit constants */679#define VERT_STRETCH_RATIO_MASK 0xfff680#define VERT_STRETCH_RATIO_MAX 4096681#define VERT_PANEL_SIZE (0xfff << 12)682#define VERT_PANEL_SHIFT 12683#define VERT_STRETCH_LINREP (0 << 26)684#define VERT_STRETCH_BLEND (1 << 26)685#define VERT_STRETCH_ENABLE (1 << 25)686#define VERT_AUTO_RATIO_EN (1 << 27)687#define VERT_FP_LOOP_STRETCH (0x7 << 28)688#define VERT_STRETCH_RESERVED 0xf1000000689 690/* DAC_CNTL bit constants */691#define DAC_8BIT_EN 0x00000100692#define DAC_4BPP_PIX_ORDER 0x00000200693#define DAC_CRC_EN 0x00080000694#define DAC_MASK_ALL (0xff << 24)695#define DAC_PDWN (1 << 15)696#define DAC_EXPAND_MODE (1 << 14)697#define DAC_VGA_ADR_EN (1 << 13)698#define DAC_RANGE_CNTL (3 << 0)699#define DAC_RANGE_CNTL_MASK 0x03700#define DAC_BLANKING (1 << 2)701#define DAC_CMP_EN (1 << 3)702#define DAC_CMP_OUTPUT (1 << 7)703 704/* DAC_CNTL2 bit constants */705#define DAC2_EXPAND_MODE (1 << 14)706#define DAC2_CMP_EN (1 << 7)707#define DAC2_PALETTE_ACCESS_CNTL (1 << 5)708 709/* DAC_EXT_CNTL bit constants */710#define DAC_FORCE_BLANK_OFF_EN (1 << 4)711#define DAC_FORCE_DATA_EN (1 << 5)712#define DAC_FORCE_DATA_SEL_MASK (3 << 6)713#define DAC_FORCE_DATA_MASK 0x0003ff00714#define DAC_FORCE_DATA_SHIFT 8715 716/* GEN_RESET_CNTL bit constants */717#define SOFT_RESET_GUI 0x00000001718#define SOFT_RESET_VCLK 0x00000100719#define SOFT_RESET_PCLK 0x00000200720#define SOFT_RESET_ECP 0x00000400721#define SOFT_RESET_DISPENG_XCLK 0x00000800722 723/* MEM_CNTL bit constants */724#define MEM_CTLR_STATUS_IDLE 0x00000000725#define MEM_CTLR_STATUS_BUSY 0x00100000726#define MEM_SEQNCR_STATUS_IDLE 0x00000000727#define MEM_SEQNCR_STATUS_BUSY 0x00200000728#define MEM_ARBITER_STATUS_IDLE 0x00000000729#define MEM_ARBITER_STATUS_BUSY 0x00400000730#define MEM_REQ_UNLOCK 0x00000000731#define MEM_REQ_LOCK 0x00800000732#define MEM_NUM_CHANNELS_MASK 0x00000001733#define MEM_USE_B_CH_ONLY 0x00000002734#define RV100_MEM_HALF_MODE 0x00000008735#define R300_MEM_NUM_CHANNELS_MASK 0x00000003736#define R300_MEM_USE_CD_CH_ONLY 0x00000004737 738 739/* RBBM_SOFT_RESET bit constants */740#define SOFT_RESET_CP (1 << 0)741#define SOFT_RESET_HI (1 << 1)742#define SOFT_RESET_SE (1 << 2)743#define SOFT_RESET_RE (1 << 3)744#define SOFT_RESET_PP (1 << 4)745#define SOFT_RESET_E2 (1 << 5)746#define SOFT_RESET_RB (1 << 6)747#define SOFT_RESET_HDP (1 << 7)748 749/* WAIT_UNTIL bit constants */750#define WAIT_DMA_GUI_IDLE (1 << 9)751#define WAIT_2D_IDLECLEAN (1 << 16)752 753/* SURFACE_CNTL bit constants */754#define SURF_TRANSLATION_DIS (1 << 8)755#define NONSURF_AP0_SWP_16BPP (1 << 20)756#define NONSURF_AP0_SWP_32BPP (1 << 21)757#define NONSURF_AP1_SWP_16BPP (1 << 22)758#define NONSURF_AP1_SWP_32BPP (1 << 23)759 760/* DEFAULT_SC_BOTTOM_RIGHT bit constants */761#define DEFAULT_SC_RIGHT_MAX (0x1fff << 0)762#define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)763 764/* MM_INDEX bit constants */765#define MM_APER 0x80000000766 767/* CLR_CMP_CNTL bit constants */768#define COMPARE_SRC_FALSE 0x00000000769#define COMPARE_SRC_TRUE 0x00000001770#define COMPARE_SRC_NOT_EQUAL 0x00000004771#define COMPARE_SRC_EQUAL 0x00000005772#define COMPARE_SRC_EQUAL_FLIP 0x00000007773#define COMPARE_DST_FALSE 0x00000000774#define COMPARE_DST_TRUE 0x00000100775#define COMPARE_DST_NOT_EQUAL 0x00000400776#define COMPARE_DST_EQUAL 0x00000500777#define COMPARE_DESTINATION 0x00000000778#define COMPARE_SOURCE 0x01000000779#define COMPARE_SRC_AND_DST 0x02000000780 781 782/* DP_CNTL bit constants */783#define DST_X_RIGHT_TO_LEFT 0x00000000784#define DST_X_LEFT_TO_RIGHT 0x00000001785#define DST_Y_BOTTOM_TO_TOP 0x00000000786#define DST_Y_TOP_TO_BOTTOM 0x00000002787#define DST_X_MAJOR 0x00000000788#define DST_Y_MAJOR 0x00000004789#define DST_X_TILE 0x00000008790#define DST_Y_TILE 0x00000010791#define DST_LAST_PEL 0x00000020792#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000793#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040794#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000795#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080796#define DST_BRES_SIGN 0x00000100797#define DST_HOST_BIG_ENDIAN_EN 0x00000200798#define DST_POLYLINE_NONLAST 0x00008000799#define DST_RASTER_STALL 0x00010000800#define DST_POLY_EDGE 0x00040000801 802 803/* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */804#define DST_X_MAJOR_S 0x00000000805#define DST_Y_MAJOR_S 0x00000001806#define DST_Y_BOTTOM_TO_TOP_S 0x00000000807#define DST_Y_TOP_TO_BOTTOM_S 0x00008000808#define DST_X_RIGHT_TO_LEFT_S 0x00000000809#define DST_X_LEFT_TO_RIGHT_S 0x80000000810 811 812/* DP_DATATYPE bit constants */813#define DST_8BPP 0x00000002814#define DST_15BPP 0x00000003815#define DST_16BPP 0x00000004816#define DST_24BPP 0x00000005817#define DST_32BPP 0x00000006818#define DST_8BPP_RGB332 0x00000007819#define DST_8BPP_Y8 0x00000008820#define DST_8BPP_RGB8 0x00000009821#define DST_16BPP_VYUY422 0x0000000b822#define DST_16BPP_YVYU422 0x0000000c823#define DST_32BPP_AYUV444 0x0000000e824#define DST_16BPP_ARGB4444 0x0000000f825#define BRUSH_SOLIDCOLOR 0x00000d00826#define SRC_MONO 0x00000000827#define SRC_MONO_LBKGD 0x00010000828#define SRC_DSTCOLOR 0x00030000829#define BYTE_ORDER_MSB_TO_LSB 0x00000000830#define BYTE_ORDER_LSB_TO_MSB 0x40000000831#define DP_CONVERSION_TEMP 0x80000000832#define HOST_BIG_ENDIAN_EN (1 << 29)833 834 835/* DP_GUI_MASTER_CNTL bit constants */836#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000837#define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001838#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000839#define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002840#define GMC_SRC_CLIP_DEFAULT 0x00000000841#define GMC_SRC_CLIP_LEAVE 0x00000004842#define GMC_DST_CLIP_DEFAULT 0x00000000843#define GMC_DST_CLIP_LEAVE 0x00000008844#define GMC_BRUSH_8x8MONO 0x00000000845#define GMC_BRUSH_8x8MONO_LBKGD 0x00000010846#define GMC_BRUSH_8x1MONO 0x00000020847#define GMC_BRUSH_8x1MONO_LBKGD 0x00000030848#define GMC_BRUSH_1x8MONO 0x00000040849#define GMC_BRUSH_1x8MONO_LBKGD 0x00000050850#define GMC_BRUSH_32x1MONO 0x00000060851#define GMC_BRUSH_32x1MONO_LBKGD 0x00000070852#define GMC_BRUSH_32x32MONO 0x00000080853#define GMC_BRUSH_32x32MONO_LBKGD 0x00000090854#define GMC_BRUSH_8x8COLOR 0x000000a0855#define GMC_BRUSH_8x1COLOR 0x000000b0856#define GMC_BRUSH_1x8COLOR 0x000000c0857#define GMC_BRUSH_SOLID_COLOR 0x000000d0858#define GMC_DST_8BPP 0x00000200859#define GMC_DST_15BPP 0x00000300860#define GMC_DST_16BPP 0x00000400861#define GMC_DST_24BPP 0x00000500862#define GMC_DST_32BPP 0x00000600863#define GMC_DST_8BPP_RGB332 0x00000700864#define GMC_DST_8BPP_Y8 0x00000800865#define GMC_DST_8BPP_RGB8 0x00000900866#define GMC_DST_16BPP_VYUY422 0x00000b00867#define GMC_DST_16BPP_YVYU422 0x00000c00868#define GMC_DST_32BPP_AYUV444 0x00000e00869#define GMC_DST_16BPP_ARGB4444 0x00000f00870#define GMC_SRC_MONO 0x00000000871#define GMC_SRC_MONO_LBKGD 0x00001000872#define GMC_SRC_DSTCOLOR 0x00003000873#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000874#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000875#define GMC_DP_CONVERSION_TEMP_9300 0x00008000876#define GMC_DP_CONVERSION_TEMP_6500 0x00000000877#define GMC_DP_SRC_RECT 0x02000000878#define GMC_DP_SRC_HOST 0x03000000879#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000880#define GMC_3D_FCN_EN_CLR 0x00000000881#define GMC_3D_FCN_EN_SET 0x08000000882#define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000883#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000884#define GMC_AUX_CLIP_LEAVE 0x00000000885#define GMC_AUX_CLIP_CLEAR 0x20000000886#define GMC_WRITE_MASK_LEAVE 0x00000000887#define GMC_WRITE_MASK_SET 0x40000000888#define GMC_CLR_CMP_CNTL_DIS (1 << 28)889#define GMC_SRC_DATATYPE_COLOR (3 << 12)890#define ROP3_S 0x00cc0000891#define ROP3_SRCCOPY 0x00cc0000892#define ROP3_P 0x00f00000893#define ROP3_PATCOPY 0x00f00000894#define DP_SRC_SOURCE_MASK (7 << 24)895#define GMC_BRUSH_NONE (15 << 4)896#define DP_SRC_SOURCE_MEMORY (2 << 24)897#define GMC_BRUSH_SOLIDCOLOR 0x000000d0898 899/* DP_MIX bit constants */900#define DP_SRC_RECT 0x00000200901#define DP_SRC_HOST 0x00000300902#define DP_SRC_HOST_BYTEALIGN 0x00000400903 904/* MPLL_CNTL bit constants */905#define MPLL_RESET 0x00000001906 907/* MDLL_CKO bit constants */908#define MCKOA_SLEEP 0x00000001909#define MCKOA_RESET 0x00000002910#define MCKOA_REF_SKEW_MASK 0x00000700911#define MCKOA_FB_SKEW_MASK 0x00007000912 913/* MDLL_RDCKA bit constants */914#define MRDCKA0_SLEEP 0x00000001915#define MRDCKA0_RESET 0x00000002916#define MRDCKA1_SLEEP 0x00010000917#define MRDCKA1_RESET 0x00020000918 919/* VCLK_ECP_CNTL constants */920#define VCLK_SRC_SEL_MASK 0x03921#define VCLK_SRC_SEL_CPUCLK 0x00922#define VCLK_SRC_SEL_PSCANCLK 0x01923#define VCLK_SRC_SEL_BYTECLK 0x02924#define VCLK_SRC_SEL_PPLLCLK 0x03925#define PIXCLK_ALWAYS_ONb 0x00000040926#define PIXCLK_DAC_ALWAYS_ONb 0x00000080927 928/* BUS_CNTL1 constants */929#define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000930#define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26931#define BUS_CNTL1_AGPCLK_VALID 0x80000000932 933/* PLL_PWRMGT_CNTL constants */934#define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002935#define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004936#define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008937#define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010938#define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000939#define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000940#define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000941 942/* TV_DAC_CNTL constants */943#define TV_DAC_CNTL_BGSLEEP 0x00000040944#define TV_DAC_CNTL_DETECT 0x00000010945#define TV_DAC_CNTL_BGADJ_MASK 0x000f0000946#define TV_DAC_CNTL_DACADJ_MASK 0x00f00000947#define TV_DAC_CNTL_BGADJ__SHIFT 16948#define TV_DAC_CNTL_DACADJ__SHIFT 20949#define TV_DAC_CNTL_RDACPD 0x01000000950#define TV_DAC_CNTL_GDACPD 0x02000000951#define TV_DAC_CNTL_BDACPD 0x04000000952 953/* DISP_MISC_CNTL constants */954#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0)955#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1)956#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2)957#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4)958#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5)959#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6)960#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12)961#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15)962#define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16)963#define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17)964#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18)965#define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19)966 967/* DISP_PWR_MAN constants */968#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0)969#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4)970#define DISP_PWR_MAN_DISP_D3_RST (1 << 16)971#define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17)972#define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18)973#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19)974#define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20)975#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21)976#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22)977#define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23)978#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24)979#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25)980#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26)981 982/* masks */983 984#define CNFG_MEMSIZE_MASK 0x1f000000985#define MEM_CFG_TYPE 0x40000000986#define DST_OFFSET_MASK 0x003fffff987#define DST_PITCH_MASK 0x3fc00000988#define DEFAULT_TILE_MASK 0xc0000000989#define PPLL_DIV_SEL_MASK 0x00000300990#define PPLL_RESET 0x00000001991#define PPLL_SLEEP 0x00000002992#define PPLL_ATOMIC_UPDATE_EN 0x00010000993#define PPLL_REF_DIV_MASK 0x000003ff994#define PPLL_FB3_DIV_MASK 0x000007ff995#define PPLL_POST3_DIV_MASK 0x00070000996#define PPLL_ATOMIC_UPDATE_R 0x00008000997#define PPLL_ATOMIC_UPDATE_W 0x00008000998#define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000999#define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)1000#define R300_PPLL_REF_DIV_ACC_SHIFT 181001 1002#define GUI_ACTIVE 0x800000001003 1004 1005#define MC_IND_INDEX 0x01F81006#define MC_IND_DATA 0x01FC1007 1008/* PAD_CTLR_STRENGTH */1009#define PAD_MANUAL_OVERRIDE 0x800000001010 1011// pllCLK_PIN_CNTL1012#define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L1013#define CLK_PIN_CNTL__OSC_EN 0x00000001L1014#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L1015#define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L1016#define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L1017#define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L1018#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L1019#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L1020#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L1021#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L1022#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L1023#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L1024#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L1025#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L1026#define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L1027#define CLK_PIN_CNTL__CG_SPARE 0x00004000L1028#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L1029#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L1030#define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L1031#define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L1032#define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L1033#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L1034#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L1035#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L1036 1037// pllCLK_PWRMGT_CNTL1038#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x000000001039#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x000000011040#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x000000021041#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT 0x000000031042#define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT 0x000000041043#define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT 0x000000051044#define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT 0x000000061045#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT 0x000000071046#define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT 0x000000081047#define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT 0x000000091048#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT 0x0000000a1049#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c1050#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT 0x0000000d1051#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT 0x0000000f1052#define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT 0x000000101053#define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x000000111054#define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT 0x000000121055#define CLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x000000131056#define CLK_PWRMGT_CNTL__DISP_PM__SHIFT 0x000000141057#define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT 0x000000151058#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT 0x000000181059#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e1060#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f1061 1062// pllP2PLL_CNTL1063#define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L1064#define P2PLL_CNTL__P2PLL_RESET 0x00000001L1065#define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L1066#define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L1067#define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L1068#define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L1069#define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L1070#define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L1071#define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L1072#define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L1073#define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L1074#define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L1075#define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L1076#define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L1077#define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L1078#define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L1079#define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L1080#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L1081#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L1082#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L1083#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L1084#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L1085#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L1086 1087// pllPIXCLKS_CNTL1088#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x000000001089#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x000000041090#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x000000051091#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x000000061092#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x000000071093#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x000000081094#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b1095#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c1096#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d1097#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT 0x0000000e1098#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f1099 1100 1101// pllPIXCLKS_CNTL1102#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L1103#define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L1104#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L1105#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb 0x00000040L1106#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb 0x00000080L1107#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL 0x00000100L1108#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb 0x00000800L1109#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb 0x00001000L1110#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L1111#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L1112#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L1113#define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9)1114#define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb (1 << 10)1115#define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13)1116#define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16)1117#define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17)1118#define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb (1 << 18)1119#define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19)1120#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)1121 1122 1123// pllP2PLL_DIV_01124#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL1125#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L1126#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L1127#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK 0x00008000L1128#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L1129#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L1130 1131// pllSCLK_CNTL1132#define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L1133#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L1134#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L1135#define SCLK_CNTL__TV_MAX_DYN_STOP_LAT 0x00000020L1136#define SCLK_CNTL__E2_MAX_DYN_STOP_LAT 0x00000040L1137#define SCLK_CNTL__SE_MAX_DYN_STOP_LAT 0x00000080L1138#define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT 0x00000100L1139#define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT 0x00000200L1140#define SCLK_CNTL__RE_MAX_DYN_STOP_LAT 0x00000400L1141#define SCLK_CNTL__PB_MAX_DYN_STOP_LAT 0x00000800L1142#define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT 0x00001000L1143#define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT 0x00002000L1144#define SCLK_CNTL__RB_MAX_DYN_STOP_LAT 0x00004000L1145#define SCLK_CNTL__DYN_STOP_LAT_MASK 0x00007ff81146#define SCLK_CNTL__FORCE_DISP2 0x00008000L1147#define SCLK_CNTL__FORCE_CP 0x00010000L1148#define SCLK_CNTL__FORCE_HDP 0x00020000L1149#define SCLK_CNTL__FORCE_DISP1 0x00040000L1150#define SCLK_CNTL__FORCE_TOP 0x00080000L1151#define SCLK_CNTL__FORCE_E2 0x00100000L1152#define SCLK_CNTL__FORCE_SE 0x00200000L1153#define SCLK_CNTL__FORCE_IDCT 0x00400000L1154#define SCLK_CNTL__FORCE_VIP 0x00800000L1155#define SCLK_CNTL__FORCE_RE 0x01000000L1156#define SCLK_CNTL__FORCE_PB 0x02000000L1157#define SCLK_CNTL__FORCE_TAM 0x04000000L1158#define SCLK_CNTL__FORCE_TDM 0x08000000L1159#define SCLK_CNTL__FORCE_RB 0x10000000L1160#define SCLK_CNTL__FORCE_TV_SCLK 0x20000000L1161#define SCLK_CNTL__FORCE_SUBPIC 0x40000000L1162#define SCLK_CNTL__FORCE_OV0 0x80000000L1163#define SCLK_CNTL__R300_FORCE_VAP (1<<21)1164#define SCLK_CNTL__R300_FORCE_SR (1<<25)1165#define SCLK_CNTL__R300_FORCE_PX (1<<26)1166#define SCLK_CNTL__R300_FORCE_TX (1<<27)1167#define SCLK_CNTL__R300_FORCE_US (1<<28)1168#define SCLK_CNTL__R300_FORCE_SU (1<<30)1169#define SCLK_CNTL__FORCEON_MASK 0xffff8000L1170 1171// pllSCLK_CNTL21172#define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10)1173#define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11)1174#define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12)1175#define SCLK_CNTL2__R300_FORCE_TCL (1<<13)1176#define SCLK_CNTL2__R300_FORCE_CBA (1<<14)1177#define SCLK_CNTL2__R300_FORCE_GA (1<<15)1178 1179// SCLK_MORE_CNTL1180#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L1181#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L1182#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L1183#define SCLK_MORE_CNTL__FORCE_DISPREGS 0x00000100L1184#define SCLK_MORE_CNTL__FORCE_MC_GUI 0x00000200L1185#define SCLK_MORE_CNTL__FORCE_MC_HOST 0x00000400L1186#define SCLK_MORE_CNTL__STOP_SCLK_EN 0x00001000L1187#define SCLK_MORE_CNTL__STOP_SCLK_A 0x00002000L1188#define SCLK_MORE_CNTL__STOP_SCLK_B 0x00004000L1189#define SCLK_MORE_CNTL__STOP_SCLK_C 0x00008000L1190#define SCLK_MORE_CNTL__HALF_SPEED_SCLK 0x00010000L1191#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP 0x00020000L1192#define SCLK_MORE_CNTL__TVFB_SOFT_RESET 0x00040000L1193#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC 0x00080000L1194#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK 0x00400000L1195#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK 0x00800000L1196#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L1197#define SCLK_MORE_CNTL__FORCEON 0x00000700L1198 1199// MCLK_CNTL1200#define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L1201#define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L1202#define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L1203#define MCLK_CNTL__YCLKB_SRC_SEL_MASK 0x00007000L1204#define MCLK_CNTL__FORCE_MCLKA_MASK 0x00010000L1205#define MCLK_CNTL__FORCE_MCLKA 0x00010000L1206#define MCLK_CNTL__FORCE_MCLKB_MASK 0x00020000L1207#define MCLK_CNTL__FORCE_MCLKB 0x00020000L1208#define MCLK_CNTL__FORCE_YCLKA_MASK 0x00040000L1209#define MCLK_CNTL__FORCE_YCLKA 0x00040000L1210#define MCLK_CNTL__FORCE_YCLKB_MASK 0x00080000L1211#define MCLK_CNTL__FORCE_YCLKB 0x00080000L1212#define MCLK_CNTL__FORCE_MC_MASK 0x00100000L1213#define MCLK_CNTL__FORCE_MC 0x00100000L1214#define MCLK_CNTL__FORCE_AIC_MASK 0x00200000L1215#define MCLK_CNTL__FORCE_AIC 0x00200000L1216#define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK 0x03000000L1217#define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK 0x0c000000L1218#define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK 0x30000000L1219#define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK 0xc0000000L1220#define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21)1221#define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21)1222 1223// MCLK_MISC1224#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L1225#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L1226#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L1227#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK 0x00000008L1228#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL 0x00000008L1229#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK 0x00000010L1230#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN 0x00000010L1231#define MCLK_MISC__DLL_READY_LAT_MASK 0x00000100L1232#define MCLK_MISC__DLL_READY_LAT 0x00000100L1233#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK 0x00001000L1234#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT 0x00001000L1235#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK 0x00002000L1236#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT 0x00002000L1237#define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK 0x00004000L1238#define MCLK_MISC__MC_MCLK_DYN_ENABLE 0x00004000L1239#define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK 0x00008000L1240#define MCLK_MISC__IO_MCLK_DYN_ENABLE 0x00008000L1241#define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK 0x00010000L1242#define MCLK_MISC__CGM_CLK_TO_OUTPIN 0x00010000L1243#define MCLK_MISC__CLK_OR_COUNT_SEL_MASK 0x00020000L1244#define MCLK_MISC__CLK_OR_COUNT_SEL 0x00020000L1245#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK 0x00040000L1246#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND 0x00040000L1247#define MCLK_MISC__CGM_SPARE_RD_MASK 0x00300000L1248#define MCLK_MISC__CGM_SPARE_A_RD_MASK 0x00c00000L1249#define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK 0x01000000L1250#define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L1251#define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L1252 1253// VCLK_ECP_CNTL1254#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L1255#define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L1256#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L1257#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040L1258#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080L1259#define VCLK_ECP_CNTL__ECP_DIV_MASK 0x00000300L1260#define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000L1261#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L1262#define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)1263 1264// PLL_PWRMGT_CNTL1265#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L1266#define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L1267#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L1268#define PLL_PWRMGT_CNTL__SPLL_TURNOFF 0x00000002L1269#define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK 0x00000004L1270#define PLL_PWRMGT_CNTL__PPLL_TURNOFF 0x00000004L1271#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK 0x00000008L1272#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF 0x00000008L1273#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK 0x00000010L1274#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF 0x00000010L1275#define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK 0x000001e0L1276#define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK 0x00000600L1277#define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK 0x00001800L1278#define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK 0x00002000L1279#define PLL_PWRMGT_CNTL__PM_MODE_SEL 0x00002000L1280#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK 0x00004000L1281#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND 0x00004000L1282#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK 0x00008000L1283#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND 0x00008000L1284#define PLL_PWRMGT_CNTL__MOBILE_SU_MASK 0x00010000L1285#define PLL_PWRMGT_CNTL__MOBILE_SU 0x00010000L1286#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK 0x00020000L1287#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK 0x00020000L1288#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK 0x00040000L1289#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK 0x00040000L1290#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK 0x00080000L1291#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE 0x00080000L1292#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK 0x00100000L1293#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE 0x00100000L1294#define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK 0x00200000L1295#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L1296#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L1297 1298// CLK_PWRMGT_CNTL1299#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L1300#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L1301#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L1302#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF 0x00000002L1303#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK 0x00000004L1304#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF 0x00000004L1305#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK 0x00000008L1306#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF 0x00000008L1307#define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK 0x00000010L1308#define CLK_PWRMGT_CNTL__MCLK_TURNOFF 0x00000010L1309#define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK 0x00000020L1310#define CLK_PWRMGT_CNTL__SCLK_TURNOFF 0x00000020L1311#define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK 0x00000040L1312#define CLK_PWRMGT_CNTL__PCLK_TURNOFF 0x00000040L1313#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK 0x00000080L1314#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF 0x00000080L1315#define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK 0x00000100L1316#define CLK_PWRMGT_CNTL__MC_CH_MODE 0x00000100L1317#define CLK_PWRMGT_CNTL__TEST_MODE_MASK 0x00000200L1318#define CLK_PWRMGT_CNTL__TEST_MODE 0x00000200L1319#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK 0x00000400L1320#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN 0x00000400L1321#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK 0x00001000L1322#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE 0x00001000L1323#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK 0x00006000L1324#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK 0x00008000L1325#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT 0x00008000L1326#define CLK_PWRMGT_CNTL__MC_BUSY_MASK 0x00010000L1327#define CLK_PWRMGT_CNTL__MC_BUSY 0x00010000L1328#define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00020000L1329#define CLK_PWRMGT_CNTL__MC_INT_CNTL 0x00020000L1330#define CLK_PWRMGT_CNTL__MC_SWITCH_MASK 0x00040000L1331#define CLK_PWRMGT_CNTL__MC_SWITCH 0x00040000L1332#define CLK_PWRMGT_CNTL__DLL_READY_MASK 0x00080000L1333#define CLK_PWRMGT_CNTL__DLL_READY 0x00080000L1334#define CLK_PWRMGT_CNTL__DISP_PM_MASK 0x00100000L1335#define CLK_PWRMGT_CNTL__DISP_PM 0x00100000L1336#define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK 0x00e00000L1337#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK 0x3f000000L1338#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK 0x40000000L1339#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF 0x40000000L1340#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L1341#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L1342 1343// BUS_CNTL11344#define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L1345#define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L1346#define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L1347#define BUS_CNTL1__PMI_MEM_DISABLE 0x00000002L1348#define BUS_CNTL1__PMI_BM_DISABLE_MASK 0x00000004L1349#define BUS_CNTL1__PMI_BM_DISABLE 0x00000004L1350#define BUS_CNTL1__PMI_INT_DISABLE_MASK 0x00000008L1351#define BUS_CNTL1__PMI_INT_DISABLE 0x00000008L1352#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK 0x00000020L1353#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE 0x00000020L1354#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK 0x00000100L1355#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS 0x00000100L1356#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK 0x00000200L1357#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS 0x00000200L1358#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK 0x00000400L1359#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS 0x00000400L1360#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L1361#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS 0x00000800L1362#define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK 0x0c000000L1363#define BUS_CNTL1__SEND_SBA_LATENCY_MASK 0x70000000L1364#define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L1365#define BUS_CNTL1__AGPCLK_VALID 0x80000000L1366 1367// BUS_CNTL11368#define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x000000001369#define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x000000011370#define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x000000021371#define BUS_CNTL1__PMI_INT_DISABLE__SHIFT 0x000000031372#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT 0x000000051373#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT 0x000000081374#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT 0x000000091375#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT 0x0000000a1376#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b1377#define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT 0x0000001a1378#define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c1379#define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f1380 1381// CRTC_OFFSET_CNTL1382#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL1383#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L1384#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L1385#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000L1386#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK 0x00008000L1387#define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000L1388#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK 0x00010000L1389#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000L1390#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK 0x00020000L1391#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000L1392#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK 0x000c0000L1393#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L1394#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000L1395#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK 0x00200000L1396#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000L1397#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L1398#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L1399#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L1400#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L1401#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L1402#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L1403#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L1404#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L1405 1406// CRTC_GEN_CNTL1407#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L1408#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L1409#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L1410#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L1411#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L1412#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L1413#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L1414#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L1415#define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L1416#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L1417#define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L1418#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L1419#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L1420#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L1421#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L1422#define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L1423#define CRTC_GEN_CNTL__CRTC_EN 0x02000000L1424#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L1425#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L1426 1427// CRTC2_GEN_CNTL1428#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L1429#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L1430#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L1431#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L1432#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L1433#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L1434#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L1435#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L1436#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L1437#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L1438#define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L1439#define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L1440#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L1441#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L1442#define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L1443#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L1444#define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L1445#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L1446#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L1447#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L1448#define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L1449#define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L1450#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L1451#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L1452#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L1453#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L1454#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L1455#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L1456#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L1457#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L1458 1459// AGP_CNTL1460#define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL1461#define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L1462#define AGP_CNTL__HOLD_RD_FIFO 0x00000100L1463#define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L1464#define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L1465#define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L1466#define AGP_CNTL__EN_2X_STBB 0x00000400L1467#define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L1468#define AGP_CNTL__FORCE_FULL_SBA 0x00000800L1469#define AGP_CNTL__SBA_DIS_MASK 0x00001000L1470#define AGP_CNTL__SBA_DIS 0x00001000L1471#define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L1472#define AGP_CNTL__AGP_REV_ID 0x00002000L1473#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L1474#define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L1475#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L1476#define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L1477#define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L1478#define AGP_CNTL__FORCE_INT_VREF 0x00010000L1479#define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L1480#define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L1481#define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L1482#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L1483#define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L1484#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L1485#define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L1486#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L1487#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L1488#define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L1489#define AGP_CNTL__EN_RBFCALM 0x00800000L1490#define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L1491#define AGP_CNTL__FORCE_EXT_VREF 0x01000000L1492#define AGP_CNTL__DIS_RBF_MASK 0x02000000L1493#define AGP_CNTL__DIS_RBF 0x02000000L1494#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L1495#define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L1496#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L1497#define AGP_CNTL__AGP_MISC_MASK 0xc0000000L1498 1499// AGP_CNTL1500#define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x000000001501#define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x000000081502#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x000000091503#define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a1504#define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b1505#define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c1506#define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d1507#define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e1508#define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f1509#define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x000000101510#define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x000000111511#define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x000000131512#define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x000000141513#define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x000000151514#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x000000161515#define AGP_CNTL__EN_RBFCALM__SHIFT 0x000000171516#define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x000000181517#define AGP_CNTL__DIS_RBF__SHIFT 0x000000191518#define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a1519#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b1520#define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e1521 1522// DISP_MISC_CNTL1523#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L1524#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L1525#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L1526#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L1527#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L1528#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L1529#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L1530#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L1531#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L1532#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L1533#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L1534#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L1535#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L1536#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L1537#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L1538#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L1539#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L1540#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L1541#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L1542#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L1543#define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L1544#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L1545#define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L1546#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L1547#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L1548#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L1549#define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L1550#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L1551#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L1552#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L1553 1554// DISP_PWR_MAN1555#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L1556#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L1557#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L1558#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L1559#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L1560#define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L1561#define DISP_PWR_MAN__DISP_D3_RST 0x00010000L1562#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L1563#define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L1564#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L1565#define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L1566#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L1567#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L1568#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L1569#define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L1570#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L1571#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L1572#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L1573#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L1574#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L1575#define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L1576#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L1577#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L1578#define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L1579#define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L1580#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L1581#define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L1582 1583// MC_IND_INDEX1584#define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL1585#define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L1586#define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L1587 1588// MC_IND_DATA1589#define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL1590 1591// MC_CHP_IO_CNTL_A11592#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x000000001593#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x000000011594#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x000000021595#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x000000031596#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x000000041597#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x000000051598#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x000000061599#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x000000071600#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x000000081601#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x000000091602#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a1603#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c1604#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e1605#define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x000000101606#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x000000121607#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x000000141608#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x000000161609#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x000000171610#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x000000181611#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a1612#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c1613#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e1614#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f1615 1616// MC_CHP_IO_CNTL_B11617#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x000000001618#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x000000011619#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x000000021620#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x000000031621#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x000000041622#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x000000051623#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x000000061624#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x000000071625#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x000000081626#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x000000091627#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a1628#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c1629#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e1630#define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x000000101631#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x000000121632#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x000000141633#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x000000161634#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x000000171635#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x000000181636#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a1637#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c1638#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e1639#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f1640 1641// MC_CHP_IO_CNTL_A11642#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L1643#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L1644#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L1645#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L1646#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L1647#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L1648#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L1649#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L1650#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L1651#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L1652#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L1653#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L1654#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L1655#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L1656#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L1657#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L1658#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L1659#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L1660#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L1661#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L1662#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L1663#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L1664#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L1665#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L1666#define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L1667#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L1668#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L1669#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L1670#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L1671#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L1672#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L1673#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L1674#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L1675#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L1676#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L1677#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L1678#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L1679#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L1680#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L1681 1682// MC_CHP_IO_CNTL_B11683#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L1684#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L1685#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L1686#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L1687#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L1688#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L1689#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L1690#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L1691#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L1692#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L1693#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L1694#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L1695#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L1696#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L1697#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L1698#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L1699#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L1700#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L1701#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L1702#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L1703#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L1704#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L1705#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L1706#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L1707#define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L1708#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L1709#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L1710#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L1711#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L1712#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L1713#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L1714#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L1715#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L1716#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L1717#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L1718#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L1719#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L1720#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L1721#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L1722 1723// MEM_SDRAM_MODE_REG1724#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL1725#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L1726#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L1727#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L1728#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L1729#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L1730#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L1731#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L1732#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L1733#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L1734#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L1735#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L1736#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L1737#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L1738#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L1739#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L1740#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L1741#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L1742#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L1743#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L1744#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L1745 1746// MEM_SDRAM_MODE_REG1747#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x000000001748#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x000000101749#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x000000141750#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x000000171751#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x000000181752#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x000000191753#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a1754#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b1755#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c1756#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d1757#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e1758#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f1759 1760// MEM_REFRESH_CNTL1761#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL1762#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L1763#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L1764#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L1765#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L1766#define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L1767#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L1768#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L1769#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L1770#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L1771#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L1772#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L1773#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L1774#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L1775#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L1776#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L1777#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L1778#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L1779#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L1780#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L1781#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L1782#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L1783#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L1784#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L1785#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L1786#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L1787#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L1788#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L1789 1790// MC_STATUS1791#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L1792#define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L1793#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L1794#define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L1795#define MC_STATUS__MC_IDLE_MASK 0x00000004L1796#define MC_STATUS__MC_IDLE 0x00000004L1797#define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L1798#define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L1799#define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L1800#define MC_STATUS__TEST_OUT_R_BACK 0x00000800L1801#define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L1802#define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L1803#define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L1804#define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L1805#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L1806#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L1807 1808// MDLL_CKO1809#define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L1810#define MDLL_CKO__MCKOA_SLEEP 0x00000001L1811#define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L1812#define MDLL_CKO__MCKOA_RESET 0x00000002L1813#define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL1814#define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L1815#define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L1816#define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L1817#define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L1818#define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L1819#define MDLL_CKO__MCKOA_BP_SEL 0x00008000L1820#define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L1821#define MDLL_CKO__MCKOB_SLEEP 0x00010000L1822#define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L1823#define MDLL_CKO__MCKOB_RESET 0x00020000L1824#define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L1825#define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L1826#define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L1827#define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L1828#define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L1829#define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L1830#define MDLL_CKO__MCKOB_BP_SEL 0x80000000L1831 1832// MDLL_RDCKA1833#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L1834#define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L1835#define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L1836#define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L1837#define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL1838#define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L1839#define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L1840#define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L1841#define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L1842#define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L1843#define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L1844#define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L1845#define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L1846#define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L1847#define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L1848#define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L1849#define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L1850#define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L1851#define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L1852#define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L1853#define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L1854#define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L1855#define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L1856#define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L1857#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L1858#define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L1859 1860// MDLL_RDCKB1861#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L1862#define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L1863#define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L1864#define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L1865#define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL1866#define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L1867#define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L1868#define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L1869#define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L1870#define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L1871#define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L1872#define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L1873#define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L1874#define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L1875#define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L1876#define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L1877#define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L1878#define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L1879#define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L1880#define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L1881#define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L1882#define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L1883#define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L1884#define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L1885#define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L1886#define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L1887 1888#define MDLL_R300_RDCK__MRDCKA_SLEEP 0x00000001L1889#define MDLL_R300_RDCK__MRDCKA_RESET 0x00000002L1890#define MDLL_R300_RDCK__MRDCKB_SLEEP 0x00000004L1891#define MDLL_R300_RDCK__MRDCKB_RESET 0x00000008L1892#define MDLL_R300_RDCK__MRDCKC_SLEEP 0x00000010L1893#define MDLL_R300_RDCK__MRDCKC_RESET 0x00000020L1894#define MDLL_R300_RDCK__MRDCKD_SLEEP 0x00000040L1895#define MDLL_R300_RDCK__MRDCKD_RESET 0x00000080L1896 1897#define pllCLK_PIN_CNTL 0x00011898#define pllPPLL_CNTL 0x00021899#define pllPPLL_REF_DIV 0x00031900#define pllPPLL_DIV_0 0x00041901#define pllPPLL_DIV_1 0x00051902#define pllPPLL_DIV_2 0x00061903#define pllPPLL_DIV_3 0x00071904#define pllVCLK_ECP_CNTL 0x00081905#define pllHTOTAL_CNTL 0x00091906#define pllM_SPLL_REF_FB_DIV 0x000A1907#define pllAGP_PLL_CNTL 0x000B1908#define pllSPLL_CNTL 0x000C1909#define pllSCLK_CNTL 0x000D1910#define pllMPLL_CNTL 0x000E1911#define pllMDLL_CKO 0x000F1912#define pllMDLL_RDCKA 0x00101913#define pllMDLL_RDCKB 0x00111914#define pllMCLK_CNTL 0x00121915#define pllPLL_TEST_CNTL 0x00131916#define pllCLK_PWRMGT_CNTL 0x00141917#define pllPLL_PWRMGT_CNTL 0x00151918#define pllCG_TEST_MACRO_RW_WRITE 0x00161919#define pllCG_TEST_MACRO_RW_READ 0x00171920#define pllCG_TEST_MACRO_RW_DATA 0x00181921#define pllCG_TEST_MACRO_RW_CNTL 0x00191922#define pllDISP_TEST_MACRO_RW_WRITE 0x001A1923#define pllDISP_TEST_MACRO_RW_READ 0x001B1924#define pllDISP_TEST_MACRO_RW_DATA 0x001C1925#define pllDISP_TEST_MACRO_RW_CNTL 0x001D1926#define pllSCLK_CNTL2 0x001E1927#define pllMCLK_MISC 0x001F1928#define pllTV_PLL_FINE_CNTL 0x00201929#define pllTV_PLL_CNTL 0x00211930#define pllTV_PLL_CNTL1 0x00221931#define pllTV_DTO_INCREMENTS 0x00231932#define pllSPLL_AUX_CNTL 0x00241933#define pllMPLL_AUX_CNTL 0x00251934#define pllP2PLL_CNTL 0x002A1935#define pllP2PLL_REF_DIV 0x002B1936#define pllP2PLL_DIV_0 0x002C1937#define pllPIXCLKS_CNTL 0x002D1938#define pllHTOTAL2_CNTL 0x002E1939#define pllSSPLL_CNTL 0x00301940#define pllSSPLL_REF_DIV 0x00311941#define pllSSPLL_DIV_0 0x00321942#define pllSS_INT_CNTL 0x00331943#define pllSS_TST_CNTL 0x00341944#define pllSCLK_MORE_CNTL 0x00351945 1946#define ixMC_PERF_CNTL 0x00001947#define ixMC_PERF_SEL 0x00011948#define ixMC_PERF_REGION_0 0x00021949#define ixMC_PERF_REGION_1 0x00031950#define ixMC_PERF_COUNT_0 0x00041951#define ixMC_PERF_COUNT_1 0x00051952#define ixMC_PERF_COUNT_2 0x00061953#define ixMC_PERF_COUNT_3 0x00071954#define ixMC_PERF_COUNT_MEMCH_A 0x00081955#define ixMC_PERF_COUNT_MEMCH_B 0x00091956#define ixMC_IMP_CNTL 0x000A1957#define ixMC_CHP_IO_CNTL_A0 0x000B1958#define ixMC_CHP_IO_CNTL_A1 0x000C1959#define ixMC_CHP_IO_CNTL_B0 0x000D1960#define ixMC_CHP_IO_CNTL_B1 0x000E1961#define ixMC_IMP_CNTL_0 0x000F1962#define ixTC_MISMATCH_1 0x00101963#define ixTC_MISMATCH_2 0x00111964#define ixMC_BIST_CTRL 0x00121965#define ixREG_COLLAR_WRITE 0x00131966#define ixREG_COLLAR_READ 0x00141967#define ixR300_MC_IMP_CNTL 0x00181968#define ixR300_MC_CHP_IO_CNTL_A0 0x00191969#define ixR300_MC_CHP_IO_CNTL_A1 0x001a1970#define ixR300_MC_CHP_IO_CNTL_B0 0x001b1971#define ixR300_MC_CHP_IO_CNTL_B1 0x001c1972#define ixR300_MC_CHP_IO_CNTL_C0 0x001d1973#define ixR300_MC_CHP_IO_CNTL_C1 0x001e1974#define ixR300_MC_CHP_IO_CNTL_D0 0x001f1975#define ixR300_MC_CHP_IO_CNTL_D1 0x00201976#define ixR300_MC_IMP_CNTL_0 0x00211977#define ixR300_MC_ELPIDA_CNTL 0x00221978#define ixR300_MC_CHP_IO_OE_CNTL_CD 0x00231979#define ixR300_MC_READ_CNTL_CD 0x00241980#define ixR300_MC_MC_INIT_WR_LAT_TIMER 0x00251981#define ixR300_MC_DEBUG_CNTL 0x00261982#define ixR300_MC_BIST_CNTL_0 0x00281983#define ixR300_MC_BIST_CNTL_1 0x00291984#define ixR300_MC_BIST_CNTL_2 0x002a1985#define ixR300_MC_BIST_CNTL_3 0x002b1986#define ixR300_MC_BIST_CNTL_4 0x002c1987#define ixR300_MC_BIST_CNTL_5 0x002d1988#define ixR300_MC_IMP_STATUS 0x002e1989#define ixR300_MC_DLL_CNTL 0x002f1990#define NB_TOM 0x15C1991 1992 1993#endif /* _RADEON_H */1994 1995