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1/*2 * linux/drivers/video/tgafb.h -- DEC 21030 TGA frame buffer device3 *4 * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha5 * 6 * $Id: tgafb.h,v 1.4.2.3 2000/04/04 06:44:56 mato Exp $7 *8 * This file is subject to the terms and conditions of the GNU General Public9 * License. See the file COPYING in the main directory of this archive for10 * more details.11 */12 13#ifndef TGAFB_H14#define TGAFB_H15 16/*17 * TGA hardware description (minimal)18 */19 20#define TGA_TYPE_8PLANE 021#define TGA_TYPE_24PLANE 122#define TGA_TYPE_24PLUSZ 323 24/*25 * Offsets within Memory Space26 */27 28#define TGA_ROM_OFFSET 0x000000029#define TGA_REGS_OFFSET 0x010000030#define TGA_8PLANE_FB_OFFSET 0x020000031#define TGA_24PLANE_FB_OFFSET 0x080400032#define TGA_24PLUSZ_FB_OFFSET 0x100400033 34#define TGA_FOREGROUND_REG 0x002035#define TGA_BACKGROUND_REG 0x002436#define TGA_PLANEMASK_REG 0x002837#define TGA_PIXELMASK_ONESHOT_REG 0x002c38#define TGA_MODE_REG 0x003039#define TGA_RASTEROP_REG 0x003440#define TGA_PIXELSHIFT_REG 0x003841#define TGA_DEEP_REG 0x005042#define TGA_START_REG 0x005443#define TGA_PIXELMASK_REG 0x005c44#define TGA_CURSOR_BASE_REG 0x006045#define TGA_HORIZ_REG 0x006446#define TGA_VERT_REG 0x006847#define TGA_BASE_ADDR_REG 0x006c48#define TGA_VALID_REG 0x007049#define TGA_CURSOR_XY_REG 0x007450#define TGA_INTR_STAT_REG 0x007c51#define TGA_DATA_REG 0x008052#define TGA_RAMDAC_SETUP_REG 0x00c053#define TGA_BLOCK_COLOR0_REG 0x014054#define TGA_BLOCK_COLOR1_REG 0x014455#define TGA_BLOCK_COLOR2_REG 0x014856#define TGA_BLOCK_COLOR3_REG 0x014c57#define TGA_BLOCK_COLOR4_REG 0x015058#define TGA_BLOCK_COLOR5_REG 0x015459#define TGA_BLOCK_COLOR6_REG 0x015860#define TGA_BLOCK_COLOR7_REG 0x015c61#define TGA_COPY64_SRC 0x016062#define TGA_COPY64_DST 0x016463#define TGA_CLOCK_REG 0x01e864#define TGA_RAMDAC_REG 0x01f065#define TGA_CMD_STAT_REG 0x01f866 67 68/* 69 * Useful defines for managing the registers70 */71 72#define TGA_HORIZ_ODD 0x8000000073#define TGA_HORIZ_POLARITY 0x4000000074#define TGA_HORIZ_ACT_MSB 0x3000000075#define TGA_HORIZ_BP 0x0fe0000076#define TGA_HORIZ_SYNC 0x001fc00077#define TGA_HORIZ_FP 0x00007c0078#define TGA_HORIZ_ACT_LSB 0x000001ff79 80#define TGA_VERT_SE 0x8000000081#define TGA_VERT_POLARITY 0x4000000082#define TGA_VERT_RESERVED 0x3000000083#define TGA_VERT_BP 0x0fc0000084#define TGA_VERT_SYNC 0x003f000085#define TGA_VERT_FP 0x0000f80086#define TGA_VERT_ACTIVE 0x000007ff87 88#define TGA_VALID_VIDEO 0x0189#define TGA_VALID_BLANK 0x0290#define TGA_VALID_CURSOR 0x0491 92#define TGA_MODE_SBM_8BPP 0x00093#define TGA_MODE_SBM_24BPP 0x30094 95#define TGA_MODE_SIMPLE 0x0096#define TGA_MODE_SIMPLEZ 0x1097#define TGA_MODE_OPAQUE_STIPPLE 0x0198#define TGA_MODE_OPAQUE_FILL 0x2199#define TGA_MODE_TRANSPARENT_STIPPLE 0x03100#define TGA_MODE_TRANSPARENT_FILL 0x23101#define TGA_MODE_BLOCK_STIPPLE 0x0d102#define TGA_MODE_BLOCK_FILL 0x2d103#define TGA_MODE_COPY 0x07104#define TGA_MODE_DMA_READ_COPY_ND 0x17105#define TGA_MODE_DMA_READ_COPY_D 0x37106#define TGA_MODE_DMA_WRITE_COPY 0x1f107 108 109/*110 * Useful defines for managing the ICS1562 PLL clock111 */112 113#define TGA_PLL_BASE_FREQ 14318 /* .18 */114#define TGA_PLL_MAX_FREQ 230000115 116 117/*118 * Useful defines for managing the BT485 on the 8-plane TGA119 */120 121#define BT485_READ_BIT 0x01122#define BT485_WRITE_BIT 0x00123 124#define BT485_ADDR_PAL_WRITE 0x00125#define BT485_DATA_PAL 0x02126#define BT485_PIXEL_MASK 0x04127#define BT485_ADDR_PAL_READ 0x06128#define BT485_ADDR_CUR_WRITE 0x08129#define BT485_DATA_CUR 0x0a130#define BT485_CMD_0 0x0c131#define BT485_ADDR_CUR_READ 0x0e132#define BT485_CMD_1 0x10133#define BT485_CMD_2 0x12134#define BT485_STATUS 0x14135#define BT485_CMD_3 0x14136#define BT485_CUR_RAM 0x16137#define BT485_CUR_LOW_X 0x18138#define BT485_CUR_HIGH_X 0x1a139#define BT485_CUR_LOW_Y 0x1c140#define BT485_CUR_HIGH_Y 0x1e141 142 143/*144 * Useful defines for managing the BT463 on the 24-plane TGAs/SFB+s145 */146 147#define BT463_ADDR_LO 0x0148#define BT463_ADDR_HI 0x1149#define BT463_REG_ACC 0x2150#define BT463_PALETTE 0x3151 152#define BT463_CUR_CLR_0 0x0100153#define BT463_CUR_CLR_1 0x0101154 155#define BT463_CMD_REG_0 0x0201156#define BT463_CMD_REG_1 0x0202157#define BT463_CMD_REG_2 0x0203158 159#define BT463_READ_MASK_0 0x0205160#define BT463_READ_MASK_1 0x0206161#define BT463_READ_MASK_2 0x0207162#define BT463_READ_MASK_3 0x0208163 164#define BT463_BLINK_MASK_0 0x0209165#define BT463_BLINK_MASK_1 0x020a166#define BT463_BLINK_MASK_2 0x020b167#define BT463_BLINK_MASK_3 0x020c168 169#define BT463_WINDOW_TYPE_BASE 0x0300170 171/*172 * Useful defines for managing the BT459 on the 8-plane SFB+s173 */174 175#define BT459_ADDR_LO 0x0176#define BT459_ADDR_HI 0x1177#define BT459_REG_ACC 0x2178#define BT459_PALETTE 0x3179 180#define BT459_CUR_CLR_1 0x0181181#define BT459_CUR_CLR_2 0x0182182#define BT459_CUR_CLR_3 0x0183183 184#define BT459_CMD_REG_0 0x0201185#define BT459_CMD_REG_1 0x0202186#define BT459_CMD_REG_2 0x0203187 188#define BT459_READ_MASK 0x0204189 190#define BT459_BLINK_MASK 0x0206191 192#define BT459_CUR_CMD_REG 0x0300193 194/*195 * The framebuffer driver private data.196 */197 198struct tga_par {199 /* PCI/TC device. */200 struct device *dev;201 202 /* Device dependent information. */203 void __iomem *tga_mem_base;204 void __iomem *tga_fb_base;205 void __iomem *tga_regs_base;206 u8 tga_type; /* TGA_TYPE_XXX */207 u8 tga_chip_rev; /* dc21030 revision */208 209 /* Remember blank mode. */210 u8 vesa_blanked;211 212 /* Define the video mode. */213 u32 xres, yres; /* resolution in pixels */214 u32 htimings; /* horizontal timing register */215 u32 vtimings; /* vertical timing register */216 u32 pll_freq; /* pixclock in mhz */217 u32 bits_per_pixel; /* bits per pixel */218 u32 sync_on_green; /* set if sync is on green */219 u32 palette[16];220};221 222 223/*224 * Macros for reading/writing TGA and RAMDAC registers225 */226 227static inline void228TGA_WRITE_REG(struct tga_par *par, u32 v, u32 r)229{230 writel(v, par->tga_regs_base +r);231}232 233static inline u32234TGA_READ_REG(struct tga_par *par, u32 r)235{236 return readl(par->tga_regs_base +r);237}238 239static inline void240BT485_WRITE(struct tga_par *par, u8 v, u8 r)241{242 TGA_WRITE_REG(par, r, TGA_RAMDAC_SETUP_REG);243 TGA_WRITE_REG(par, v | (r << 8), TGA_RAMDAC_REG);244}245 246static inline void247BT463_LOAD_ADDR(struct tga_par *par, u16 a)248{249 TGA_WRITE_REG(par, BT463_ADDR_LO<<2, TGA_RAMDAC_SETUP_REG);250 TGA_WRITE_REG(par, (BT463_ADDR_LO<<10) | (a & 0xff), TGA_RAMDAC_REG);251 TGA_WRITE_REG(par, BT463_ADDR_HI<<2, TGA_RAMDAC_SETUP_REG);252 TGA_WRITE_REG(par, (BT463_ADDR_HI<<10) | (a >> 8), TGA_RAMDAC_REG);253}254 255static inline void256BT463_WRITE(struct tga_par *par, u32 m, u16 a, u8 v)257{258 BT463_LOAD_ADDR(par, a);259 TGA_WRITE_REG(par, m << 2, TGA_RAMDAC_SETUP_REG);260 TGA_WRITE_REG(par, m << 10 | v, TGA_RAMDAC_REG);261}262 263static inline void264BT459_LOAD_ADDR(struct tga_par *par, u16 a)265{266 TGA_WRITE_REG(par, BT459_ADDR_LO << 2, TGA_RAMDAC_SETUP_REG);267 TGA_WRITE_REG(par, a & 0xff, TGA_RAMDAC_REG);268 TGA_WRITE_REG(par, BT459_ADDR_HI << 2, TGA_RAMDAC_SETUP_REG);269 TGA_WRITE_REG(par, a >> 8, TGA_RAMDAC_REG);270}271 272static inline void273BT459_WRITE(struct tga_par *par, u32 m, u16 a, u8 v)274{275 BT459_LOAD_ADDR(par, a);276 TGA_WRITE_REG(par, m << 2, TGA_RAMDAC_SETUP_REG);277 TGA_WRITE_REG(par, v, TGA_RAMDAC_REG);278}279 280#endif /* TGAFB_H */281