248 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver4 *5 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.6 */7#ifndef AACI_H8#define AACI_H9 10/*11 * Control and status register offsets12 * P39.13 */14#define AACI_CSCH1 0x00015#define AACI_CSCH2 0x01416#define AACI_CSCH3 0x02817#define AACI_CSCH4 0x03c18 19#define AACI_RXCR 0x000 /* 29 bits Control Rx FIFO */20#define AACI_TXCR 0x004 /* 17 bits Control Tx FIFO */21#define AACI_SR 0x008 /* 12 bits Status */22#define AACI_ISR 0x00c /* 7 bits Int Status */23#define AACI_IE 0x010 /* 7 bits Int Enable */24 25/*26 * Other registers27 */28#define AACI_SL1RX 0x05029#define AACI_SL1TX 0x05430#define AACI_SL2RX 0x05831#define AACI_SL2TX 0x05c32#define AACI_SL12RX 0x06033#define AACI_SL12TX 0x06434#define AACI_SLFR 0x068 /* slot flags */35#define AACI_SLISTAT 0x06c /* slot interrupt status */36#define AACI_SLIEN 0x070 /* slot interrupt enable */37#define AACI_INTCLR 0x074 /* interrupt clear */38#define AACI_MAINCR 0x078 /* main control */39#define AACI_RESET 0x07c /* reset control */40#define AACI_SYNC 0x080 /* sync control */41#define AACI_ALLINTS 0x084 /* all fifo interrupt status */42#define AACI_MAINFR 0x088 /* main flag register */43#define AACI_DR1 0x090 /* data read/written fifo 1 */44#define AACI_DR2 0x0b0 /* data read/written fifo 2 */45#define AACI_DR3 0x0d0 /* data read/written fifo 3 */46#define AACI_DR4 0x0f0 /* data read/written fifo 4 */47 48/*49 * TX/RX fifo control register (CR). P4850 */51#define CR_FEN (1 << 16) /* fifo enable */52#define CR_COMPACT (1 << 15) /* compact mode */53#define CR_SZ16 (0 << 13) /* 16 bits */54#define CR_SZ18 (1 << 13) /* 18 bits */55#define CR_SZ20 (2 << 13) /* 20 bits */56#define CR_SZ12 (3 << 13) /* 12 bits */57#define CR_SL12 (1 << 12)58#define CR_SL11 (1 << 11)59#define CR_SL10 (1 << 10)60#define CR_SL9 (1 << 9)61#define CR_SL8 (1 << 8)62#define CR_SL7 (1 << 7)63#define CR_SL6 (1 << 6)64#define CR_SL5 (1 << 5)65#define CR_SL4 (1 << 4)66#define CR_SL3 (1 << 3)67#define CR_SL2 (1 << 2)68#define CR_SL1 (1 << 1)69#define CR_EN (1 << 0) /* transmit enable */70 71/*72 * status register bits. P4973 */74#define SR_RXTOFE (1 << 11) /* rx timeout fifo empty */75#define SR_TXTO (1 << 10) /* rx timeout fifo nonempty */76#define SR_TXU (1 << 9) /* tx underrun */77#define SR_RXO (1 << 8) /* rx overrun */78#define SR_TXB (1 << 7) /* tx busy */79#define SR_RXB (1 << 6) /* rx busy */80#define SR_TXFF (1 << 5) /* tx fifo full */81#define SR_RXFF (1 << 4) /* rx fifo full */82#define SR_TXHE (1 << 3) /* tx fifo half empty */83#define SR_RXHF (1 << 2) /* rx fifo half full */84#define SR_TXFE (1 << 1) /* tx fifo empty */85#define SR_RXFE (1 << 0) /* rx fifo empty */86 87/*88 * interrupt status register bits.89 */90#define ISR_RXTOFEINTR (1 << 6) /* rx fifo empty */91#define ISR_URINTR (1 << 5) /* tx underflow */92#define ISR_ORINTR (1 << 4) /* rx overflow */93#define ISR_RXINTR (1 << 3) /* rx fifo */94#define ISR_TXINTR (1 << 2) /* tx fifo intr */95#define ISR_RXTOINTR (1 << 1) /* tx timeout */96#define ISR_TXCINTR (1 << 0) /* tx complete */97 98/*99 * interrupt enable register bits.100 */101#define IE_RXTOIE (1 << 6)102#define IE_URIE (1 << 5)103#define IE_ORIE (1 << 4)104#define IE_RXIE (1 << 3)105#define IE_TXIE (1 << 2)106#define IE_RXTIE (1 << 1)107#define IE_TXCIE (1 << 0)108 109/*110 * interrupt status. P51111 */112#define ISR_RXTOFE (1 << 6) /* rx timeout fifo empty */113#define ISR_UR (1 << 5) /* tx fifo underrun */114#define ISR_OR (1 << 4) /* rx fifo overrun */115#define ISR_RX (1 << 3) /* rx interrupt status */116#define ISR_TX (1 << 2) /* tx interrupt status */117#define ISR_RXTO (1 << 1) /* rx timeout */118#define ISR_TXC (1 << 0) /* tx complete */119 120/*121 * interrupt enable. P52122 */123#define IE_RXTOFE (1 << 6) /* rx timeout fifo empty */124#define IE_UR (1 << 5) /* tx fifo underrun */125#define IE_OR (1 << 4) /* rx fifo overrun */126#define IE_RX (1 << 3) /* rx interrupt status */127#define IE_TX (1 << 2) /* tx interrupt status */128#define IE_RXTO (1 << 1) /* rx timeout */129#define IE_TXC (1 << 0) /* tx complete */130 131/*132 * slot flag register bits. P56133 */134#define SLFR_RWIS (1 << 13) /* raw wake-up interrupt status */135#define SLFR_RGPIOINTR (1 << 12) /* raw gpio interrupt */136#define SLFR_12TXE (1 << 11) /* slot 12 tx empty */137#define SLFR_12RXV (1 << 10) /* slot 12 rx valid */138#define SLFR_2TXE (1 << 9) /* slot 2 tx empty */139#define SLFR_2RXV (1 << 8) /* slot 2 rx valid */140#define SLFR_1TXE (1 << 7) /* slot 1 tx empty */141#define SLFR_1RXV (1 << 6) /* slot 1 rx valid */142#define SLFR_12TXB (1 << 5) /* slot 12 tx busy */143#define SLFR_12RXB (1 << 4) /* slot 12 rx busy */144#define SLFR_2TXB (1 << 3) /* slot 2 tx busy */145#define SLFR_2RXB (1 << 2) /* slot 2 rx busy */146#define SLFR_1TXB (1 << 1) /* slot 1 tx busy */147#define SLFR_1RXB (1 << 0) /* slot 1 rx busy */148 149/*150 * Interrupt clear register.151 */152#define ICLR_RXTOFEC4 (1 << 12)153#define ICLR_RXTOFEC3 (1 << 11)154#define ICLR_RXTOFEC2 (1 << 10)155#define ICLR_RXTOFEC1 (1 << 9)156#define ICLR_TXUEC4 (1 << 8)157#define ICLR_TXUEC3 (1 << 7)158#define ICLR_TXUEC2 (1 << 6)159#define ICLR_TXUEC1 (1 << 5)160#define ICLR_RXOEC4 (1 << 4)161#define ICLR_RXOEC3 (1 << 3)162#define ICLR_RXOEC2 (1 << 2)163#define ICLR_RXOEC1 (1 << 1)164#define ICLR_WISC (1 << 0)165 166/*167 * Main control register bits. P62168 */169#define MAINCR_SCRA(x) ((x) << 10) /* secondary codec reg access */170#define MAINCR_DMAEN (1 << 9) /* dma enable */171#define MAINCR_SL12TXEN (1 << 8) /* slot 12 transmit enable */172#define MAINCR_SL12RXEN (1 << 7) /* slot 12 receive enable */173#define MAINCR_SL2TXEN (1 << 6) /* slot 2 transmit enable */174#define MAINCR_SL2RXEN (1 << 5) /* slot 2 receive enable */175#define MAINCR_SL1TXEN (1 << 4) /* slot 1 transmit enable */176#define MAINCR_SL1RXEN (1 << 3) /* slot 1 receive enable */177#define MAINCR_LPM (1 << 2) /* low power mode */178#define MAINCR_LOOPBK (1 << 1) /* loopback */179#define MAINCR_IE (1 << 0) /* aaci interface enable */180 181/*182 * Reset register bits. P65183 */184#define RESET_NRST (1 << 0)185 186/*187 * Sync register bits. P65188 */189#define SYNC_FORCE (1 << 0)190 191/*192 * Main flag register bits. P66193 */194#define MAINFR_TXB (1 << 1) /* transmit busy */195#define MAINFR_RXB (1 << 0) /* receive busy */196 197 198 199struct aaci_runtime {200 void __iomem *base;201 void __iomem *fifo;202 spinlock_t lock;203 204 struct ac97_pcm *pcm;205 int pcm_open;206 207 u32 cr;208 struct snd_pcm_substream *substream;209 210 unsigned int period; /* byte size of a "period" */211 212 /*213 * PIO support214 */215 void *start;216 void *end;217 void *ptr;218 int bytes;219 unsigned int fifo_bytes;220};221 222struct aaci {223 struct amba_device *dev;224 struct snd_card *card;225 void __iomem *base;226 unsigned int fifo_depth;227 unsigned int users;228 struct mutex irq_lock;229 230 /* AC'97 */231 struct mutex ac97_sem;232 struct snd_ac97_bus *ac97_bus;233 struct snd_ac97 *ac97;234 235 u32 maincr;236 237 struct aaci_runtime playback;238 struct aaci_runtime capture;239 240 struct snd_pcm *pcm;241};242 243#define ACSTREAM_FRONT 0244#define ACSTREAM_SURROUND 1245#define ACSTREAM_LFE 2246 247#endif248