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1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef SOUND_FIREWIRE_DICE_INTERFACE_H_INCLUDED3#define SOUND_FIREWIRE_DICE_INTERFACE_H_INCLUDED4 5/*6 * DICE device interface definitions7 */8 9/*10 * Generally, all registers can be read like memory, i.e., with quadlet read or11 * block read transactions with at least quadlet-aligned offset and length.12 * Writes are not allowed except where noted; quadlet-sized registers must be13 * written with a quadlet write transaction.14 *15 * All values are in big endian. The DICE firmware runs on a little-endian CPU16 * and just byte-swaps _all_ quadlets on the bus, so values without endianness17 * (e.g. strings) get scrambled and must be byte-swapped again by the driver.18 */19 20/*21 * Streaming is handled by the "DICE driver" interface. Its registers are22 * located in this private address space.23 */24#define DICE_PRIVATE_SPACE 0xffffe0000000uLL25 26/*27 * The registers are organized in several sections, which are organized28 * separately to allow them to be extended individually. Whether a register is29 * supported can be detected by checking its offset against its section's size.30 *31 * The section offset values are relative to DICE_PRIVATE_SPACE; the offset/32 * size values are measured in quadlets. Read-only.33 */34#define DICE_GLOBAL_OFFSET 0x0035#define DICE_GLOBAL_SIZE 0x0436#define DICE_TX_OFFSET 0x0837#define DICE_TX_SIZE 0x0c38#define DICE_RX_OFFSET 0x1039#define DICE_RX_SIZE 0x1440#define DICE_EXT_SYNC_OFFSET 0x1841#define DICE_EXT_SYNC_SIZE 0x1c42#define DICE_UNUSED2_OFFSET 0x2043#define DICE_UNUSED2_SIZE 0x2444 45/*46 * Global settings.47 */48 49/*50 * Stores the full 64-bit address (node ID and offset in the node's address51 * space) where the device will send notifications. Must be changed with52 * a compare/swap transaction by the owner. This register is automatically53 * cleared on a bus reset.54 */55#define GLOBAL_OWNER 0x00056#define OWNER_NO_OWNER 0xffff000000000000uLL57#define OWNER_NODE_SHIFT 4858 59/*60 * A bitmask with asynchronous events; read-only. When any event(s) happen,61 * the bits of previous events are cleared, and the value of this register is62 * also written to the address stored in the owner register.63 */64#define GLOBAL_NOTIFICATION 0x00865/* Some registers in the Rx/Tx sections may have changed. */66#define NOTIFY_RX_CFG_CHG 0x0000000167#define NOTIFY_TX_CFG_CHG 0x0000000268/* Lock status of the current clock source may have changed. */69#define NOTIFY_LOCK_CHG 0x0000001070/* Write to the clock select register has been finished. */71#define NOTIFY_CLOCK_ACCEPTED 0x0000002072/* Lock status of some clock source has changed. */73#define NOTIFY_EXT_STATUS 0x0000004074/* Other bits may be used for device-specific events. */75 76/*77 * A name that can be customized for each device; read/write. Padded with zero78 * bytes. Quadlets are byte-swapped. The encoding is whatever the host driver79 * happens to be using.80 */81#define GLOBAL_NICK_NAME 0x00c82#define NICK_NAME_SIZE 6483 84/*85 * The current sample rate and clock source; read/write. Whether a clock86 * source or sample rate is supported is device-specific; the internal clock87 * source is always available. Low/mid/high = up to 48/96/192 kHz. This88 * register can be changed even while streams are running.89 */90#define GLOBAL_CLOCK_SELECT 0x04c91#define CLOCK_SOURCE_MASK 0x000000ff92#define CLOCK_SOURCE_AES1 0x0000000093#define CLOCK_SOURCE_AES2 0x0000000194#define CLOCK_SOURCE_AES3 0x0000000295#define CLOCK_SOURCE_AES4 0x0000000396#define CLOCK_SOURCE_AES_ANY 0x0000000497#define CLOCK_SOURCE_ADAT 0x0000000598#define CLOCK_SOURCE_TDIF 0x0000000699#define CLOCK_SOURCE_WC 0x00000007100#define CLOCK_SOURCE_ARX1 0x00000008101#define CLOCK_SOURCE_ARX2 0x00000009102#define CLOCK_SOURCE_ARX3 0x0000000a103#define CLOCK_SOURCE_ARX4 0x0000000b104#define CLOCK_SOURCE_INTERNAL 0x0000000c105#define CLOCK_RATE_MASK 0x0000ff00106#define CLOCK_RATE_32000 0x00000000107#define CLOCK_RATE_44100 0x00000100108#define CLOCK_RATE_48000 0x00000200109#define CLOCK_RATE_88200 0x00000300110#define CLOCK_RATE_96000 0x00000400111#define CLOCK_RATE_176400 0x00000500112#define CLOCK_RATE_192000 0x00000600113#define CLOCK_RATE_ANY_LOW 0x00000700114#define CLOCK_RATE_ANY_MID 0x00000800115#define CLOCK_RATE_ANY_HIGH 0x00000900116#define CLOCK_RATE_NONE 0x00000a00117#define CLOCK_RATE_SHIFT 8118 119/*120 * Enable streaming; read/write. Writing a non-zero value (re)starts all121 * streams that have a valid iso channel set; zero stops all streams. The122 * streams' parameters must be configured before starting. This register is123 * automatically cleared on a bus reset.124 */125#define GLOBAL_ENABLE 0x050126 127/*128 * Status of the sample clock; read-only.129 */130#define GLOBAL_STATUS 0x054131/* The current clock source is locked. */132#define STATUS_SOURCE_LOCKED 0x00000001133/* The actual sample rate; CLOCK_RATE_32000-_192000 or _NONE. */134#define STATUS_NOMINAL_RATE_MASK 0x0000ff00135 136/*137 * Status of all clock sources; read-only.138 */139#define GLOBAL_EXTENDED_STATUS 0x058140/*141 * The _LOCKED bits always show the current status; any change generates142 * a notification.143 */144#define EXT_STATUS_AES1_LOCKED 0x00000001145#define EXT_STATUS_AES2_LOCKED 0x00000002146#define EXT_STATUS_AES3_LOCKED 0x00000004147#define EXT_STATUS_AES4_LOCKED 0x00000008148#define EXT_STATUS_ADAT_LOCKED 0x00000010149#define EXT_STATUS_TDIF_LOCKED 0x00000020150#define EXT_STATUS_ARX1_LOCKED 0x00000040151#define EXT_STATUS_ARX2_LOCKED 0x00000080152#define EXT_STATUS_ARX3_LOCKED 0x00000100153#define EXT_STATUS_ARX4_LOCKED 0x00000200154#define EXT_STATUS_WC_LOCKED 0x00000400155/*156 * The _SLIP bits do not generate notifications; a set bit indicates that an157 * error occurred since the last time when this register was read with158 * a quadlet read transaction.159 */160#define EXT_STATUS_AES1_SLIP 0x00010000161#define EXT_STATUS_AES2_SLIP 0x00020000162#define EXT_STATUS_AES3_SLIP 0x00040000163#define EXT_STATUS_AES4_SLIP 0x00080000164#define EXT_STATUS_ADAT_SLIP 0x00100000165#define EXT_STATUS_TDIF_SLIP 0x00200000166#define EXT_STATUS_ARX1_SLIP 0x00400000167#define EXT_STATUS_ARX2_SLIP 0x00800000168#define EXT_STATUS_ARX3_SLIP 0x01000000169#define EXT_STATUS_ARX4_SLIP 0x02000000170#define EXT_STATUS_WC_SLIP 0x04000000171 172/*173 * The measured rate of the current clock source, in Hz; read-only.174 */175#define GLOBAL_SAMPLE_RATE 0x05c176 177/*178 * Some old firmware versions do not have the following global registers.179 * Windows drivers produced by TCAT lost backward compatibility in its180 * early release because they can handle firmware only which supports the181 * following registers.182 */183 184/*185 * The version of the DICE driver specification that this device conforms to;186 * read-only.187 */188#define GLOBAL_VERSION 0x060189 190/*191 * Supported sample rates and clock sources; read-only.192 */193#define GLOBAL_CLOCK_CAPABILITIES 0x064194#define CLOCK_CAP_RATE_32000 0x00000001195#define CLOCK_CAP_RATE_44100 0x00000002196#define CLOCK_CAP_RATE_48000 0x00000004197#define CLOCK_CAP_RATE_88200 0x00000008198#define CLOCK_CAP_RATE_96000 0x00000010199#define CLOCK_CAP_RATE_176400 0x00000020200#define CLOCK_CAP_RATE_192000 0x00000040201#define CLOCK_CAP_SOURCE_AES1 0x00010000202#define CLOCK_CAP_SOURCE_AES2 0x00020000203#define CLOCK_CAP_SOURCE_AES3 0x00040000204#define CLOCK_CAP_SOURCE_AES4 0x00080000205#define CLOCK_CAP_SOURCE_AES_ANY 0x00100000206#define CLOCK_CAP_SOURCE_ADAT 0x00200000207#define CLOCK_CAP_SOURCE_TDIF 0x00400000208#define CLOCK_CAP_SOURCE_WC 0x00800000209#define CLOCK_CAP_SOURCE_ARX1 0x01000000210#define CLOCK_CAP_SOURCE_ARX2 0x02000000211#define CLOCK_CAP_SOURCE_ARX3 0x04000000212#define CLOCK_CAP_SOURCE_ARX4 0x08000000213#define CLOCK_CAP_SOURCE_INTERNAL 0x10000000214 215/*216 * Names of all clock sources; read-only. Quadlets are byte-swapped. Names217 * are separated with one backslash, the list is terminated with two218 * backslashes. Unused clock sources are included.219 */220#define GLOBAL_CLOCK_SOURCE_NAMES 0x068221#define CLOCK_SOURCE_NAMES_SIZE 256222 223/*224 * Capture stream settings. This section includes the number/size registers225 * and the registers of all streams.226 */227 228/*229 * The number of supported capture streams; read-only.230 */231#define TX_NUMBER 0x000232 233/*234 * The size of one stream's register block, in quadlets; read-only. The235 * registers of the first stream follow immediately afterwards; the registers236 * of the following streams are offset by this register's value.237 */238#define TX_SIZE 0x004239 240/*241 * The isochronous channel number on which packets are sent, or -1 if the242 * stream is not to be used; read/write.243 */244#define TX_ISOCHRONOUS 0x008245 246/*247 * The number of audio channels; read-only. There will be one quadlet per248 * channel; the first channel is the first quadlet in a data block.249 */250#define TX_NUMBER_AUDIO 0x00c251 252/*253 * The number of MIDI ports, 0-8; read-only. If > 0, there will be one254 * additional quadlet in each data block, following the audio quadlets.255 */256#define TX_NUMBER_MIDI 0x010257 258/*259 * The speed at which the packets are sent, SCODE_100-_400; read/write.260 * SCODE_800 is only available in Dice III.261 */262#define TX_SPEED 0x014263 264/*265 * Names of all audio channels; read-only. Quadlets are byte-swapped. Names266 * are separated with one backslash, the list is terminated with two267 * backslashes.268 */269#define TX_NAMES 0x018270#define TX_NAMES_SIZE 256271 272/*273 * Audio IEC60958 capabilities; read-only. Bitmask with one bit per audio274 * channel.275 */276#define TX_AC3_CAPABILITIES 0x118277 278/*279 * Send audio data with IEC60958 label; read/write. Bitmask with one bit per280 * audio channel. This register can be changed even while the stream is281 * running.282 */283#define TX_AC3_ENABLE 0x11c284 285/*286 * Playback stream settings. This section includes the number/size registers287 * and the registers of all streams.288 */289 290/*291 * The number of supported playback streams; read-only.292 */293#define RX_NUMBER 0x000294 295/*296 * The size of one stream's register block, in quadlets; read-only. The297 * registers of the first stream follow immediately afterwards; the registers298 * of the following streams are offset by this register's value.299 */300#define RX_SIZE 0x004301 302/*303 * The isochronous channel number on which packets are received, or -1 if the304 * stream is not to be used; read/write.305 */306#define RX_ISOCHRONOUS 0x008307 308/*309 * Index of first quadlet to be interpreted; read/write. If > 0, that many310 * quadlets at the beginning of each data block will be ignored, and all the311 * audio and MIDI quadlets will follow.312 */313#define RX_SEQ_START 0x00c314 315/*316 * The number of audio channels; read-only. There will be one quadlet per317 * channel.318 */319#define RX_NUMBER_AUDIO 0x010320 321/*322 * The number of MIDI ports, 0-8; read-only. If > 0, there will be one323 * additional quadlet in each data block, following the audio quadlets.324 */325#define RX_NUMBER_MIDI 0x014326 327/*328 * Names of all audio channels; read-only. Quadlets are byte-swapped. Names329 * are separated with one backslash, the list is terminated with two330 * backslashes.331 */332#define RX_NAMES 0x018333#define RX_NAMES_SIZE 256334 335/*336 * Audio IEC60958 capabilities; read-only. Bitmask with one bit per audio337 * channel.338 */339#define RX_AC3_CAPABILITIES 0x118340 341/*342 * Receive audio data with IEC60958 label; read/write. Bitmask with one bit343 * per audio channel. This register can be changed even while the stream is344 * running.345 */346#define RX_AC3_ENABLE 0x11c347 348/*349 * Extended synchronization information.350 * This section can be read completely with a block read request.351 */352 353/*354 * Current clock source; read-only.355 */356#define EXT_SYNC_CLOCK_SOURCE 0x000357 358/*359 * Clock source is locked (boolean); read-only.360 */361#define EXT_SYNC_LOCKED 0x004362 363/*364 * Current sample rate (CLOCK_RATE_* >> CLOCK_RATE_SHIFT), _32000-_192000 or365 * _NONE; read-only.366 */367#define EXT_SYNC_RATE 0x008368 369/*370 * ADAT user data bits; read-only.371 */372#define EXT_SYNC_ADAT_USER_DATA 0x00c373/* The data bits, if available. */374#define ADAT_USER_DATA_MASK 0x0f375/* The data bits are not available. */376#define ADAT_USER_DATA_NO_DATA 0x10377 378#endif379