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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * digi00x.h - a part of driver for Digidesign Digi 002/003 family4 *5 * Copyright (c) 2014-2015 Takashi Sakamoto6 */7 8#ifndef SOUND_DIGI00X_H_INCLUDED9#define SOUND_DIGI00X_H_INCLUDED10 11#include <linux/compat.h>12#include <linux/device.h>13#include <linux/firewire.h>14#include <linux/module.h>15#include <linux/mod_devicetable.h>16#include <linux/delay.h>17#include <linux/slab.h>18#include <linux/sched/signal.h>19 20#include <sound/core.h>21#include <sound/initval.h>22#include <sound/info.h>23#include <sound/pcm.h>24#include <sound/pcm_params.h>25#include <sound/firewire.h>26#include <sound/hwdep.h>27#include <sound/rawmidi.h>28 29#include "../lib.h"30#include "../iso-resources.h"31#include "../amdtp-stream.h"32 33struct snd_dg00x {34 struct snd_card *card;35 struct fw_unit *unit;36 37 struct mutex mutex;38 spinlock_t lock;39 40 struct amdtp_stream tx_stream;41 struct fw_iso_resources tx_resources;42 43 struct amdtp_stream rx_stream;44 struct fw_iso_resources rx_resources;45 46 unsigned int substreams_counter;47 48 /* for uapi */49 int dev_lock_count;50 bool dev_lock_changed;51 wait_queue_head_t hwdep_wait;52 53 /* For asynchronous messages. */54 struct fw_address_handler async_handler;55 u32 msg;56 57 /* Console models have additional MIDI ports for control surface. */58 bool is_console;59 60 struct amdtp_domain domain;61};62 63#define DG00X_ADDR_BASE 0xffffe0000000ull64 65#define DG00X_OFFSET_STREAMING_STATE 0x000066#define DG00X_OFFSET_STREAMING_SET 0x000467/* unknown but address in host space 0x0008 */68/* For LSB of the address 0x000c */69/* unknown 0x0010 */70#define DG00X_OFFSET_MESSAGE_ADDR 0x001471/* For LSB of the address 0x0018 */72/* unknown 0x001c */73/* unknown 0x0020 */74/* not used 0x0024--0x00ff */75#define DG00X_OFFSET_ISOC_CHANNELS 0x010076/* unknown 0x0104 */77/* unknown 0x0108 */78/* unknown 0x010c */79#define DG00X_OFFSET_LOCAL_RATE 0x011080#define DG00X_OFFSET_EXTERNAL_RATE 0x011481#define DG00X_OFFSET_CLOCK_SOURCE 0x011882#define DG00X_OFFSET_OPT_IFACE_MODE 0x011c83/* unknown 0x0120 */84/* Mixer control on/off 0x0124 */85/* unknown 0x0128 */86#define DG00X_OFFSET_DETECT_EXTERNAL 0x012c87/* unknown 0x0138 */88#define DG00X_OFFSET_MMC 0x040089 90enum snd_dg00x_rate {91 SND_DG00X_RATE_44100 = 0,92 SND_DG00X_RATE_48000,93 SND_DG00X_RATE_88200,94 SND_DG00X_RATE_96000,95 SND_DG00X_RATE_COUNT,96};97 98enum snd_dg00x_clock {99 SND_DG00X_CLOCK_INTERNAL = 0,100 SND_DG00X_CLOCK_SPDIF,101 SND_DG00X_CLOCK_ADAT,102 SND_DG00X_CLOCK_WORD,103 SND_DG00X_CLOCK_COUNT,104};105 106enum snd_dg00x_optical_mode {107 SND_DG00X_OPT_IFACE_MODE_ADAT = 0,108 SND_DG00X_OPT_IFACE_MODE_SPDIF,109 SND_DG00X_OPT_IFACE_MODE_COUNT,110};111 112#define DOT_MIDI_IN_PORTS 1113#define DOT_MIDI_OUT_PORTS 2114 115int amdtp_dot_init(struct amdtp_stream *s, struct fw_unit *unit,116 enum amdtp_stream_direction dir);117int amdtp_dot_set_parameters(struct amdtp_stream *s, unsigned int rate,118 unsigned int pcm_channels);119void amdtp_dot_reset(struct amdtp_stream *s);120int amdtp_dot_add_pcm_hw_constraints(struct amdtp_stream *s,121 struct snd_pcm_runtime *runtime);122void amdtp_dot_midi_trigger(struct amdtp_stream *s, unsigned int port,123 struct snd_rawmidi_substream *midi);124 125int snd_dg00x_transaction_register(struct snd_dg00x *dg00x);126int snd_dg00x_transaction_reregister(struct snd_dg00x *dg00x);127void snd_dg00x_transaction_unregister(struct snd_dg00x *dg00x);128 129extern const unsigned int snd_dg00x_stream_rates[SND_DG00X_RATE_COUNT];130extern const unsigned int snd_dg00x_stream_pcm_channels[SND_DG00X_RATE_COUNT];131int snd_dg00x_stream_get_external_rate(struct snd_dg00x *dg00x,132 unsigned int *rate);133int snd_dg00x_stream_get_local_rate(struct snd_dg00x *dg00x,134 unsigned int *rate);135int snd_dg00x_stream_set_local_rate(struct snd_dg00x *dg00x, unsigned int rate);136int snd_dg00x_stream_get_clock(struct snd_dg00x *dg00x,137 enum snd_dg00x_clock *clock);138int snd_dg00x_stream_check_external_clock(struct snd_dg00x *dg00x,139 bool *detect);140int snd_dg00x_stream_init_duplex(struct snd_dg00x *dg00x);141int snd_dg00x_stream_reserve_duplex(struct snd_dg00x *dg00x, unsigned int rate,142 unsigned int frames_per_period,143 unsigned int frames_per_buffer);144int snd_dg00x_stream_start_duplex(struct snd_dg00x *dg00x);145void snd_dg00x_stream_stop_duplex(struct snd_dg00x *dg00x);146void snd_dg00x_stream_update_duplex(struct snd_dg00x *dg00x);147void snd_dg00x_stream_destroy_duplex(struct snd_dg00x *dg00x);148 149void snd_dg00x_stream_lock_changed(struct snd_dg00x *dg00x);150int snd_dg00x_stream_lock_try(struct snd_dg00x *dg00x);151void snd_dg00x_stream_lock_release(struct snd_dg00x *dg00x);152 153void snd_dg00x_proc_init(struct snd_dg00x *dg00x);154 155int snd_dg00x_create_pcm_devices(struct snd_dg00x *dg00x);156 157int snd_dg00x_create_midi_devices(struct snd_dg00x *dg00x);158 159int snd_dg00x_create_hwdep_device(struct snd_dg00x *dg00x);160#endif161