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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * HD-audio stream operations4 */5 6#include <linux/kernel.h>7#include <linux/delay.h>8#include <linux/export.h>9#include <linux/clocksource.h>10#include <sound/compress_driver.h>11#include <sound/core.h>12#include <sound/pcm.h>13#include <sound/hdaudio.h>14#include <sound/hda_register.h>15#include "trace.h"16 17/*18 * the hdac_stream library is intended to be used with the following19 * transitions. The states are not formally defined in the code but loosely20 * inspired by boolean variables. Note that the 'prepared' field is not used21 * in this library but by the callers during the hw_params/prepare transitions22 *23 * |24 * stream_init() |25 * v26 * +--+-------+27 * | unused |28 * +--+----+--+29 * | ^30 * stream_assign() | | stream_release()31 * v |32 * +--+----+--+33 * | opened |34 * +--+----+--+35 * | ^36 * stream_reset() | |37 * stream_setup() | | stream_cleanup()38 * v |39 * +--+----+--+40 * | prepared |41 * +--+----+--+42 * | ^43 * stream_start() | | stream_stop()44 * v |45 * +--+----+--+46 * | running |47 * +----------+48 */49 50/**51 * snd_hdac_get_stream_stripe_ctl - get stripe control value52 * @bus: HD-audio core bus53 * @substream: PCM substream54 */55int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,56 struct snd_pcm_substream *substream)57{58 struct snd_pcm_runtime *runtime = substream->runtime;59 unsigned int channels = runtime->channels,60 rate = runtime->rate,61 bits_per_sample = runtime->sample_bits,62 max_sdo_lines, value, sdo_line;63 64 /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */65 max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;66 67 /* following is from HD audio spec */68 for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {69 if (rate > 48000)70 value = (channels * bits_per_sample *71 (rate / 48000)) / sdo_line;72 else73 value = (channels * bits_per_sample) / sdo_line;74 75 if (value >= bus->sdo_limit)76 break;77 }78 79 /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */80 return sdo_line >> 1;81}82EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);83 84/**85 * snd_hdac_stream_init - initialize each stream (aka device)86 * @bus: HD-audio core bus87 * @azx_dev: HD-audio core stream object to initialize88 * @idx: stream index number89 * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)90 * @tag: the tag id to assign91 *92 * Assign the starting bdl address to each stream (device) and initialize.93 */94void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,95 int idx, int direction, int tag)96{97 azx_dev->bus = bus;98 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */99 azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);100 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */101 azx_dev->sd_int_sta_mask = 1 << idx;102 azx_dev->index = idx;103 azx_dev->direction = direction;104 azx_dev->stream_tag = tag;105 snd_hdac_dsp_lock_init(azx_dev);106 list_add_tail(&azx_dev->list, &bus->stream_list);107 108 if (bus->spbcap) {109 azx_dev->spib_addr = bus->spbcap + AZX_SPB_BASE +110 AZX_SPB_INTERVAL * idx +111 AZX_SPB_SPIB;112 113 azx_dev->fifo_addr = bus->spbcap + AZX_SPB_BASE +114 AZX_SPB_INTERVAL * idx +115 AZX_SPB_MAXFIFO;116 }117 118 if (bus->drsmcap)119 azx_dev->dpibr_addr = bus->drsmcap + AZX_DRSM_BASE +120 AZX_DRSM_INTERVAL * idx;121}122EXPORT_SYMBOL_GPL(snd_hdac_stream_init);123 124/**125 * snd_hdac_stream_start - start a stream126 * @azx_dev: HD-audio core stream to start127 *128 * Start a stream, set start_wallclk and set the running flag.129 */130void snd_hdac_stream_start(struct hdac_stream *azx_dev)131{132 struct hdac_bus *bus = azx_dev->bus;133 int stripe_ctl;134 135 trace_snd_hdac_stream_start(bus, azx_dev);136 137 azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);138 139 /* enable SIE */140 snd_hdac_chip_updatel(bus, INTCTL,141 1 << azx_dev->index,142 1 << azx_dev->index);143 /* set stripe control */144 if (azx_dev->stripe) {145 if (azx_dev->substream)146 stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);147 else148 stripe_ctl = 0;149 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,150 stripe_ctl);151 }152 /* set DMA start and interrupt mask */153 if (bus->access_sdnctl_in_dword)154 snd_hdac_stream_updatel(azx_dev, SD_CTL,155 0, SD_CTL_DMA_START | SD_INT_MASK);156 else157 snd_hdac_stream_updateb(azx_dev, SD_CTL,158 0, SD_CTL_DMA_START | SD_INT_MASK);159 azx_dev->running = true;160}161EXPORT_SYMBOL_GPL(snd_hdac_stream_start);162 163/**164 * snd_hdac_stream_clear - helper to clear stream registers and stop DMA transfers165 * @azx_dev: HD-audio core stream to stop166 */167static void snd_hdac_stream_clear(struct hdac_stream *azx_dev)168{169 snd_hdac_stream_updateb(azx_dev, SD_CTL,170 SD_CTL_DMA_START | SD_INT_MASK, 0);171 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */172 if (azx_dev->stripe)173 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);174 azx_dev->running = false;175}176 177/**178 * snd_hdac_stream_stop - stop a stream179 * @azx_dev: HD-audio core stream to stop180 *181 * Stop a stream DMA and disable stream interrupt182 */183void snd_hdac_stream_stop(struct hdac_stream *azx_dev)184{185 trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);186 187 snd_hdac_stream_clear(azx_dev);188 /* disable SIE */189 snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);190}191EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);192 193/**194 * snd_hdac_stop_streams - stop all streams195 * @bus: HD-audio core bus196 */197void snd_hdac_stop_streams(struct hdac_bus *bus)198{199 struct hdac_stream *stream;200 201 list_for_each_entry(stream, &bus->stream_list, list)202 snd_hdac_stream_stop(stream);203}204EXPORT_SYMBOL_GPL(snd_hdac_stop_streams);205 206/**207 * snd_hdac_stop_streams_and_chip - stop all streams and chip if running208 * @bus: HD-audio core bus209 */210void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus)211{212 213 if (bus->chip_init) {214 snd_hdac_stop_streams(bus);215 snd_hdac_bus_stop_chip(bus);216 }217}218EXPORT_SYMBOL_GPL(snd_hdac_stop_streams_and_chip);219 220/**221 * snd_hdac_stream_reset - reset a stream222 * @azx_dev: HD-audio core stream to reset223 */224void snd_hdac_stream_reset(struct hdac_stream *azx_dev)225{226 unsigned char val;227 int dma_run_state;228 229 snd_hdac_stream_clear(azx_dev);230 231 dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START;232 233 snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);234 235 /* wait for hardware to report that the stream entered reset */236 snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, (val & SD_CTL_STREAM_RESET), 3, 300);237 238 if (azx_dev->bus->dma_stop_delay && dma_run_state)239 udelay(azx_dev->bus->dma_stop_delay);240 241 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_CTL_STREAM_RESET, 0);242 243 /* wait for hardware to report that the stream is out of reset */244 snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, !(val & SD_CTL_STREAM_RESET), 3, 300);245 246 /* reset first position - may not be synced with hw at this time */247 if (azx_dev->posbuf)248 *azx_dev->posbuf = 0;249}250EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);251 252/**253 * snd_hdac_stream_setup - set up the SD for streaming254 * @azx_dev: HD-audio core stream to set up255 * @code_loading: Whether the stream is for PCM or code-loading.256 */257int snd_hdac_stream_setup(struct hdac_stream *azx_dev, bool code_loading)258{259 struct hdac_bus *bus = azx_dev->bus;260 struct snd_pcm_runtime *runtime;261 unsigned int val;262 u16 reg;263 int ret;264 265 if (azx_dev->substream)266 runtime = azx_dev->substream->runtime;267 else268 runtime = NULL;269 /* make sure the run bit is zero for SD */270 snd_hdac_stream_clear(azx_dev);271 /* program the stream_tag */272 val = snd_hdac_stream_readl(azx_dev, SD_CTL);273 val = (val & ~SD_CTL_STREAM_TAG_MASK) |274 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);275 if (!bus->snoop)276 val |= SD_CTL_TRAFFIC_PRIO;277 snd_hdac_stream_writel(azx_dev, SD_CTL, val);278 279 /* program the length of samples in cyclic buffer */280 snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);281 282 /* program the stream format */283 /* this value needs to be the same as the one programmed */284 snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);285 286 /* program the stream LVI (last valid index) of the BDL */287 snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);288 289 /* program the BDL address */290 /* lower BDL address */291 snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);292 /* upper BDL address */293 snd_hdac_stream_writel(azx_dev, SD_BDLPU,294 upper_32_bits(azx_dev->bdl.addr));295 296 /* enable the position buffer */297 if (bus->use_posbuf && bus->posbuf.addr) {298 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))299 snd_hdac_chip_writel(bus, DPLBASE,300 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);301 }302 303 /* set the interrupt enable bits in the descriptor control register */304 snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);305 306 if (!code_loading) {307 /* Once SDxFMT is set, the controller programs SDxFIFOS to non-zero value. */308 ret = snd_hdac_stream_readw_poll(azx_dev, SD_FIFOSIZE, reg,309 reg & AZX_SD_FIFOSIZE_MASK, 3, 300);310 if (ret)311 dev_dbg(bus->dev, "polling SD_FIFOSIZE 0x%04x failed: %d\n",312 AZX_REG_SD_FIFOSIZE, ret);313 azx_dev->fifo_size = reg;314 }315 316 /* when LPIB delay correction gives a small negative value,317 * we ignore it; currently set the threshold statically to318 * 64 frames319 */320 if (runtime && runtime->period_size > 64)321 azx_dev->delay_negative_threshold =322 -frames_to_bytes(runtime, 64);323 else324 azx_dev->delay_negative_threshold = 0;325 326 /* wallclk has 24Mhz clock source */327 if (runtime)328 azx_dev->period_wallclk = (((runtime->period_size * 24000) /329 runtime->rate) * 1000);330 331 return 0;332}333EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);334 335/**336 * snd_hdac_stream_cleanup - cleanup a stream337 * @azx_dev: HD-audio core stream to clean up338 */339void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)340{341 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);342 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);343 snd_hdac_stream_writel(azx_dev, SD_CTL, 0);344 azx_dev->bufsize = 0;345 azx_dev->period_bytes = 0;346 azx_dev->format_val = 0;347}348EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);349 350/**351 * snd_hdac_stream_assign - assign a stream for the PCM352 * @bus: HD-audio core bus353 * @substream: PCM substream to assign354 *355 * Look for an unused stream for the given PCM substream, assign it356 * and return the stream object. If no stream is free, returns NULL.357 * The function tries to keep using the same stream object when it's used358 * beforehand. Also, when bus->reverse_assign flag is set, the last free359 * or matching entry is returned. This is needed for some strange codecs.360 */361struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,362 struct snd_pcm_substream *substream)363{364 struct hdac_stream *azx_dev;365 struct hdac_stream *res = NULL;366 367 /* make a non-zero unique key for the substream */368 int key = (substream->number << 2) | (substream->stream + 1);369 370 if (substream->pcm)371 key |= (substream->pcm->device << 16);372 373 spin_lock_irq(&bus->reg_lock);374 list_for_each_entry(azx_dev, &bus->stream_list, list) {375 if (azx_dev->direction != substream->stream)376 continue;377 if (azx_dev->opened)378 continue;379 if (azx_dev->assigned_key == key) {380 res = azx_dev;381 break;382 }383 if (!res || bus->reverse_assign)384 res = azx_dev;385 }386 if (res) {387 res->opened = 1;388 res->running = 0;389 res->assigned_key = key;390 res->substream = substream;391 }392 spin_unlock_irq(&bus->reg_lock);393 return res;394}395EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);396 397/**398 * snd_hdac_stream_release_locked - release the assigned stream399 * @azx_dev: HD-audio core stream to release400 *401 * Release the stream that has been assigned by snd_hdac_stream_assign().402 * The bus->reg_lock needs to be taken at a higher level403 */404void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev)405{406 azx_dev->opened = 0;407 azx_dev->running = 0;408 azx_dev->substream = NULL;409}410EXPORT_SYMBOL_GPL(snd_hdac_stream_release_locked);411 412/**413 * snd_hdac_stream_release - release the assigned stream414 * @azx_dev: HD-audio core stream to release415 *416 * Release the stream that has been assigned by snd_hdac_stream_assign().417 */418void snd_hdac_stream_release(struct hdac_stream *azx_dev)419{420 struct hdac_bus *bus = azx_dev->bus;421 422 spin_lock_irq(&bus->reg_lock);423 snd_hdac_stream_release_locked(azx_dev);424 spin_unlock_irq(&bus->reg_lock);425}426EXPORT_SYMBOL_GPL(snd_hdac_stream_release);427 428/**429 * snd_hdac_get_stream - return hdac_stream based on stream_tag and430 * direction431 *432 * @bus: HD-audio core bus433 * @dir: direction for the stream to be found434 * @stream_tag: stream tag for stream to be found435 */436struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,437 int dir, int stream_tag)438{439 struct hdac_stream *s;440 441 list_for_each_entry(s, &bus->stream_list, list) {442 if (s->direction == dir && s->stream_tag == stream_tag)443 return s;444 }445 446 return NULL;447}448EXPORT_SYMBOL_GPL(snd_hdac_get_stream);449 450/*451 * set up a BDL entry452 */453static int setup_bdle(struct hdac_bus *bus,454 struct snd_dma_buffer *dmab,455 struct hdac_stream *azx_dev, __le32 **bdlp,456 int ofs, int size, int with_ioc)457{458 __le32 *bdl = *bdlp;459 460 while (size > 0) {461 dma_addr_t addr;462 int chunk;463 464 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)465 return -EINVAL;466 467 addr = snd_sgbuf_get_addr(dmab, ofs);468 /* program the address field of the BDL entry */469 bdl[0] = cpu_to_le32((u32)addr);470 bdl[1] = cpu_to_le32(upper_32_bits(addr));471 /* program the size field of the BDL entry */472 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);473 /* one BDLE cannot cross 4K boundary on CTHDA chips */474 if (bus->align_bdle_4k) {475 u32 remain = 0x1000 - (ofs & 0xfff);476 477 if (chunk > remain)478 chunk = remain;479 }480 bdl[2] = cpu_to_le32(chunk);481 /* program the IOC to enable interrupt482 * only when the whole fragment is processed483 */484 size -= chunk;485 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);486 bdl += 4;487 azx_dev->frags++;488 ofs += chunk;489 }490 *bdlp = bdl;491 return ofs;492}493 494/**495 * snd_hdac_stream_setup_periods - set up BDL entries496 * @azx_dev: HD-audio core stream to set up497 *498 * Set up the buffer descriptor table of the given stream based on the499 * period and buffer sizes of the assigned PCM substream.500 */501int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)502{503 struct hdac_bus *bus = azx_dev->bus;504 struct snd_pcm_substream *substream = azx_dev->substream;505 struct snd_compr_stream *cstream = azx_dev->cstream;506 struct snd_pcm_runtime *runtime = NULL;507 struct snd_dma_buffer *dmab;508 __le32 *bdl;509 int i, ofs, periods, period_bytes;510 int pos_adj, pos_align;511 512 if (substream) {513 runtime = substream->runtime;514 dmab = snd_pcm_get_dma_buf(substream);515 } else if (cstream) {516 dmab = snd_pcm_get_dma_buf(cstream);517 } else {518 WARN(1, "No substream or cstream assigned\n");519 return -EINVAL;520 }521 522 /* reset BDL address */523 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);524 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);525 526 period_bytes = azx_dev->period_bytes;527 periods = azx_dev->bufsize / period_bytes;528 529 /* program the initial BDL entries */530 bdl = (__le32 *)azx_dev->bdl.area;531 ofs = 0;532 azx_dev->frags = 0;533 534 pos_adj = bus->bdl_pos_adj;535 if (runtime && !azx_dev->no_period_wakeup && pos_adj > 0) {536 pos_align = pos_adj;537 pos_adj = DIV_ROUND_UP(pos_adj * runtime->rate, 48000);538 if (!pos_adj)539 pos_adj = pos_align;540 else541 pos_adj = roundup(pos_adj, pos_align);542 pos_adj = frames_to_bytes(runtime, pos_adj);543 if (pos_adj >= period_bytes) {544 dev_warn(bus->dev, "Too big adjustment %d\n",545 pos_adj);546 pos_adj = 0;547 } else {548 ofs = setup_bdle(bus, dmab, azx_dev,549 &bdl, ofs, pos_adj, true);550 if (ofs < 0)551 goto error;552 }553 } else554 pos_adj = 0;555 556 for (i = 0; i < periods; i++) {557 if (i == periods - 1 && pos_adj)558 ofs = setup_bdle(bus, dmab, azx_dev,559 &bdl, ofs, period_bytes - pos_adj, 0);560 else561 ofs = setup_bdle(bus, dmab, azx_dev,562 &bdl, ofs, period_bytes,563 !azx_dev->no_period_wakeup);564 if (ofs < 0)565 goto error;566 }567 return 0;568 569 error:570 dev_dbg(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",571 azx_dev->bufsize, period_bytes);572 return -EINVAL;573}574EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);575 576/**577 * snd_hdac_stream_set_params - set stream parameters578 * @azx_dev: HD-audio core stream for which parameters are to be set579 * @format_val: format value parameter580 *581 * Setup the HD-audio core stream parameters from substream of the stream582 * and passed format value583 */584int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,585 unsigned int format_val)586{587 struct snd_pcm_substream *substream = azx_dev->substream;588 struct snd_compr_stream *cstream = azx_dev->cstream;589 unsigned int bufsize, period_bytes;590 unsigned int no_period_wakeup;591 int err;592 593 if (substream) {594 bufsize = snd_pcm_lib_buffer_bytes(substream);595 period_bytes = snd_pcm_lib_period_bytes(substream);596 no_period_wakeup = substream->runtime->no_period_wakeup;597 } else if (cstream) {598 bufsize = cstream->runtime->buffer_size;599 period_bytes = cstream->runtime->fragment_size;600 no_period_wakeup = 0;601 } else {602 return -EINVAL;603 }604 605 if (bufsize != azx_dev->bufsize ||606 period_bytes != azx_dev->period_bytes ||607 format_val != azx_dev->format_val ||608 no_period_wakeup != azx_dev->no_period_wakeup) {609 azx_dev->bufsize = bufsize;610 azx_dev->period_bytes = period_bytes;611 azx_dev->format_val = format_val;612 azx_dev->no_period_wakeup = no_period_wakeup;613 err = snd_hdac_stream_setup_periods(azx_dev);614 if (err < 0)615 return err;616 }617 return 0;618}619EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);620 621static u64 azx_cc_read(const struct cyclecounter *cc)622{623 struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);624 625 return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);626}627 628static void azx_timecounter_init(struct hdac_stream *azx_dev,629 bool force, u64 last)630{631 struct timecounter *tc = &azx_dev->tc;632 struct cyclecounter *cc = &azx_dev->cc;633 u64 nsec;634 635 cc->read = azx_cc_read;636 cc->mask = CLOCKSOURCE_MASK(32);637 638 /*639 * Calculate the optimal mult/shift values. The counter wraps640 * around after ~178.9 seconds.641 */642 clocks_calc_mult_shift(&cc->mult, &cc->shift, 24000000,643 NSEC_PER_SEC, 178);644 645 nsec = 0; /* audio time is elapsed time since trigger */646 timecounter_init(tc, cc, nsec);647 if (force) {648 /*649 * force timecounter to use predefined value,650 * used for synchronized starts651 */652 tc->cycle_last = last;653 }654}655 656/**657 * snd_hdac_stream_timecounter_init - initialize time counter658 * @azx_dev: HD-audio core stream (master stream)659 * @streams: bit flags of streams to set up660 * @start: true for PCM trigger start, false for other cases661 *662 * Initializes the time counter of streams marked by the bit flags (each663 * bit corresponds to the stream index).664 * The trigger timestamp of PCM substream assigned to the given stream is665 * updated accordingly, too.666 */667void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,668 unsigned int streams, bool start)669{670 struct hdac_bus *bus = azx_dev->bus;671 struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;672 struct hdac_stream *s;673 bool inited = false;674 u64 cycle_last = 0;675 676 if (!start)677 goto skip;678 679 list_for_each_entry(s, &bus->stream_list, list) {680 if ((streams & (1 << s->index))) {681 azx_timecounter_init(s, inited, cycle_last);682 if (!inited) {683 inited = true;684 cycle_last = s->tc.cycle_last;685 }686 }687 }688 689skip:690 snd_pcm_gettime(runtime, &runtime->trigger_tstamp);691 runtime->trigger_tstamp_latched = true;692}693EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);694 695/**696 * snd_hdac_stream_sync_trigger - turn on/off stream sync register697 * @azx_dev: HD-audio core stream (master stream)698 * @set: true = set, false = clear699 * @streams: bit flags of streams to sync700 * @reg: the stream sync register address701 */702void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,703 unsigned int streams, unsigned int reg)704{705 struct hdac_bus *bus = azx_dev->bus;706 unsigned int val;707 708 if (!reg)709 reg = AZX_REG_SSYNC;710 val = _snd_hdac_chip_readl(bus, reg);711 if (set)712 val |= streams;713 else714 val &= ~streams;715 _snd_hdac_chip_writel(bus, reg, val);716}717EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);718 719/**720 * snd_hdac_stream_sync - sync with start/stop trigger operation721 * @azx_dev: HD-audio core stream (master stream)722 * @start: true = start, false = stop723 * @streams: bit flags of streams to sync724 *725 * For @start = true, wait until all FIFOs get ready.726 * For @start = false, wait until all RUN bits are cleared.727 */728void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,729 unsigned int streams)730{731 struct hdac_bus *bus = azx_dev->bus;732 int nwait, timeout;733 struct hdac_stream *s;734 735 for (timeout = 5000; timeout; timeout--) {736 nwait = 0;737 list_for_each_entry(s, &bus->stream_list, list) {738 if (!(streams & (1 << s->index)))739 continue;740 741 if (start) {742 /* check FIFO gets ready */743 if (!(snd_hdac_stream_readb(s, SD_STS) &744 SD_STS_FIFO_READY))745 nwait++;746 } else {747 /* check RUN bit is cleared */748 if (snd_hdac_stream_readb(s, SD_CTL) &749 SD_CTL_DMA_START) {750 nwait++;751 /*752 * Perform stream reset if DMA RUN753 * bit not cleared within given timeout754 */755 if (timeout == 1)756 snd_hdac_stream_reset(s);757 }758 }759 }760 if (!nwait)761 break;762 cpu_relax();763 }764}765EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);766 767/**768 * snd_hdac_stream_spbcap_enable - enable SPIB for a stream769 * @bus: HD-audio core bus770 * @enable: flag to enable/disable SPIB771 * @index: stream index for which SPIB need to be enabled772 */773void snd_hdac_stream_spbcap_enable(struct hdac_bus *bus,774 bool enable, int index)775{776 u32 mask = 0;777 778 if (!bus->spbcap) {779 dev_err(bus->dev, "Address of SPB capability is NULL\n");780 return;781 }782 783 mask |= (1 << index);784 785 if (enable)786 snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, mask);787 else788 snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, 0);789}790EXPORT_SYMBOL_GPL(snd_hdac_stream_spbcap_enable);791 792/**793 * snd_hdac_stream_set_spib - sets the spib value of a stream794 * @bus: HD-audio core bus795 * @azx_dev: hdac_stream796 * @value: spib value to set797 */798int snd_hdac_stream_set_spib(struct hdac_bus *bus,799 struct hdac_stream *azx_dev, u32 value)800{801 if (!bus->spbcap) {802 dev_err(bus->dev, "Address of SPB capability is NULL\n");803 return -EINVAL;804 }805 806 writel(value, azx_dev->spib_addr);807 808 return 0;809}810EXPORT_SYMBOL_GPL(snd_hdac_stream_set_spib);811 812/**813 * snd_hdac_stream_get_spbmaxfifo - gets the spib value of a stream814 * @bus: HD-audio core bus815 * @azx_dev: hdac_stream816 *817 * Return maxfifo for the stream818 */819int snd_hdac_stream_get_spbmaxfifo(struct hdac_bus *bus,820 struct hdac_stream *azx_dev)821{822 if (!bus->spbcap) {823 dev_err(bus->dev, "Address of SPB capability is NULL\n");824 return -EINVAL;825 }826 827 return readl(azx_dev->fifo_addr);828}829EXPORT_SYMBOL_GPL(snd_hdac_stream_get_spbmaxfifo);830 831/**832 * snd_hdac_stream_drsm_enable - enable DMA resume for a stream833 * @bus: HD-audio core bus834 * @enable: flag to enable/disable DRSM835 * @index: stream index for which DRSM need to be enabled836 */837void snd_hdac_stream_drsm_enable(struct hdac_bus *bus,838 bool enable, int index)839{840 u32 mask = 0;841 842 if (!bus->drsmcap) {843 dev_err(bus->dev, "Address of DRSM capability is NULL\n");844 return;845 }846 847 mask |= (1 << index);848 849 if (enable)850 snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, mask);851 else852 snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, 0);853}854EXPORT_SYMBOL_GPL(snd_hdac_stream_drsm_enable);855 856/*857 * snd_hdac_stream_wait_drsm - wait for HW to clear RSM for a stream858 * @azx_dev: HD-audio core stream to await RSM for859 *860 * Returns 0 on success and -ETIMEDOUT upon a timeout.861 */862int snd_hdac_stream_wait_drsm(struct hdac_stream *azx_dev)863{864 struct hdac_bus *bus = azx_dev->bus;865 u32 mask, reg;866 int ret;867 868 mask = 1 << azx_dev->index;869 870 ret = read_poll_timeout(snd_hdac_reg_readl, reg, !(reg & mask), 250, 2000, false, bus,871 bus->drsmcap + AZX_REG_DRSM_CTL);872 if (ret)873 dev_dbg(bus->dev, "polling RSM 0x%08x failed: %d\n", mask, ret);874 return ret;875}876EXPORT_SYMBOL_GPL(snd_hdac_stream_wait_drsm);877 878/**879 * snd_hdac_stream_set_dpibr - sets the dpibr value of a stream880 * @bus: HD-audio core bus881 * @azx_dev: hdac_stream882 * @value: dpib value to set883 */884int snd_hdac_stream_set_dpibr(struct hdac_bus *bus,885 struct hdac_stream *azx_dev, u32 value)886{887 if (!bus->drsmcap) {888 dev_err(bus->dev, "Address of DRSM capability is NULL\n");889 return -EINVAL;890 }891 892 writel(value, azx_dev->dpibr_addr);893 894 return 0;895}896EXPORT_SYMBOL_GPL(snd_hdac_stream_set_dpibr);897 898/**899 * snd_hdac_stream_set_lpib - sets the lpib value of a stream900 * @azx_dev: hdac_stream901 * @value: lpib value to set902 */903int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value)904{905 snd_hdac_stream_writel(azx_dev, SD_LPIB, value);906 907 return 0;908}909EXPORT_SYMBOL_GPL(snd_hdac_stream_set_lpib);910 911#ifdef CONFIG_SND_HDA_DSP_LOADER912/**913 * snd_hdac_dsp_prepare - prepare for DSP loading914 * @azx_dev: HD-audio core stream used for DSP loading915 * @format: HD-audio stream format916 * @byte_size: data chunk byte size917 * @bufp: allocated buffer918 *919 * Allocate the buffer for the given size and set up the given stream for920 * DSP loading. Returns the stream tag (>= 0), or a negative error code.921 */922int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,923 unsigned int byte_size, struct snd_dma_buffer *bufp)924{925 struct hdac_bus *bus = azx_dev->bus;926 __le32 *bdl;927 int err;928 929 snd_hdac_dsp_lock(azx_dev);930 spin_lock_irq(&bus->reg_lock);931 if (azx_dev->running || azx_dev->locked) {932 spin_unlock_irq(&bus->reg_lock);933 err = -EBUSY;934 goto unlock;935 }936 azx_dev->locked = true;937 spin_unlock_irq(&bus->reg_lock);938 939 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev,940 byte_size, bufp);941 if (err < 0)942 goto err_alloc;943 944 azx_dev->substream = NULL;945 azx_dev->bufsize = byte_size;946 azx_dev->period_bytes = byte_size;947 azx_dev->format_val = format;948 949 snd_hdac_stream_reset(azx_dev);950 951 /* reset BDL address */952 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);953 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);954 955 azx_dev->frags = 0;956 bdl = (__le32 *)azx_dev->bdl.area;957 err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);958 if (err < 0)959 goto error;960 961 snd_hdac_stream_setup(azx_dev, true);962 snd_hdac_dsp_unlock(azx_dev);963 return azx_dev->stream_tag;964 965 error:966 snd_dma_free_pages(bufp);967 err_alloc:968 spin_lock_irq(&bus->reg_lock);969 azx_dev->locked = false;970 spin_unlock_irq(&bus->reg_lock);971 unlock:972 snd_hdac_dsp_unlock(azx_dev);973 return err;974}975EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);976 977/**978 * snd_hdac_dsp_trigger - start / stop DSP loading979 * @azx_dev: HD-audio core stream used for DSP loading980 * @start: trigger start or stop981 */982void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)983{984 if (start)985 snd_hdac_stream_start(azx_dev);986 else987 snd_hdac_stream_stop(azx_dev);988}989EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);990 991/**992 * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal993 * @azx_dev: HD-audio core stream used for DSP loading994 * @dmab: buffer used by DSP loading995 */996void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,997 struct snd_dma_buffer *dmab)998{999 struct hdac_bus *bus = azx_dev->bus;1000 1001 if (!dmab->area || !azx_dev->locked)1002 return;1003 1004 snd_hdac_dsp_lock(azx_dev);1005 /* reset BDL address */1006 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);1007 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);1008 snd_hdac_stream_writel(azx_dev, SD_CTL, 0);1009 azx_dev->bufsize = 0;1010 azx_dev->period_bytes = 0;1011 azx_dev->format_val = 0;1012 1013 snd_dma_free_pages(dmab);1014 dmab->area = NULL;1015 1016 spin_lock_irq(&bus->reg_lock);1017 azx_dev->locked = false;1018 spin_unlock_irq(&bus->reg_lock);1019 snd_hdac_dsp_unlock(azx_dev);1020}1021EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);1022#endif /* CONFIG_SND_HDA_DSP_LOADER */1023