2205 lines · c
1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>4 * Routines for control of CS4231(A)/CS4232/InterWave & compatible chips5 *6 * Bugs:7 * - sometimes record brokes playback with WSS portion of8 * Yamaha OPL3-SA3 chip9 * - CS4231 (GUS MAX) - still trouble with occasional noises10 * - broken initialization?11 */12 13#include <linux/delay.h>14#include <linux/pm.h>15#include <linux/init.h>16#include <linux/interrupt.h>17#include <linux/slab.h>18#include <linux/ioport.h>19#include <linux/module.h>20#include <linux/io.h>21#include <sound/core.h>22#include <sound/wss.h>23#include <sound/pcm_params.h>24#include <sound/tlv.h>25 26#include <asm/dma.h>27#include <asm/irq.h>28 29MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");30MODULE_DESCRIPTION("Routines for control of CS4231(A)/CS4232/InterWave & compatible chips");31MODULE_LICENSE("GPL");32 33#if 034#define SNDRV_DEBUG_MCE35#endif36 37/*38 * Some variables39 */40 41static const unsigned char freq_bits[14] = {42 /* 5510 */ 0x00 | CS4231_XTAL2,43 /* 6620 */ 0x0E | CS4231_XTAL2,44 /* 8000 */ 0x00 | CS4231_XTAL1,45 /* 9600 */ 0x0E | CS4231_XTAL1,46 /* 11025 */ 0x02 | CS4231_XTAL2,47 /* 16000 */ 0x02 | CS4231_XTAL1,48 /* 18900 */ 0x04 | CS4231_XTAL2,49 /* 22050 */ 0x06 | CS4231_XTAL2,50 /* 27042 */ 0x04 | CS4231_XTAL1,51 /* 32000 */ 0x06 | CS4231_XTAL1,52 /* 33075 */ 0x0C | CS4231_XTAL2,53 /* 37800 */ 0x08 | CS4231_XTAL2,54 /* 44100 */ 0x0A | CS4231_XTAL2,55 /* 48000 */ 0x0C | CS4231_XTAL156};57 58static const unsigned int rates[14] = {59 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,60 27042, 32000, 33075, 37800, 44100, 4800061};62 63static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {64 .count = ARRAY_SIZE(rates),65 .list = rates,66 .mask = 0,67};68 69static int snd_wss_xrate(struct snd_pcm_runtime *runtime)70{71 return snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,72 &hw_constraints_rates);73}74 75static const unsigned char snd_wss_original_image[32] =76{77 0x00, /* 00/00 - lic */78 0x00, /* 01/01 - ric */79 0x9f, /* 02/02 - la1ic */80 0x9f, /* 03/03 - ra1ic */81 0x9f, /* 04/04 - la2ic */82 0x9f, /* 05/05 - ra2ic */83 0xbf, /* 06/06 - loc */84 0xbf, /* 07/07 - roc */85 0x20, /* 08/08 - pdfr */86 CS4231_AUTOCALIB, /* 09/09 - ic */87 0x00, /* 0a/10 - pc */88 0x00, /* 0b/11 - ti */89 CS4231_MODE2, /* 0c/12 - mi */90 0xfc, /* 0d/13 - lbc */91 0x00, /* 0e/14 - pbru */92 0x00, /* 0f/15 - pbrl */93 0x80, /* 10/16 - afei */94 0x01, /* 11/17 - afeii */95 0x9f, /* 12/18 - llic */96 0x9f, /* 13/19 - rlic */97 0x00, /* 14/20 - tlb */98 0x00, /* 15/21 - thb */99 0x00, /* 16/22 - la3mic/reserved */100 0x00, /* 17/23 - ra3mic/reserved */101 0x00, /* 18/24 - afs */102 0x00, /* 19/25 - lamoc/version */103 0xcf, /* 1a/26 - mioc */104 0x00, /* 1b/27 - ramoc/reserved */105 0x20, /* 1c/28 - cdfr */106 0x00, /* 1d/29 - res4 */107 0x00, /* 1e/30 - cbru */108 0x00, /* 1f/31 - cbrl */109};110 111static const unsigned char snd_opti93x_original_image[32] =112{113 0x00, /* 00/00 - l_mixout_outctrl */114 0x00, /* 01/01 - r_mixout_outctrl */115 0x88, /* 02/02 - l_cd_inctrl */116 0x88, /* 03/03 - r_cd_inctrl */117 0x88, /* 04/04 - l_a1/fm_inctrl */118 0x88, /* 05/05 - r_a1/fm_inctrl */119 0x80, /* 06/06 - l_dac_inctrl */120 0x80, /* 07/07 - r_dac_inctrl */121 0x00, /* 08/08 - ply_dataform_reg */122 0x00, /* 09/09 - if_conf */123 0x00, /* 0a/10 - pin_ctrl */124 0x00, /* 0b/11 - err_init_reg */125 0x0a, /* 0c/12 - id_reg */126 0x00, /* 0d/13 - reserved */127 0x00, /* 0e/14 - ply_upcount_reg */128 0x00, /* 0f/15 - ply_lowcount_reg */129 0x88, /* 10/16 - reserved/l_a1_inctrl */130 0x88, /* 11/17 - reserved/r_a1_inctrl */131 0x88, /* 12/18 - l_line_inctrl */132 0x88, /* 13/19 - r_line_inctrl */133 0x88, /* 14/20 - l_mic_inctrl */134 0x88, /* 15/21 - r_mic_inctrl */135 0x80, /* 16/22 - l_out_outctrl */136 0x80, /* 17/23 - r_out_outctrl */137 0x00, /* 18/24 - reserved */138 0x00, /* 19/25 - reserved */139 0x00, /* 1a/26 - reserved */140 0x00, /* 1b/27 - reserved */141 0x00, /* 1c/28 - cap_dataform_reg */142 0x00, /* 1d/29 - reserved */143 0x00, /* 1e/30 - cap_upcount_reg */144 0x00 /* 1f/31 - cap_lowcount_reg */145};146 147/*148 * Basic I/O functions149 */150 151static inline void wss_outb(struct snd_wss *chip, u8 offset, u8 val)152{153 outb(val, chip->port + offset);154}155 156static inline u8 wss_inb(struct snd_wss *chip, u8 offset)157{158 return inb(chip->port + offset);159}160 161static void snd_wss_wait(struct snd_wss *chip)162{163 int timeout;164 165 for (timeout = 250;166 timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);167 timeout--)168 udelay(100);169}170 171static void snd_wss_dout(struct snd_wss *chip, unsigned char reg,172 unsigned char value)173{174 int timeout;175 176 for (timeout = 250;177 timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);178 timeout--)179 udelay(10);180 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);181 wss_outb(chip, CS4231P(REG), value);182 mb();183}184 185void snd_wss_out(struct snd_wss *chip, unsigned char reg, unsigned char value)186{187 snd_wss_wait(chip);188#ifdef CONFIG_SND_DEBUG189 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)190 dev_dbg(chip->card->dev,191 "out: auto calibration time out - reg = 0x%x, value = 0x%x\n",192 reg, value);193#endif194 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);195 wss_outb(chip, CS4231P(REG), value);196 chip->image[reg] = value;197 mb();198 dev_dbg(chip->card->dev, "codec out - reg 0x%x = 0x%x\n",199 chip->mce_bit | reg, value);200}201EXPORT_SYMBOL(snd_wss_out);202 203unsigned char snd_wss_in(struct snd_wss *chip, unsigned char reg)204{205 snd_wss_wait(chip);206#ifdef CONFIG_SND_DEBUG207 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)208 dev_dbg(chip->card->dev,209 "in: auto calibration time out - reg = 0x%x\n", reg);210#endif211 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);212 mb();213 return wss_inb(chip, CS4231P(REG));214}215EXPORT_SYMBOL(snd_wss_in);216 217void snd_cs4236_ext_out(struct snd_wss *chip, unsigned char reg,218 unsigned char val)219{220 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);221 wss_outb(chip, CS4231P(REG),222 reg | (chip->image[CS4236_EXT_REG] & 0x01));223 wss_outb(chip, CS4231P(REG), val);224 chip->eimage[CS4236_REG(reg)] = val;225#if 0226 dev_dbg(chip->card->dev, "ext out : reg = 0x%x, val = 0x%x\n", reg, val);227#endif228}229EXPORT_SYMBOL(snd_cs4236_ext_out);230 231unsigned char snd_cs4236_ext_in(struct snd_wss *chip, unsigned char reg)232{233 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);234 wss_outb(chip, CS4231P(REG),235 reg | (chip->image[CS4236_EXT_REG] & 0x01));236#if 1237 return wss_inb(chip, CS4231P(REG));238#else239 {240 unsigned char res;241 res = wss_inb(chip, CS4231P(REG));242 dev_dbg(chip->card->dev, "ext in : reg = 0x%x, val = 0x%x\n",243 reg, res);244 return res;245 }246#endif247}248EXPORT_SYMBOL(snd_cs4236_ext_in);249 250#if 0251 252static void snd_wss_debug(struct snd_wss *chip)253{254 dev_dbg(chip->card->dev,255 "CS4231 REGS: INDEX = 0x%02x "256 " STATUS = 0x%02x\n",257 wss_inb(chip, CS4231P(REGSEL)),258 wss_inb(chip, CS4231P(STATUS)));259 dev_dbg(chip->card->dev,260 " 0x00: left input = 0x%02x "261 " 0x10: alt 1 (CFIG 2) = 0x%02x\n",262 snd_wss_in(chip, 0x00),263 snd_wss_in(chip, 0x10));264 dev_dbg(chip->card->dev,265 " 0x01: right input = 0x%02x "266 " 0x11: alt 2 (CFIG 3) = 0x%02x\n",267 snd_wss_in(chip, 0x01),268 snd_wss_in(chip, 0x11));269 dev_dbg(chip->card->dev,270 " 0x02: GF1 left input = 0x%02x "271 " 0x12: left line in = 0x%02x\n",272 snd_wss_in(chip, 0x02),273 snd_wss_in(chip, 0x12));274 dev_dbg(chip->card->dev,275 " 0x03: GF1 right input = 0x%02x "276 " 0x13: right line in = 0x%02x\n",277 snd_wss_in(chip, 0x03),278 snd_wss_in(chip, 0x13));279 dev_dbg(chip->card->dev,280 " 0x04: CD left input = 0x%02x "281 " 0x14: timer low = 0x%02x\n",282 snd_wss_in(chip, 0x04),283 snd_wss_in(chip, 0x14));284 dev_dbg(chip->card->dev,285 " 0x05: CD right input = 0x%02x "286 " 0x15: timer high = 0x%02x\n",287 snd_wss_in(chip, 0x05),288 snd_wss_in(chip, 0x15));289 dev_dbg(chip->card->dev,290 " 0x06: left output = 0x%02x "291 " 0x16: left MIC (PnP) = 0x%02x\n",292 snd_wss_in(chip, 0x06),293 snd_wss_in(chip, 0x16));294 dev_dbg(chip->card->dev,295 " 0x07: right output = 0x%02x "296 " 0x17: right MIC (PnP) = 0x%02x\n",297 snd_wss_in(chip, 0x07),298 snd_wss_in(chip, 0x17));299 dev_dbg(chip->card->dev,300 " 0x08: playback format = 0x%02x "301 " 0x18: IRQ status = 0x%02x\n",302 snd_wss_in(chip, 0x08),303 snd_wss_in(chip, 0x18));304 dev_dbg(chip->card->dev,305 " 0x09: iface (CFIG 1) = 0x%02x "306 " 0x19: left line out = 0x%02x\n",307 snd_wss_in(chip, 0x09),308 snd_wss_in(chip, 0x19));309 dev_dbg(chip->card->dev,310 " 0x0a: pin control = 0x%02x "311 " 0x1a: mono control = 0x%02x\n",312 snd_wss_in(chip, 0x0a),313 snd_wss_in(chip, 0x1a));314 dev_dbg(chip->card->dev,315 " 0x0b: init & status = 0x%02x "316 " 0x1b: right line out = 0x%02x\n",317 snd_wss_in(chip, 0x0b),318 snd_wss_in(chip, 0x1b));319 dev_dbg(chip->card->dev,320 " 0x0c: revision & mode = 0x%02x "321 " 0x1c: record format = 0x%02x\n",322 snd_wss_in(chip, 0x0c),323 snd_wss_in(chip, 0x1c));324 dev_dbg(chip->card->dev,325 " 0x0d: loopback = 0x%02x "326 " 0x1d: var freq (PnP) = 0x%02x\n",327 snd_wss_in(chip, 0x0d),328 snd_wss_in(chip, 0x1d));329 dev_dbg(chip->card->dev,330 " 0x0e: ply upr count = 0x%02x "331 " 0x1e: ply lwr count = 0x%02x\n",332 snd_wss_in(chip, 0x0e),333 snd_wss_in(chip, 0x1e));334 dev_dbg(chip->card->dev,335 " 0x0f: rec upr count = 0x%02x "336 " 0x1f: rec lwr count = 0x%02x\n",337 snd_wss_in(chip, 0x0f),338 snd_wss_in(chip, 0x1f));339}340 341#endif342 343/*344 * CS4231 detection / MCE routines345 */346 347static void snd_wss_busy_wait(struct snd_wss *chip)348{349 int timeout;350 351 /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */352 for (timeout = 5; timeout > 0; timeout--)353 wss_inb(chip, CS4231P(REGSEL));354 /* end of cleanup sequence */355 for (timeout = 25000;356 timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);357 timeout--)358 udelay(10);359}360 361void snd_wss_mce_up(struct snd_wss *chip)362{363 unsigned long flags;364 int timeout;365 366 snd_wss_wait(chip);367#ifdef CONFIG_SND_DEBUG368 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)369 dev_dbg(chip->card->dev,370 "mce_up - auto calibration time out (0)\n");371#endif372 spin_lock_irqsave(&chip->reg_lock, flags);373 chip->mce_bit |= CS4231_MCE;374 timeout = wss_inb(chip, CS4231P(REGSEL));375 if (timeout == 0x80)376 dev_dbg(chip->card->dev,377 "mce_up [0x%lx]: serious init problem - codec still busy\n",378 chip->port);379 if (!(timeout & CS4231_MCE))380 wss_outb(chip, CS4231P(REGSEL),381 chip->mce_bit | (timeout & 0x1f));382 spin_unlock_irqrestore(&chip->reg_lock, flags);383}384EXPORT_SYMBOL(snd_wss_mce_up);385 386void snd_wss_mce_down(struct snd_wss *chip)387{388 unsigned long flags;389 unsigned long end_time;390 int timeout;391 int hw_mask = WSS_HW_CS4231_MASK | WSS_HW_CS4232_MASK | WSS_HW_AD1848;392 393 snd_wss_busy_wait(chip);394 395#ifdef CONFIG_SND_DEBUG396 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)397 dev_dbg(chip->card->dev,398 "mce_down [0x%lx] - auto calibration time out (0)\n",399 (long)CS4231P(REGSEL));400#endif401 spin_lock_irqsave(&chip->reg_lock, flags);402 chip->mce_bit &= ~CS4231_MCE;403 timeout = wss_inb(chip, CS4231P(REGSEL));404 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));405 spin_unlock_irqrestore(&chip->reg_lock, flags);406 if (timeout == 0x80)407 dev_dbg(chip->card->dev,408 "mce_down [0x%lx]: serious init problem - codec still busy\n",409 chip->port);410 if ((timeout & CS4231_MCE) == 0 || !(chip->hardware & hw_mask))411 return;412 413 /*414 * Wait for (possible -- during init auto-calibration may not be set)415 * calibration process to start. Needs up to 5 sample periods on AD1848416 * which at the slowest possible rate of 5.5125 kHz means 907 us.417 */418 msleep(1);419 420 dev_dbg(chip->card->dev, "(1) jiffies = %lu\n", jiffies);421 422 /* check condition up to 250 ms */423 end_time = jiffies + msecs_to_jiffies(250);424 while (snd_wss_in(chip, CS4231_TEST_INIT) &425 CS4231_CALIB_IN_PROGRESS) {426 427 if (time_after(jiffies, end_time)) {428 dev_err(chip->card->dev,429 "mce_down - auto calibration time out (2)\n");430 return;431 }432 msleep(1);433 }434 435 dev_dbg(chip->card->dev, "(2) jiffies = %lu\n", jiffies);436 437 /* check condition up to 100 ms */438 end_time = jiffies + msecs_to_jiffies(100);439 while (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {440 if (time_after(jiffies, end_time)) {441 dev_err(chip->card->dev,442 "mce_down - auto calibration time out (3)\n");443 return;444 }445 msleep(1);446 }447 448 dev_dbg(chip->card->dev, "(3) jiffies = %lu\n", jiffies);449 dev_dbg(chip->card->dev, "mce_down - exit = 0x%x\n",450 wss_inb(chip, CS4231P(REGSEL)));451}452EXPORT_SYMBOL(snd_wss_mce_down);453 454static unsigned int snd_wss_get_count(unsigned char format, unsigned int size)455{456 switch (format & 0xe0) {457 case CS4231_LINEAR_16:458 case CS4231_LINEAR_16_BIG:459 size >>= 1;460 break;461 case CS4231_ADPCM_16:462 return size >> 2;463 }464 if (format & CS4231_STEREO)465 size >>= 1;466 return size;467}468 469static int snd_wss_trigger(struct snd_pcm_substream *substream,470 int cmd)471{472 struct snd_wss *chip = snd_pcm_substream_chip(substream);473 int result = 0;474 unsigned int what;475 struct snd_pcm_substream *s;476 int do_start;477 478 switch (cmd) {479 case SNDRV_PCM_TRIGGER_START:480 case SNDRV_PCM_TRIGGER_RESUME:481 do_start = 1; break;482 case SNDRV_PCM_TRIGGER_STOP:483 case SNDRV_PCM_TRIGGER_SUSPEND:484 do_start = 0; break;485 default:486 return -EINVAL;487 }488 489 what = 0;490 snd_pcm_group_for_each_entry(s, substream) {491 if (s == chip->playback_substream) {492 what |= CS4231_PLAYBACK_ENABLE;493 snd_pcm_trigger_done(s, substream);494 } else if (s == chip->capture_substream) {495 what |= CS4231_RECORD_ENABLE;496 snd_pcm_trigger_done(s, substream);497 }498 }499 spin_lock(&chip->reg_lock);500 if (do_start) {501 chip->image[CS4231_IFACE_CTRL] |= what;502 if (chip->trigger)503 chip->trigger(chip, what, 1);504 } else {505 chip->image[CS4231_IFACE_CTRL] &= ~what;506 if (chip->trigger)507 chip->trigger(chip, what, 0);508 }509 snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);510 spin_unlock(&chip->reg_lock);511#if 0512 snd_wss_debug(chip);513#endif514 return result;515}516 517/*518 * CODEC I/O519 */520 521static unsigned char snd_wss_get_rate(unsigned int rate)522{523 int i;524 525 for (i = 0; i < ARRAY_SIZE(rates); i++)526 if (rate == rates[i])527 return freq_bits[i];528 // snd_BUG();529 return freq_bits[ARRAY_SIZE(rates) - 1];530}531 532static unsigned char snd_wss_get_format(struct snd_wss *chip,533 snd_pcm_format_t format,534 int channels)535{536 unsigned char rformat;537 538 rformat = CS4231_LINEAR_8;539 switch (format) {540 case SNDRV_PCM_FORMAT_MU_LAW: rformat = CS4231_ULAW_8; break;541 case SNDRV_PCM_FORMAT_A_LAW: rformat = CS4231_ALAW_8; break;542 case SNDRV_PCM_FORMAT_S16_LE: rformat = CS4231_LINEAR_16; break;543 case SNDRV_PCM_FORMAT_S16_BE: rformat = CS4231_LINEAR_16_BIG; break;544 case SNDRV_PCM_FORMAT_IMA_ADPCM: rformat = CS4231_ADPCM_16; break;545 }546 if (channels > 1)547 rformat |= CS4231_STEREO;548#if 0549 dev_dbg(chip->card->dev, "get_format: 0x%x (mode=0x%x)\n", format, mode);550#endif551 return rformat;552}553 554static void snd_wss_calibrate_mute(struct snd_wss *chip, int mute)555{556 unsigned long flags;557 558 mute = mute ? 0x80 : 0;559 spin_lock_irqsave(&chip->reg_lock, flags);560 if (chip->calibrate_mute == mute) {561 spin_unlock_irqrestore(&chip->reg_lock, flags);562 return;563 }564 if (!mute) {565 snd_wss_dout(chip, CS4231_LEFT_INPUT,566 chip->image[CS4231_LEFT_INPUT]);567 snd_wss_dout(chip, CS4231_RIGHT_INPUT,568 chip->image[CS4231_RIGHT_INPUT]);569 snd_wss_dout(chip, CS4231_LOOPBACK,570 chip->image[CS4231_LOOPBACK]);571 } else {572 snd_wss_dout(chip, CS4231_LEFT_INPUT,573 0);574 snd_wss_dout(chip, CS4231_RIGHT_INPUT,575 0);576 snd_wss_dout(chip, CS4231_LOOPBACK,577 0xfd);578 }579 580 snd_wss_dout(chip, CS4231_AUX1_LEFT_INPUT,581 mute | chip->image[CS4231_AUX1_LEFT_INPUT]);582 snd_wss_dout(chip, CS4231_AUX1_RIGHT_INPUT,583 mute | chip->image[CS4231_AUX1_RIGHT_INPUT]);584 snd_wss_dout(chip, CS4231_AUX2_LEFT_INPUT,585 mute | chip->image[CS4231_AUX2_LEFT_INPUT]);586 snd_wss_dout(chip, CS4231_AUX2_RIGHT_INPUT,587 mute | chip->image[CS4231_AUX2_RIGHT_INPUT]);588 snd_wss_dout(chip, CS4231_LEFT_OUTPUT,589 mute | chip->image[CS4231_LEFT_OUTPUT]);590 snd_wss_dout(chip, CS4231_RIGHT_OUTPUT,591 mute | chip->image[CS4231_RIGHT_OUTPUT]);592 if (!(chip->hardware & WSS_HW_AD1848_MASK)) {593 snd_wss_dout(chip, CS4231_LEFT_LINE_IN,594 mute | chip->image[CS4231_LEFT_LINE_IN]);595 snd_wss_dout(chip, CS4231_RIGHT_LINE_IN,596 mute | chip->image[CS4231_RIGHT_LINE_IN]);597 snd_wss_dout(chip, CS4231_MONO_CTRL,598 mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);599 }600 if (chip->hardware == WSS_HW_INTERWAVE) {601 snd_wss_dout(chip, CS4231_LEFT_MIC_INPUT,602 mute | chip->image[CS4231_LEFT_MIC_INPUT]);603 snd_wss_dout(chip, CS4231_RIGHT_MIC_INPUT,604 mute | chip->image[CS4231_RIGHT_MIC_INPUT]);605 snd_wss_dout(chip, CS4231_LINE_LEFT_OUTPUT,606 mute | chip->image[CS4231_LINE_LEFT_OUTPUT]);607 snd_wss_dout(chip, CS4231_LINE_RIGHT_OUTPUT,608 mute | chip->image[CS4231_LINE_RIGHT_OUTPUT]);609 }610 chip->calibrate_mute = mute;611 spin_unlock_irqrestore(&chip->reg_lock, flags);612}613 614static void snd_wss_playback_format(struct snd_wss *chip,615 struct snd_pcm_hw_params *params,616 unsigned char pdfr)617{618 unsigned long flags;619 int full_calib = 1;620 621 mutex_lock(&chip->mce_mutex);622 if (chip->hardware == WSS_HW_CS4231A ||623 (chip->hardware & WSS_HW_CS4232_MASK)) {624 spin_lock_irqsave(&chip->reg_lock, flags);625 if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (pdfr & 0x0f)) { /* rate is same? */626 snd_wss_out(chip, CS4231_ALT_FEATURE_1,627 chip->image[CS4231_ALT_FEATURE_1] | 0x10);628 chip->image[CS4231_PLAYBK_FORMAT] = pdfr;629 snd_wss_out(chip, CS4231_PLAYBK_FORMAT,630 chip->image[CS4231_PLAYBK_FORMAT]);631 snd_wss_out(chip, CS4231_ALT_FEATURE_1,632 chip->image[CS4231_ALT_FEATURE_1] &= ~0x10);633 udelay(100); /* Fixes audible clicks at least on GUS MAX */634 full_calib = 0;635 }636 spin_unlock_irqrestore(&chip->reg_lock, flags);637 } else if (chip->hardware == WSS_HW_AD1845) {638 unsigned rate = params_rate(params);639 640 /*641 * Program the AD1845 correctly for the playback stream.642 * Note that we do NOT need to toggle the MCE bit because643 * the PLAYBACK_ENABLE bit of the Interface Configuration644 * register is set.645 *646 * NOTE: We seem to need to write to the MSB before the LSB647 * to get the correct sample frequency.648 */649 spin_lock_irqsave(&chip->reg_lock, flags);650 snd_wss_out(chip, CS4231_PLAYBK_FORMAT, (pdfr & 0xf0));651 snd_wss_out(chip, AD1845_UPR_FREQ_SEL, (rate >> 8) & 0xff);652 snd_wss_out(chip, AD1845_LWR_FREQ_SEL, rate & 0xff);653 full_calib = 0;654 spin_unlock_irqrestore(&chip->reg_lock, flags);655 }656 if (full_calib) {657 snd_wss_mce_up(chip);658 spin_lock_irqsave(&chip->reg_lock, flags);659 if (chip->hardware != WSS_HW_INTERWAVE && !chip->single_dma) {660 if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE)661 pdfr = (pdfr & 0xf0) |662 (chip->image[CS4231_REC_FORMAT] & 0x0f);663 } else {664 chip->image[CS4231_PLAYBK_FORMAT] = pdfr;665 }666 snd_wss_out(chip, CS4231_PLAYBK_FORMAT, pdfr);667 spin_unlock_irqrestore(&chip->reg_lock, flags);668 if (chip->hardware == WSS_HW_OPL3SA2)669 udelay(100); /* this seems to help */670 snd_wss_mce_down(chip);671 }672 mutex_unlock(&chip->mce_mutex);673}674 675static void snd_wss_capture_format(struct snd_wss *chip,676 struct snd_pcm_hw_params *params,677 unsigned char cdfr)678{679 unsigned long flags;680 int full_calib = 1;681 682 mutex_lock(&chip->mce_mutex);683 if (chip->hardware == WSS_HW_CS4231A ||684 (chip->hardware & WSS_HW_CS4232_MASK)) {685 spin_lock_irqsave(&chip->reg_lock, flags);686 if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (cdfr & 0x0f) || /* rate is same? */687 (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {688 snd_wss_out(chip, CS4231_ALT_FEATURE_1,689 chip->image[CS4231_ALT_FEATURE_1] | 0x20);690 snd_wss_out(chip, CS4231_REC_FORMAT,691 chip->image[CS4231_REC_FORMAT] = cdfr);692 snd_wss_out(chip, CS4231_ALT_FEATURE_1,693 chip->image[CS4231_ALT_FEATURE_1] &= ~0x20);694 full_calib = 0;695 }696 spin_unlock_irqrestore(&chip->reg_lock, flags);697 } else if (chip->hardware == WSS_HW_AD1845) {698 unsigned rate = params_rate(params);699 700 /*701 * Program the AD1845 correctly for the capture stream.702 * Note that we do NOT need to toggle the MCE bit because703 * the PLAYBACK_ENABLE bit of the Interface Configuration704 * register is set.705 *706 * NOTE: We seem to need to write to the MSB before the LSB707 * to get the correct sample frequency.708 */709 spin_lock_irqsave(&chip->reg_lock, flags);710 snd_wss_out(chip, CS4231_REC_FORMAT, (cdfr & 0xf0));711 snd_wss_out(chip, AD1845_UPR_FREQ_SEL, (rate >> 8) & 0xff);712 snd_wss_out(chip, AD1845_LWR_FREQ_SEL, rate & 0xff);713 full_calib = 0;714 spin_unlock_irqrestore(&chip->reg_lock, flags);715 }716 if (full_calib) {717 snd_wss_mce_up(chip);718 spin_lock_irqsave(&chip->reg_lock, flags);719 if (chip->hardware != WSS_HW_INTERWAVE &&720 !(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {721 if (chip->single_dma)722 snd_wss_out(chip, CS4231_PLAYBK_FORMAT, cdfr);723 else724 snd_wss_out(chip, CS4231_PLAYBK_FORMAT,725 (chip->image[CS4231_PLAYBK_FORMAT] & 0xf0) |726 (cdfr & 0x0f));727 spin_unlock_irqrestore(&chip->reg_lock, flags);728 snd_wss_mce_down(chip);729 snd_wss_mce_up(chip);730 spin_lock_irqsave(&chip->reg_lock, flags);731 }732 if (chip->hardware & WSS_HW_AD1848_MASK)733 snd_wss_out(chip, CS4231_PLAYBK_FORMAT, cdfr);734 else735 snd_wss_out(chip, CS4231_REC_FORMAT, cdfr);736 spin_unlock_irqrestore(&chip->reg_lock, flags);737 snd_wss_mce_down(chip);738 }739 mutex_unlock(&chip->mce_mutex);740}741 742/*743 * Timer interface744 */745 746static unsigned long snd_wss_timer_resolution(struct snd_timer *timer)747{748 struct snd_wss *chip = snd_timer_chip(timer);749 if (chip->hardware & WSS_HW_CS4236B_MASK)750 return 14467;751 else752 return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;753}754 755static int snd_wss_timer_start(struct snd_timer *timer)756{757 unsigned long flags;758 unsigned int ticks;759 struct snd_wss *chip = snd_timer_chip(timer);760 spin_lock_irqsave(&chip->reg_lock, flags);761 ticks = timer->sticks;762 if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||763 (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||764 (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {765 chip->image[CS4231_TIMER_HIGH] = (unsigned char) (ticks >> 8);766 snd_wss_out(chip, CS4231_TIMER_HIGH,767 chip->image[CS4231_TIMER_HIGH]);768 chip->image[CS4231_TIMER_LOW] = (unsigned char) ticks;769 snd_wss_out(chip, CS4231_TIMER_LOW,770 chip->image[CS4231_TIMER_LOW]);771 snd_wss_out(chip, CS4231_ALT_FEATURE_1,772 chip->image[CS4231_ALT_FEATURE_1] |773 CS4231_TIMER_ENABLE);774 }775 spin_unlock_irqrestore(&chip->reg_lock, flags);776 return 0;777}778 779static int snd_wss_timer_stop(struct snd_timer *timer)780{781 unsigned long flags;782 struct snd_wss *chip = snd_timer_chip(timer);783 spin_lock_irqsave(&chip->reg_lock, flags);784 chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE;785 snd_wss_out(chip, CS4231_ALT_FEATURE_1,786 chip->image[CS4231_ALT_FEATURE_1]);787 spin_unlock_irqrestore(&chip->reg_lock, flags);788 return 0;789}790 791static void snd_wss_init(struct snd_wss *chip)792{793 unsigned long flags;794 795 snd_wss_calibrate_mute(chip, 1);796 snd_wss_mce_down(chip);797 798#ifdef SNDRV_DEBUG_MCE799 dev_dbg(chip->card->dev, "init: (1)\n");800#endif801 snd_wss_mce_up(chip);802 spin_lock_irqsave(&chip->reg_lock, flags);803 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |804 CS4231_PLAYBACK_PIO |805 CS4231_RECORD_ENABLE |806 CS4231_RECORD_PIO |807 CS4231_CALIB_MODE);808 chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;809 snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);810 spin_unlock_irqrestore(&chip->reg_lock, flags);811 snd_wss_mce_down(chip);812 813#ifdef SNDRV_DEBUG_MCE814 dev_dbg(chip->card->dev, "init: (2)\n");815#endif816 817 snd_wss_mce_up(chip);818 spin_lock_irqsave(&chip->reg_lock, flags);819 chip->image[CS4231_IFACE_CTRL] &= ~CS4231_AUTOCALIB;820 snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);821 snd_wss_out(chip,822 CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]);823 spin_unlock_irqrestore(&chip->reg_lock, flags);824 snd_wss_mce_down(chip);825 826#ifdef SNDRV_DEBUG_MCE827 dev_dbg(chip->card->dev, "init: (3) - afei = 0x%x\n",828 chip->image[CS4231_ALT_FEATURE_1]);829#endif830 831 spin_lock_irqsave(&chip->reg_lock, flags);832 snd_wss_out(chip, CS4231_ALT_FEATURE_2,833 chip->image[CS4231_ALT_FEATURE_2]);834 spin_unlock_irqrestore(&chip->reg_lock, flags);835 836 snd_wss_mce_up(chip);837 spin_lock_irqsave(&chip->reg_lock, flags);838 snd_wss_out(chip, CS4231_PLAYBK_FORMAT,839 chip->image[CS4231_PLAYBK_FORMAT]);840 spin_unlock_irqrestore(&chip->reg_lock, flags);841 snd_wss_mce_down(chip);842 843#ifdef SNDRV_DEBUG_MCE844 dev_dbg(chip->card->dev, "init: (4)\n");845#endif846 847 snd_wss_mce_up(chip);848 spin_lock_irqsave(&chip->reg_lock, flags);849 if (!(chip->hardware & WSS_HW_AD1848_MASK))850 snd_wss_out(chip, CS4231_REC_FORMAT,851 chip->image[CS4231_REC_FORMAT]);852 spin_unlock_irqrestore(&chip->reg_lock, flags);853 snd_wss_mce_down(chip);854 snd_wss_calibrate_mute(chip, 0);855 856#ifdef SNDRV_DEBUG_MCE857 dev_dbg(chip->card->dev, "init: (5)\n");858#endif859}860 861static int snd_wss_open(struct snd_wss *chip, unsigned int mode)862{863 unsigned long flags;864 865 mutex_lock(&chip->open_mutex);866 if ((chip->mode & mode) ||867 ((chip->mode & WSS_MODE_OPEN) && chip->single_dma)) {868 mutex_unlock(&chip->open_mutex);869 return -EAGAIN;870 }871 if (chip->mode & WSS_MODE_OPEN) {872 chip->mode |= mode;873 mutex_unlock(&chip->open_mutex);874 return 0;875 }876 /* ok. now enable and ack CODEC IRQ */877 spin_lock_irqsave(&chip->reg_lock, flags);878 if (!(chip->hardware & WSS_HW_AD1848_MASK)) {879 snd_wss_out(chip, CS4231_IRQ_STATUS,880 CS4231_PLAYBACK_IRQ |881 CS4231_RECORD_IRQ |882 CS4231_TIMER_IRQ);883 snd_wss_out(chip, CS4231_IRQ_STATUS, 0);884 }885 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */886 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */887 chip->image[CS4231_PIN_CTRL] |= CS4231_IRQ_ENABLE;888 snd_wss_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);889 if (!(chip->hardware & WSS_HW_AD1848_MASK)) {890 snd_wss_out(chip, CS4231_IRQ_STATUS,891 CS4231_PLAYBACK_IRQ |892 CS4231_RECORD_IRQ |893 CS4231_TIMER_IRQ);894 snd_wss_out(chip, CS4231_IRQ_STATUS, 0);895 }896 spin_unlock_irqrestore(&chip->reg_lock, flags);897 898 chip->mode = mode;899 mutex_unlock(&chip->open_mutex);900 return 0;901}902 903static void snd_wss_close(struct snd_wss *chip, unsigned int mode)904{905 unsigned long flags;906 907 mutex_lock(&chip->open_mutex);908 chip->mode &= ~mode;909 if (chip->mode & WSS_MODE_OPEN) {910 mutex_unlock(&chip->open_mutex);911 return;912 }913 /* disable IRQ */914 spin_lock_irqsave(&chip->reg_lock, flags);915 if (!(chip->hardware & WSS_HW_AD1848_MASK))916 snd_wss_out(chip, CS4231_IRQ_STATUS, 0);917 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */918 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */919 chip->image[CS4231_PIN_CTRL] &= ~CS4231_IRQ_ENABLE;920 snd_wss_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);921 922 /* now disable record & playback */923 924 if (chip->image[CS4231_IFACE_CTRL] & (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |925 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {926 spin_unlock_irqrestore(&chip->reg_lock, flags);927 snd_wss_mce_up(chip);928 spin_lock_irqsave(&chip->reg_lock, flags);929 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |930 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);931 snd_wss_out(chip, CS4231_IFACE_CTRL,932 chip->image[CS4231_IFACE_CTRL]);933 spin_unlock_irqrestore(&chip->reg_lock, flags);934 snd_wss_mce_down(chip);935 spin_lock_irqsave(&chip->reg_lock, flags);936 }937 938 /* clear IRQ again */939 if (!(chip->hardware & WSS_HW_AD1848_MASK))940 snd_wss_out(chip, CS4231_IRQ_STATUS, 0);941 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */942 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */943 spin_unlock_irqrestore(&chip->reg_lock, flags);944 945 chip->mode = 0;946 mutex_unlock(&chip->open_mutex);947}948 949/*950 * timer open/close951 */952 953static int snd_wss_timer_open(struct snd_timer *timer)954{955 struct snd_wss *chip = snd_timer_chip(timer);956 snd_wss_open(chip, WSS_MODE_TIMER);957 return 0;958}959 960static int snd_wss_timer_close(struct snd_timer *timer)961{962 struct snd_wss *chip = snd_timer_chip(timer);963 snd_wss_close(chip, WSS_MODE_TIMER);964 return 0;965}966 967static const struct snd_timer_hardware snd_wss_timer_table =968{969 .flags = SNDRV_TIMER_HW_AUTO,970 .resolution = 9945,971 .ticks = 65535,972 .open = snd_wss_timer_open,973 .close = snd_wss_timer_close,974 .c_resolution = snd_wss_timer_resolution,975 .start = snd_wss_timer_start,976 .stop = snd_wss_timer_stop,977};978 979/*980 * ok.. exported functions..981 */982 983static int snd_wss_playback_hw_params(struct snd_pcm_substream *substream,984 struct snd_pcm_hw_params *hw_params)985{986 struct snd_wss *chip = snd_pcm_substream_chip(substream);987 unsigned char new_pdfr;988 989 new_pdfr = snd_wss_get_format(chip, params_format(hw_params),990 params_channels(hw_params)) |991 snd_wss_get_rate(params_rate(hw_params));992 chip->set_playback_format(chip, hw_params, new_pdfr);993 return 0;994}995 996static int snd_wss_playback_prepare(struct snd_pcm_substream *substream)997{998 struct snd_wss *chip = snd_pcm_substream_chip(substream);999 struct snd_pcm_runtime *runtime = substream->runtime;1000 unsigned long flags;1001 unsigned int size = snd_pcm_lib_buffer_bytes(substream);1002 unsigned int count = snd_pcm_lib_period_bytes(substream);1003 1004 spin_lock_irqsave(&chip->reg_lock, flags);1005 chip->p_dma_size = size;1006 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO);1007 snd_dma_program(chip->dma1, runtime->dma_addr, size, DMA_MODE_WRITE | DMA_AUTOINIT);1008 count = snd_wss_get_count(chip->image[CS4231_PLAYBK_FORMAT], count) - 1;1009 snd_wss_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);1010 snd_wss_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8));1011 spin_unlock_irqrestore(&chip->reg_lock, flags);1012#if 01013 snd_wss_debug(chip);1014#endif1015 return 0;1016}1017 1018static int snd_wss_capture_hw_params(struct snd_pcm_substream *substream,1019 struct snd_pcm_hw_params *hw_params)1020{1021 struct snd_wss *chip = snd_pcm_substream_chip(substream);1022 unsigned char new_cdfr;1023 1024 new_cdfr = snd_wss_get_format(chip, params_format(hw_params),1025 params_channels(hw_params)) |1026 snd_wss_get_rate(params_rate(hw_params));1027 chip->set_capture_format(chip, hw_params, new_cdfr);1028 return 0;1029}1030 1031static int snd_wss_capture_prepare(struct snd_pcm_substream *substream)1032{1033 struct snd_wss *chip = snd_pcm_substream_chip(substream);1034 struct snd_pcm_runtime *runtime = substream->runtime;1035 unsigned long flags;1036 unsigned int size = snd_pcm_lib_buffer_bytes(substream);1037 unsigned int count = snd_pcm_lib_period_bytes(substream);1038 1039 spin_lock_irqsave(&chip->reg_lock, flags);1040 chip->c_dma_size = size;1041 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);1042 snd_dma_program(chip->dma2, runtime->dma_addr, size, DMA_MODE_READ | DMA_AUTOINIT);1043 if (chip->hardware & WSS_HW_AD1848_MASK)1044 count = snd_wss_get_count(chip->image[CS4231_PLAYBK_FORMAT],1045 count);1046 else1047 count = snd_wss_get_count(chip->image[CS4231_REC_FORMAT],1048 count);1049 count--;1050 if (chip->single_dma && chip->hardware != WSS_HW_INTERWAVE) {1051 snd_wss_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);1052 snd_wss_out(chip, CS4231_PLY_UPR_CNT,1053 (unsigned char) (count >> 8));1054 } else {1055 snd_wss_out(chip, CS4231_REC_LWR_CNT, (unsigned char) count);1056 snd_wss_out(chip, CS4231_REC_UPR_CNT,1057 (unsigned char) (count >> 8));1058 }1059 spin_unlock_irqrestore(&chip->reg_lock, flags);1060 return 0;1061}1062 1063void snd_wss_overrange(struct snd_wss *chip)1064{1065 unsigned long flags;1066 unsigned char res;1067 1068 spin_lock_irqsave(&chip->reg_lock, flags);1069 res = snd_wss_in(chip, CS4231_TEST_INIT);1070 spin_unlock_irqrestore(&chip->reg_lock, flags);1071 if (res & (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */1072 chip->capture_substream->runtime->overrange++;1073}1074EXPORT_SYMBOL(snd_wss_overrange);1075 1076irqreturn_t snd_wss_interrupt(int irq, void *dev_id)1077{1078 struct snd_wss *chip = dev_id;1079 unsigned char status;1080 1081 if (chip->hardware & WSS_HW_AD1848_MASK)1082 /* pretend it was the only possible irq for AD1848 */1083 status = CS4231_PLAYBACK_IRQ;1084 else1085 status = snd_wss_in(chip, CS4231_IRQ_STATUS);1086 if (status & CS4231_TIMER_IRQ) {1087 if (chip->timer)1088 snd_timer_interrupt(chip->timer, chip->timer->sticks);1089 }1090 if (chip->single_dma && chip->hardware != WSS_HW_INTERWAVE) {1091 if (status & CS4231_PLAYBACK_IRQ) {1092 if (chip->mode & WSS_MODE_PLAY) {1093 if (chip->playback_substream)1094 snd_pcm_period_elapsed(chip->playback_substream);1095 }1096 if (chip->mode & WSS_MODE_RECORD) {1097 if (chip->capture_substream) {1098 snd_wss_overrange(chip);1099 snd_pcm_period_elapsed(chip->capture_substream);1100 }1101 }1102 }1103 } else {1104 if (status & CS4231_PLAYBACK_IRQ) {1105 if (chip->playback_substream)1106 snd_pcm_period_elapsed(chip->playback_substream);1107 }1108 if (status & CS4231_RECORD_IRQ) {1109 if (chip->capture_substream) {1110 snd_wss_overrange(chip);1111 snd_pcm_period_elapsed(chip->capture_substream);1112 }1113 }1114 }1115 1116 spin_lock(&chip->reg_lock);1117 status = ~CS4231_ALL_IRQS | ~status;1118 if (chip->hardware & WSS_HW_AD1848_MASK)1119 wss_outb(chip, CS4231P(STATUS), 0);1120 else1121 snd_wss_out(chip, CS4231_IRQ_STATUS, status);1122 spin_unlock(&chip->reg_lock);1123 return IRQ_HANDLED;1124}1125EXPORT_SYMBOL(snd_wss_interrupt);1126 1127static snd_pcm_uframes_t snd_wss_playback_pointer(struct snd_pcm_substream *substream)1128{1129 struct snd_wss *chip = snd_pcm_substream_chip(substream);1130 size_t ptr;1131 1132 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))1133 return 0;1134 ptr = snd_dma_pointer(chip->dma1, chip->p_dma_size);1135 return bytes_to_frames(substream->runtime, ptr);1136}1137 1138static snd_pcm_uframes_t snd_wss_capture_pointer(struct snd_pcm_substream *substream)1139{1140 struct snd_wss *chip = snd_pcm_substream_chip(substream);1141 size_t ptr;1142 1143 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))1144 return 0;1145 ptr = snd_dma_pointer(chip->dma2, chip->c_dma_size);1146 return bytes_to_frames(substream->runtime, ptr);1147}1148 1149/*1150 1151 */1152 1153static int snd_ad1848_probe(struct snd_wss *chip)1154{1155 unsigned long timeout = jiffies + msecs_to_jiffies(1000);1156 unsigned long flags;1157 unsigned char r;1158 unsigned short hardware = 0;1159 int err = 0;1160 int i;1161 1162 while (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {1163 if (time_after(jiffies, timeout))1164 return -ENODEV;1165 cond_resched();1166 }1167 spin_lock_irqsave(&chip->reg_lock, flags);1168 1169 /* set CS423x MODE 1 */1170 snd_wss_dout(chip, CS4231_MISC_INFO, 0);1171 1172 snd_wss_dout(chip, CS4231_RIGHT_INPUT, 0x45); /* 0x55 & ~0x10 */1173 r = snd_wss_in(chip, CS4231_RIGHT_INPUT);1174 if (r != 0x45) {1175 /* RMGE always high on AD1847 */1176 if ((r & ~CS4231_ENABLE_MIC_GAIN) != 0x45) {1177 err = -ENODEV;1178 goto out;1179 }1180 hardware = WSS_HW_AD1847;1181 } else {1182 snd_wss_dout(chip, CS4231_LEFT_INPUT, 0xaa);1183 r = snd_wss_in(chip, CS4231_LEFT_INPUT);1184 /* L/RMGE always low on AT2320 */1185 if ((r | CS4231_ENABLE_MIC_GAIN) != 0xaa) {1186 err = -ENODEV;1187 goto out;1188 }1189 }1190 1191 /* clear pending IRQ */1192 wss_inb(chip, CS4231P(STATUS));1193 wss_outb(chip, CS4231P(STATUS), 0);1194 mb();1195 1196 if ((chip->hardware & WSS_HW_TYPE_MASK) != WSS_HW_DETECT)1197 goto out;1198 1199 if (hardware) {1200 chip->hardware = hardware;1201 goto out;1202 }1203 1204 r = snd_wss_in(chip, CS4231_MISC_INFO);1205 1206 /* set CS423x MODE 2 */1207 snd_wss_dout(chip, CS4231_MISC_INFO, CS4231_MODE2);1208 for (i = 0; i < 16; i++) {1209 if (snd_wss_in(chip, i) != snd_wss_in(chip, 16 + i)) {1210 /* we have more than 16 registers: check ID */1211 if ((r & 0xf) != 0xa)1212 goto out_mode;1213 /*1214 * on CMI8330, CS4231_VERSION is volume control and1215 * can be set to 01216 */1217 snd_wss_dout(chip, CS4231_VERSION, 0);1218 r = snd_wss_in(chip, CS4231_VERSION) & 0xe7;1219 if (!r)1220 chip->hardware = WSS_HW_CMI8330;1221 goto out_mode;1222 }1223 }1224 if (r & 0x80)1225 chip->hardware = WSS_HW_CS4248;1226 else1227 chip->hardware = WSS_HW_AD1848;1228out_mode:1229 snd_wss_dout(chip, CS4231_MISC_INFO, 0);1230out:1231 spin_unlock_irqrestore(&chip->reg_lock, flags);1232 return err;1233}1234 1235static int snd_wss_probe(struct snd_wss *chip)1236{1237 unsigned long flags;1238 int i, id, rev, regnum;1239 unsigned char *ptr;1240 unsigned int hw;1241 1242 id = snd_ad1848_probe(chip);1243 if (id < 0)1244 return id;1245 1246 hw = chip->hardware;1247 if ((hw & WSS_HW_TYPE_MASK) == WSS_HW_DETECT) {1248 for (i = 0; i < 50; i++) {1249 mb();1250 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)1251 msleep(2);1252 else {1253 spin_lock_irqsave(&chip->reg_lock, flags);1254 snd_wss_out(chip, CS4231_MISC_INFO,1255 CS4231_MODE2);1256 id = snd_wss_in(chip, CS4231_MISC_INFO) & 0x0f;1257 spin_unlock_irqrestore(&chip->reg_lock, flags);1258 if (id == 0x0a)1259 break; /* this is valid value */1260 }1261 }1262 dev_dbg(chip->card->dev, "wss: port = 0x%lx, id = 0x%x\n",1263 chip->port, id);1264 if (id != 0x0a)1265 return -ENODEV; /* no valid device found */1266 1267 rev = snd_wss_in(chip, CS4231_VERSION) & 0xe7;1268 dev_dbg(chip->card->dev, "CS4231: VERSION (I25) = 0x%x\n", rev);1269 if (rev == 0x80) {1270 unsigned char tmp = snd_wss_in(chip, 23);1271 snd_wss_out(chip, 23, ~tmp);1272 if (snd_wss_in(chip, 23) != tmp)1273 chip->hardware = WSS_HW_AD1845;1274 else1275 chip->hardware = WSS_HW_CS4231;1276 } else if (rev == 0xa0) {1277 chip->hardware = WSS_HW_CS4231A;1278 } else if (rev == 0xa2) {1279 chip->hardware = WSS_HW_CS4232;1280 } else if (rev == 0xb2) {1281 chip->hardware = WSS_HW_CS4232A;1282 } else if (rev == 0x83) {1283 chip->hardware = WSS_HW_CS4236;1284 } else if (rev == 0x03) {1285 chip->hardware = WSS_HW_CS4236B;1286 } else {1287 dev_err(chip->card->dev,1288 "unknown CS chip with version 0x%x\n", rev);1289 return -ENODEV; /* unknown CS4231 chip? */1290 }1291 }1292 spin_lock_irqsave(&chip->reg_lock, flags);1293 wss_inb(chip, CS4231P(STATUS)); /* clear any pendings IRQ */1294 wss_outb(chip, CS4231P(STATUS), 0);1295 mb();1296 spin_unlock_irqrestore(&chip->reg_lock, flags);1297 1298 if (!(chip->hardware & WSS_HW_AD1848_MASK))1299 chip->image[CS4231_MISC_INFO] = CS4231_MODE2;1300 switch (chip->hardware) {1301 case WSS_HW_INTERWAVE:1302 chip->image[CS4231_MISC_INFO] = CS4231_IW_MODE3;1303 break;1304 case WSS_HW_CS4235:1305 case WSS_HW_CS4236B:1306 case WSS_HW_CS4237B:1307 case WSS_HW_CS4238B:1308 case WSS_HW_CS4239:1309 if (hw == WSS_HW_DETECT3)1310 chip->image[CS4231_MISC_INFO] = CS4231_4236_MODE3;1311 else1312 chip->hardware = WSS_HW_CS4236;1313 break;1314 }1315 1316 chip->image[CS4231_IFACE_CTRL] =1317 (chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA) |1318 (chip->single_dma ? CS4231_SINGLE_DMA : 0);1319 if (chip->hardware != WSS_HW_OPTI93X) {1320 chip->image[CS4231_ALT_FEATURE_1] = 0x80;1321 chip->image[CS4231_ALT_FEATURE_2] =1322 chip->hardware == WSS_HW_INTERWAVE ? 0xc2 : 0x01;1323 }1324 /* enable fine grained frequency selection */1325 if (chip->hardware == WSS_HW_AD1845)1326 chip->image[AD1845_PWR_DOWN] = 8;1327 1328 ptr = (unsigned char *) &chip->image;1329 regnum = (chip->hardware & WSS_HW_AD1848_MASK) ? 16 : 32;1330 snd_wss_mce_down(chip);1331 spin_lock_irqsave(&chip->reg_lock, flags);1332 for (i = 0; i < regnum; i++) /* ok.. fill all registers */1333 snd_wss_out(chip, i, *ptr++);1334 spin_unlock_irqrestore(&chip->reg_lock, flags);1335 snd_wss_mce_up(chip);1336 snd_wss_mce_down(chip);1337 1338 mdelay(2);1339 1340 /* ok.. try check hardware version for CS4236+ chips */1341 if ((hw & WSS_HW_TYPE_MASK) == WSS_HW_DETECT) {1342 if (chip->hardware == WSS_HW_CS4236B) {1343 rev = snd_cs4236_ext_in(chip, CS4236_VERSION);1344 snd_cs4236_ext_out(chip, CS4236_VERSION, 0xff);1345 id = snd_cs4236_ext_in(chip, CS4236_VERSION);1346 snd_cs4236_ext_out(chip, CS4236_VERSION, rev);1347 dev_dbg(chip->card->dev,1348 "CS4231: ext version; rev = 0x%x, id = 0x%x\n",1349 rev, id);1350 if ((id & 0x1f) == 0x1d) { /* CS4235 */1351 chip->hardware = WSS_HW_CS4235;1352 switch (id >> 5) {1353 case 4:1354 case 5:1355 case 6:1356 break;1357 default:1358 dev_warn(chip->card->dev,1359 "unknown CS4235 chip (enhanced version = 0x%x)\n",1360 id);1361 }1362 } else if ((id & 0x1f) == 0x0b) { /* CS4236/B */1363 switch (id >> 5) {1364 case 4:1365 case 5:1366 case 6:1367 case 7:1368 chip->hardware = WSS_HW_CS4236B;1369 break;1370 default:1371 dev_warn(chip->card->dev,1372 "unknown CS4236 chip (enhanced version = 0x%x)\n",1373 id);1374 }1375 } else if ((id & 0x1f) == 0x08) { /* CS4237B */1376 chip->hardware = WSS_HW_CS4237B;1377 switch (id >> 5) {1378 case 4:1379 case 5:1380 case 6:1381 case 7:1382 break;1383 default:1384 dev_warn(chip->card->dev,1385 "unknown CS4237B chip (enhanced version = 0x%x)\n",1386 id);1387 }1388 } else if ((id & 0x1f) == 0x09) { /* CS4238B */1389 chip->hardware = WSS_HW_CS4238B;1390 switch (id >> 5) {1391 case 5:1392 case 6:1393 case 7:1394 break;1395 default:1396 dev_warn(chip->card->dev,1397 "unknown CS4238B chip (enhanced version = 0x%x)\n",1398 id);1399 }1400 } else if ((id & 0x1f) == 0x1e) { /* CS4239 */1401 chip->hardware = WSS_HW_CS4239;1402 switch (id >> 5) {1403 case 4:1404 case 5:1405 case 6:1406 break;1407 default:1408 dev_warn(chip->card->dev,1409 "unknown CS4239 chip (enhanced version = 0x%x)\n",1410 id);1411 }1412 } else {1413 dev_warn(chip->card->dev,1414 "unknown CS4236/CS423xB chip (enhanced version = 0x%x)\n",1415 id);1416 }1417 }1418 }1419 return 0; /* all things are ok.. */1420}1421 1422/*1423 1424 */1425 1426static const struct snd_pcm_hardware snd_wss_playback =1427{1428 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |1429 SNDRV_PCM_INFO_MMAP_VALID |1430 SNDRV_PCM_INFO_SYNC_START),1431 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |1432 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),1433 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,1434 .rate_min = 5510,1435 .rate_max = 48000,1436 .channels_min = 1,1437 .channels_max = 2,1438 .buffer_bytes_max = (128*1024),1439 .period_bytes_min = 64,1440 .period_bytes_max = (128*1024),1441 .periods_min = 1,1442 .periods_max = 1024,1443 .fifo_size = 0,1444};1445 1446static const struct snd_pcm_hardware snd_wss_capture =1447{1448 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |1449 SNDRV_PCM_INFO_MMAP_VALID |1450 SNDRV_PCM_INFO_RESUME |1451 SNDRV_PCM_INFO_SYNC_START),1452 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |1453 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),1454 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,1455 .rate_min = 5510,1456 .rate_max = 48000,1457 .channels_min = 1,1458 .channels_max = 2,1459 .buffer_bytes_max = (128*1024),1460 .period_bytes_min = 64,1461 .period_bytes_max = (128*1024),1462 .periods_min = 1,1463 .periods_max = 1024,1464 .fifo_size = 0,1465};1466 1467/*1468 1469 */1470 1471static int snd_wss_playback_open(struct snd_pcm_substream *substream)1472{1473 struct snd_wss *chip = snd_pcm_substream_chip(substream);1474 struct snd_pcm_runtime *runtime = substream->runtime;1475 int err;1476 1477 runtime->hw = snd_wss_playback;1478 1479 /* hardware limitation of older chipsets */1480 if (chip->hardware & WSS_HW_AD1848_MASK)1481 runtime->hw.formats &= ~(SNDRV_PCM_FMTBIT_IMA_ADPCM |1482 SNDRV_PCM_FMTBIT_S16_BE);1483 1484 /* hardware bug in InterWave chipset */1485 if (chip->hardware == WSS_HW_INTERWAVE && chip->dma1 > 3)1486 runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_MU_LAW;1487 1488 /* hardware limitation of cheap chips */1489 if (chip->hardware == WSS_HW_CS4235 ||1490 chip->hardware == WSS_HW_CS4239)1491 runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE;1492 1493 snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.buffer_bytes_max);1494 snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.period_bytes_max);1495 1496 if (chip->claim_dma) {1497 err = chip->claim_dma(chip, chip->dma_private_data, chip->dma1);1498 if (err < 0)1499 return err;1500 }1501 1502 err = snd_wss_open(chip, WSS_MODE_PLAY);1503 if (err < 0) {1504 if (chip->release_dma)1505 chip->release_dma(chip, chip->dma_private_data, chip->dma1);1506 return err;1507 }1508 chip->playback_substream = substream;1509 snd_pcm_set_sync(substream);1510 chip->rate_constraint(runtime);1511 return 0;1512}1513 1514static int snd_wss_capture_open(struct snd_pcm_substream *substream)1515{1516 struct snd_wss *chip = snd_pcm_substream_chip(substream);1517 struct snd_pcm_runtime *runtime = substream->runtime;1518 int err;1519 1520 runtime->hw = snd_wss_capture;1521 1522 /* hardware limitation of older chipsets */1523 if (chip->hardware & WSS_HW_AD1848_MASK)1524 runtime->hw.formats &= ~(SNDRV_PCM_FMTBIT_IMA_ADPCM |1525 SNDRV_PCM_FMTBIT_S16_BE);1526 1527 /* hardware limitation of cheap chips */1528 if (chip->hardware == WSS_HW_CS4235 ||1529 chip->hardware == WSS_HW_CS4239 ||1530 chip->hardware == WSS_HW_OPTI93X)1531 runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 |1532 SNDRV_PCM_FMTBIT_S16_LE;1533 1534 snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.buffer_bytes_max);1535 snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.period_bytes_max);1536 1537 if (chip->claim_dma) {1538 err = chip->claim_dma(chip, chip->dma_private_data, chip->dma2);1539 if (err < 0)1540 return err;1541 }1542 1543 err = snd_wss_open(chip, WSS_MODE_RECORD);1544 if (err < 0) {1545 if (chip->release_dma)1546 chip->release_dma(chip, chip->dma_private_data, chip->dma2);1547 return err;1548 }1549 chip->capture_substream = substream;1550 snd_pcm_set_sync(substream);1551 chip->rate_constraint(runtime);1552 return 0;1553}1554 1555static int snd_wss_playback_close(struct snd_pcm_substream *substream)1556{1557 struct snd_wss *chip = snd_pcm_substream_chip(substream);1558 1559 chip->playback_substream = NULL;1560 snd_wss_close(chip, WSS_MODE_PLAY);1561 return 0;1562}1563 1564static int snd_wss_capture_close(struct snd_pcm_substream *substream)1565{1566 struct snd_wss *chip = snd_pcm_substream_chip(substream);1567 1568 chip->capture_substream = NULL;1569 snd_wss_close(chip, WSS_MODE_RECORD);1570 return 0;1571}1572 1573static void snd_wss_thinkpad_twiddle(struct snd_wss *chip, int on)1574{1575 int tmp;1576 1577 if (!chip->thinkpad_flag)1578 return;1579 1580 outb(0x1c, AD1848_THINKPAD_CTL_PORT1);1581 tmp = inb(AD1848_THINKPAD_CTL_PORT2);1582 1583 if (on)1584 /* turn it on */1585 tmp |= AD1848_THINKPAD_CS4248_ENABLE_BIT;1586 else1587 /* turn it off */1588 tmp &= ~AD1848_THINKPAD_CS4248_ENABLE_BIT;1589 1590 outb(tmp, AD1848_THINKPAD_CTL_PORT2);1591}1592 1593#ifdef CONFIG_PM1594 1595/* lowlevel suspend callback for CS4231 */1596static void snd_wss_suspend(struct snd_wss *chip)1597{1598 int reg;1599 unsigned long flags;1600 1601 spin_lock_irqsave(&chip->reg_lock, flags);1602 for (reg = 0; reg < 32; reg++)1603 chip->image[reg] = snd_wss_in(chip, reg);1604 spin_unlock_irqrestore(&chip->reg_lock, flags);1605 if (chip->thinkpad_flag)1606 snd_wss_thinkpad_twiddle(chip, 0);1607}1608 1609/* lowlevel resume callback for CS4231 */1610static void snd_wss_resume(struct snd_wss *chip)1611{1612 int reg;1613 unsigned long flags;1614 /* int timeout; */1615 1616 if (chip->thinkpad_flag)1617 snd_wss_thinkpad_twiddle(chip, 1);1618 snd_wss_mce_up(chip);1619 spin_lock_irqsave(&chip->reg_lock, flags);1620 for (reg = 0; reg < 32; reg++) {1621 switch (reg) {1622 case CS4231_VERSION:1623 break;1624 default:1625 snd_wss_out(chip, reg, chip->image[reg]);1626 break;1627 }1628 }1629 /* Yamaha needs this to resume properly */1630 if (chip->hardware == WSS_HW_OPL3SA2)1631 snd_wss_out(chip, CS4231_PLAYBK_FORMAT,1632 chip->image[CS4231_PLAYBK_FORMAT]);1633 spin_unlock_irqrestore(&chip->reg_lock, flags);1634#if 11635 snd_wss_mce_down(chip);1636#else1637 /* The following is a workaround to avoid freeze after resume on TP600E.1638 This is the first half of copy of snd_wss_mce_down(), but doesn't1639 include rescheduling. -- iwai1640 */1641 snd_wss_busy_wait(chip);1642 spin_lock_irqsave(&chip->reg_lock, flags);1643 chip->mce_bit &= ~CS4231_MCE;1644 timeout = wss_inb(chip, CS4231P(REGSEL));1645 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));1646 spin_unlock_irqrestore(&chip->reg_lock, flags);1647 if (timeout == 0x80)1648 dev_err(chip->card->dev1649 "down [0x%lx]: serious init problem - codec still busy\n",1650 chip->port);1651 if ((timeout & CS4231_MCE) == 0 ||1652 !(chip->hardware & (WSS_HW_CS4231_MASK | WSS_HW_CS4232_MASK))) {1653 return;1654 }1655 snd_wss_busy_wait(chip);1656#endif1657}1658#endif /* CONFIG_PM */1659 1660const char *snd_wss_chip_id(struct snd_wss *chip)1661{1662 switch (chip->hardware) {1663 case WSS_HW_CS4231:1664 return "CS4231";1665 case WSS_HW_CS4231A:1666 return "CS4231A";1667 case WSS_HW_CS4232:1668 return "CS4232";1669 case WSS_HW_CS4232A:1670 return "CS4232A";1671 case WSS_HW_CS4235:1672 return "CS4235";1673 case WSS_HW_CS4236:1674 return "CS4236";1675 case WSS_HW_CS4236B:1676 return "CS4236B";1677 case WSS_HW_CS4237B:1678 return "CS4237B";1679 case WSS_HW_CS4238B:1680 return "CS4238B";1681 case WSS_HW_CS4239:1682 return "CS4239";1683 case WSS_HW_INTERWAVE:1684 return "AMD InterWave";1685 case WSS_HW_OPL3SA2:1686 return chip->card->shortname;1687 case WSS_HW_AD1845:1688 return "AD1845";1689 case WSS_HW_OPTI93X:1690 return "OPTi 93x";1691 case WSS_HW_AD1847:1692 return "AD1847";1693 case WSS_HW_AD1848:1694 return "AD1848";1695 case WSS_HW_CS4248:1696 return "CS4248";1697 case WSS_HW_CMI8330:1698 return "CMI8330/C3D";1699 default:1700 return "???";1701 }1702}1703EXPORT_SYMBOL(snd_wss_chip_id);1704 1705static int snd_wss_new(struct snd_card *card,1706 unsigned short hardware,1707 unsigned short hwshare,1708 struct snd_wss **rchip)1709{1710 struct snd_wss *chip;1711 1712 *rchip = NULL;1713 chip = devm_kzalloc(card->dev, sizeof(*chip), GFP_KERNEL);1714 if (chip == NULL)1715 return -ENOMEM;1716 chip->hardware = hardware;1717 chip->hwshare = hwshare;1718 1719 spin_lock_init(&chip->reg_lock);1720 mutex_init(&chip->mce_mutex);1721 mutex_init(&chip->open_mutex);1722 chip->card = card;1723 chip->rate_constraint = snd_wss_xrate;1724 chip->set_playback_format = snd_wss_playback_format;1725 chip->set_capture_format = snd_wss_capture_format;1726 if (chip->hardware == WSS_HW_OPTI93X)1727 memcpy(&chip->image, &snd_opti93x_original_image,1728 sizeof(snd_opti93x_original_image));1729 else1730 memcpy(&chip->image, &snd_wss_original_image,1731 sizeof(snd_wss_original_image));1732 if (chip->hardware & WSS_HW_AD1848_MASK) {1733 chip->image[CS4231_PIN_CTRL] = 0;1734 chip->image[CS4231_TEST_INIT] = 0;1735 }1736 1737 *rchip = chip;1738 return 0;1739}1740 1741int snd_wss_create(struct snd_card *card,1742 unsigned long port,1743 unsigned long cport,1744 int irq, int dma1, int dma2,1745 unsigned short hardware,1746 unsigned short hwshare,1747 struct snd_wss **rchip)1748{1749 struct snd_wss *chip;1750 int err;1751 1752 err = snd_wss_new(card, hardware, hwshare, &chip);1753 if (err < 0)1754 return err;1755 1756 chip->irq = -1;1757 chip->dma1 = -1;1758 chip->dma2 = -1;1759 1760 chip->res_port = devm_request_region(card->dev, port, 4, "WSS");1761 if (!chip->res_port) {1762 dev_err(chip->card->dev, "wss: can't grab port 0x%lx\n", port);1763 return -EBUSY;1764 }1765 chip->port = port;1766 if ((long)cport >= 0) {1767 chip->res_cport = devm_request_region(card->dev, cport, 8,1768 "CS4232 Control");1769 if (!chip->res_cport) {1770 dev_err(chip->card->dev,1771 "wss: can't grab control port 0x%lx\n", cport);1772 return -ENODEV;1773 }1774 }1775 chip->cport = cport;1776 if (!(hwshare & WSS_HWSHARE_IRQ))1777 if (devm_request_irq(card->dev, irq, snd_wss_interrupt, 0,1778 "WSS", (void *) chip)) {1779 dev_err(chip->card->dev, "wss: can't grab IRQ %d\n", irq);1780 return -EBUSY;1781 }1782 chip->irq = irq;1783 card->sync_irq = chip->irq;1784 if (!(hwshare & WSS_HWSHARE_DMA1) &&1785 snd_devm_request_dma(card->dev, dma1, "WSS - 1")) {1786 dev_err(chip->card->dev, "wss: can't grab DMA1 %d\n", dma1);1787 return -EBUSY;1788 }1789 chip->dma1 = dma1;1790 if (!(hwshare & WSS_HWSHARE_DMA2) && dma1 != dma2 && dma2 >= 0 &&1791 snd_devm_request_dma(card->dev, dma2, "WSS - 2")) {1792 dev_err(chip->card->dev, "wss: can't grab DMA2 %d\n", dma2);1793 return -EBUSY;1794 }1795 if (dma1 == dma2 || dma2 < 0) {1796 chip->single_dma = 1;1797 chip->dma2 = chip->dma1;1798 } else1799 chip->dma2 = dma2;1800 1801 if (hardware == WSS_HW_THINKPAD) {1802 chip->thinkpad_flag = 1;1803 chip->hardware = WSS_HW_DETECT; /* reset */1804 snd_wss_thinkpad_twiddle(chip, 1);1805 }1806 1807 /* global setup */1808 if (snd_wss_probe(chip) < 0)1809 return -ENODEV;1810 snd_wss_init(chip);1811 1812#if 01813 if (chip->hardware & WSS_HW_CS4232_MASK) {1814 if (chip->res_cport == NULL)1815 dev_err(chip->card->dev,1816 "CS4232 control port features are not accessible\n");1817 }1818#endif1819 1820#ifdef CONFIG_PM1821 /* Power Management */1822 chip->suspend = snd_wss_suspend;1823 chip->resume = snd_wss_resume;1824#endif1825 1826 *rchip = chip;1827 return 0;1828}1829EXPORT_SYMBOL(snd_wss_create);1830 1831static const struct snd_pcm_ops snd_wss_playback_ops = {1832 .open = snd_wss_playback_open,1833 .close = snd_wss_playback_close,1834 .hw_params = snd_wss_playback_hw_params,1835 .prepare = snd_wss_playback_prepare,1836 .trigger = snd_wss_trigger,1837 .pointer = snd_wss_playback_pointer,1838};1839 1840static const struct snd_pcm_ops snd_wss_capture_ops = {1841 .open = snd_wss_capture_open,1842 .close = snd_wss_capture_close,1843 .hw_params = snd_wss_capture_hw_params,1844 .prepare = snd_wss_capture_prepare,1845 .trigger = snd_wss_trigger,1846 .pointer = snd_wss_capture_pointer,1847};1848 1849int snd_wss_pcm(struct snd_wss *chip, int device)1850{1851 struct snd_pcm *pcm;1852 int err;1853 1854 err = snd_pcm_new(chip->card, "WSS", device, 1, 1, &pcm);1855 if (err < 0)1856 return err;1857 1858 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_wss_playback_ops);1859 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_wss_capture_ops);1860 1861 /* global setup */1862 pcm->private_data = chip;1863 pcm->info_flags = 0;1864 if (chip->single_dma)1865 pcm->info_flags |= SNDRV_PCM_INFO_HALF_DUPLEX;1866 if (chip->hardware != WSS_HW_INTERWAVE)1867 pcm->info_flags |= SNDRV_PCM_INFO_JOINT_DUPLEX;1868 strcpy(pcm->name, snd_wss_chip_id(chip));1869 1870 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, chip->card->dev,1871 64*1024, chip->dma1 > 3 || chip->dma2 > 3 ? 128*1024 : 64*1024);1872 1873 chip->pcm = pcm;1874 return 0;1875}1876EXPORT_SYMBOL(snd_wss_pcm);1877 1878static void snd_wss_timer_free(struct snd_timer *timer)1879{1880 struct snd_wss *chip = timer->private_data;1881 chip->timer = NULL;1882}1883 1884int snd_wss_timer(struct snd_wss *chip, int device)1885{1886 struct snd_timer *timer;1887 struct snd_timer_id tid;1888 int err;1889 1890 /* Timer initialization */1891 tid.dev_class = SNDRV_TIMER_CLASS_CARD;1892 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;1893 tid.card = chip->card->number;1894 tid.device = device;1895 tid.subdevice = 0;1896 err = snd_timer_new(chip->card, "CS4231", &tid, &timer);1897 if (err < 0)1898 return err;1899 strcpy(timer->name, snd_wss_chip_id(chip));1900 timer->private_data = chip;1901 timer->private_free = snd_wss_timer_free;1902 timer->hw = snd_wss_timer_table;1903 chip->timer = timer;1904 return 0;1905}1906EXPORT_SYMBOL(snd_wss_timer);1907 1908/*1909 * MIXER part1910 */1911 1912static int snd_wss_info_mux(struct snd_kcontrol *kcontrol,1913 struct snd_ctl_elem_info *uinfo)1914{1915 static const char * const texts[4] = {1916 "Line", "Aux", "Mic", "Mix"1917 };1918 static const char * const opl3sa_texts[4] = {1919 "Line", "CD", "Mic", "Mix"1920 };1921 static const char * const gusmax_texts[4] = {1922 "Line", "Synth", "Mic", "Mix"1923 };1924 const char * const *ptexts = texts;1925 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);1926 1927 if (snd_BUG_ON(!chip->card))1928 return -EINVAL;1929 if (!strcmp(chip->card->driver, "GUS MAX"))1930 ptexts = gusmax_texts;1931 switch (chip->hardware) {1932 case WSS_HW_INTERWAVE:1933 ptexts = gusmax_texts;1934 break;1935 case WSS_HW_OPTI93X:1936 case WSS_HW_OPL3SA2:1937 ptexts = opl3sa_texts;1938 break;1939 }1940 return snd_ctl_enum_info(uinfo, 2, 4, ptexts);1941}1942 1943static int snd_wss_get_mux(struct snd_kcontrol *kcontrol,1944 struct snd_ctl_elem_value *ucontrol)1945{1946 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);1947 unsigned long flags;1948 1949 spin_lock_irqsave(&chip->reg_lock, flags);1950 ucontrol->value.enumerated.item[0] = (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;1951 ucontrol->value.enumerated.item[1] = (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;1952 spin_unlock_irqrestore(&chip->reg_lock, flags);1953 return 0;1954}1955 1956static int snd_wss_put_mux(struct snd_kcontrol *kcontrol,1957 struct snd_ctl_elem_value *ucontrol)1958{1959 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);1960 unsigned long flags;1961 unsigned short left, right;1962 int change;1963 1964 if (ucontrol->value.enumerated.item[0] > 3 ||1965 ucontrol->value.enumerated.item[1] > 3)1966 return -EINVAL;1967 left = ucontrol->value.enumerated.item[0] << 6;1968 right = ucontrol->value.enumerated.item[1] << 6;1969 spin_lock_irqsave(&chip->reg_lock, flags);1970 left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;1971 right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;1972 change = left != chip->image[CS4231_LEFT_INPUT] ||1973 right != chip->image[CS4231_RIGHT_INPUT];1974 snd_wss_out(chip, CS4231_LEFT_INPUT, left);1975 snd_wss_out(chip, CS4231_RIGHT_INPUT, right);1976 spin_unlock_irqrestore(&chip->reg_lock, flags);1977 return change;1978}1979 1980int snd_wss_info_single(struct snd_kcontrol *kcontrol,1981 struct snd_ctl_elem_info *uinfo)1982{1983 int mask = (kcontrol->private_value >> 16) & 0xff;1984 1985 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;1986 uinfo->count = 1;1987 uinfo->value.integer.min = 0;1988 uinfo->value.integer.max = mask;1989 return 0;1990}1991EXPORT_SYMBOL(snd_wss_info_single);1992 1993int snd_wss_get_single(struct snd_kcontrol *kcontrol,1994 struct snd_ctl_elem_value *ucontrol)1995{1996 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);1997 unsigned long flags;1998 int reg = kcontrol->private_value & 0xff;1999 int shift = (kcontrol->private_value >> 8) & 0xff;2000 int mask = (kcontrol->private_value >> 16) & 0xff;2001 int invert = (kcontrol->private_value >> 24) & 0xff;2002 2003 spin_lock_irqsave(&chip->reg_lock, flags);2004 ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;2005 spin_unlock_irqrestore(&chip->reg_lock, flags);2006 if (invert)2007 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];2008 return 0;2009}2010EXPORT_SYMBOL(snd_wss_get_single);2011 2012int snd_wss_put_single(struct snd_kcontrol *kcontrol,2013 struct snd_ctl_elem_value *ucontrol)2014{2015 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);2016 unsigned long flags;2017 int reg = kcontrol->private_value & 0xff;2018 int shift = (kcontrol->private_value >> 8) & 0xff;2019 int mask = (kcontrol->private_value >> 16) & 0xff;2020 int invert = (kcontrol->private_value >> 24) & 0xff;2021 int change;2022 unsigned short val;2023 2024 val = (ucontrol->value.integer.value[0] & mask);2025 if (invert)2026 val = mask - val;2027 val <<= shift;2028 spin_lock_irqsave(&chip->reg_lock, flags);2029 val = (chip->image[reg] & ~(mask << shift)) | val;2030 change = val != chip->image[reg];2031 snd_wss_out(chip, reg, val);2032 spin_unlock_irqrestore(&chip->reg_lock, flags);2033 return change;2034}2035EXPORT_SYMBOL(snd_wss_put_single);2036 2037int snd_wss_info_double(struct snd_kcontrol *kcontrol,2038 struct snd_ctl_elem_info *uinfo)2039{2040 int mask = (kcontrol->private_value >> 24) & 0xff;2041 2042 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;2043 uinfo->count = 2;2044 uinfo->value.integer.min = 0;2045 uinfo->value.integer.max = mask;2046 return 0;2047}2048EXPORT_SYMBOL(snd_wss_info_double);2049 2050int snd_wss_get_double(struct snd_kcontrol *kcontrol,2051 struct snd_ctl_elem_value *ucontrol)2052{2053 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);2054 unsigned long flags;2055 int left_reg = kcontrol->private_value & 0xff;2056 int right_reg = (kcontrol->private_value >> 8) & 0xff;2057 int shift_left = (kcontrol->private_value >> 16) & 0x07;2058 int shift_right = (kcontrol->private_value >> 19) & 0x07;2059 int mask = (kcontrol->private_value >> 24) & 0xff;2060 int invert = (kcontrol->private_value >> 22) & 1;2061 2062 spin_lock_irqsave(&chip->reg_lock, flags);2063 ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;2064 ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;2065 spin_unlock_irqrestore(&chip->reg_lock, flags);2066 if (invert) {2067 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];2068 ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];2069 }2070 return 0;2071}2072EXPORT_SYMBOL(snd_wss_get_double);2073 2074int snd_wss_put_double(struct snd_kcontrol *kcontrol,2075 struct snd_ctl_elem_value *ucontrol)2076{2077 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);2078 unsigned long flags;2079 int left_reg = kcontrol->private_value & 0xff;2080 int right_reg = (kcontrol->private_value >> 8) & 0xff;2081 int shift_left = (kcontrol->private_value >> 16) & 0x07;2082 int shift_right = (kcontrol->private_value >> 19) & 0x07;2083 int mask = (kcontrol->private_value >> 24) & 0xff;2084 int invert = (kcontrol->private_value >> 22) & 1;2085 int change;2086 unsigned short val1, val2;2087 2088 val1 = ucontrol->value.integer.value[0] & mask;2089 val2 = ucontrol->value.integer.value[1] & mask;2090 if (invert) {2091 val1 = mask - val1;2092 val2 = mask - val2;2093 }2094 val1 <<= shift_left;2095 val2 <<= shift_right;2096 spin_lock_irqsave(&chip->reg_lock, flags);2097 if (left_reg != right_reg) {2098 val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;2099 val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;2100 change = val1 != chip->image[left_reg] ||2101 val2 != chip->image[right_reg];2102 snd_wss_out(chip, left_reg, val1);2103 snd_wss_out(chip, right_reg, val2);2104 } else {2105 mask = (mask << shift_left) | (mask << shift_right);2106 val1 = (chip->image[left_reg] & ~mask) | val1 | val2;2107 change = val1 != chip->image[left_reg];2108 snd_wss_out(chip, left_reg, val1);2109 }2110 spin_unlock_irqrestore(&chip->reg_lock, flags);2111 return change;2112}2113EXPORT_SYMBOL(snd_wss_put_double);2114 2115static const DECLARE_TLV_DB_SCALE(db_scale_6bit, -9450, 150, 0);2116static const DECLARE_TLV_DB_SCALE(db_scale_5bit_12db_max, -3450, 150, 0);2117static const DECLARE_TLV_DB_SCALE(db_scale_rec_gain, 0, 150, 0);2118static const DECLARE_TLV_DB_SCALE(db_scale_4bit, -4500, 300, 0);2119 2120static const struct snd_kcontrol_new snd_wss_controls[] = {2121WSS_DOUBLE("PCM Playback Switch", 0,2122 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),2123WSS_DOUBLE_TLV("PCM Playback Volume", 0,2124 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1,2125 db_scale_6bit),2126WSS_DOUBLE("Aux Playback Switch", 0,2127 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),2128WSS_DOUBLE_TLV("Aux Playback Volume", 0,2129 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1,2130 db_scale_5bit_12db_max),2131WSS_DOUBLE("Aux Playback Switch", 1,2132 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),2133WSS_DOUBLE_TLV("Aux Playback Volume", 1,2134 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1,2135 db_scale_5bit_12db_max),2136WSS_DOUBLE_TLV("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT,2137 0, 0, 15, 0, db_scale_rec_gain),2138{2139 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,2140 .name = "Capture Source",2141 .info = snd_wss_info_mux,2142 .get = snd_wss_get_mux,2143 .put = snd_wss_put_mux,2144},2145WSS_DOUBLE("Mic Boost (+20dB)", 0,2146 CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),2147WSS_SINGLE("Loopback Capture Switch", 0,2148 CS4231_LOOPBACK, 0, 1, 0),2149WSS_SINGLE_TLV("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1,2150 db_scale_6bit),2151WSS_DOUBLE("Line Playback Switch", 0,2152 CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),2153WSS_DOUBLE_TLV("Line Playback Volume", 0,2154 CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1,2155 db_scale_5bit_12db_max),2156WSS_SINGLE("Beep Playback Switch", 0,2157 CS4231_MONO_CTRL, 7, 1, 1),2158WSS_SINGLE_TLV("Beep Playback Volume", 0,2159 CS4231_MONO_CTRL, 0, 15, 1,2160 db_scale_4bit),2161WSS_SINGLE("Mono Output Playback Switch", 0,2162 CS4231_MONO_CTRL, 6, 1, 1),2163WSS_SINGLE("Beep Bypass Playback Switch", 0,2164 CS4231_MONO_CTRL, 5, 1, 0),2165};2166 2167int snd_wss_mixer(struct snd_wss *chip)2168{2169 struct snd_card *card;2170 unsigned int idx;2171 int err;2172 int count = ARRAY_SIZE(snd_wss_controls);2173 2174 if (snd_BUG_ON(!chip || !chip->pcm))2175 return -EINVAL;2176 2177 card = chip->card;2178 2179 strcpy(card->mixername, chip->pcm->name);2180 2181 /* Use only the first 11 entries on AD1848 */2182 if (chip->hardware & WSS_HW_AD1848_MASK)2183 count = 11;2184 /* There is no loopback on OPTI93X */2185 else if (chip->hardware == WSS_HW_OPTI93X)2186 count = 9;2187 2188 for (idx = 0; idx < count; idx++) {2189 err = snd_ctl_add(card,2190 snd_ctl_new1(&snd_wss_controls[idx],2191 chip));2192 if (err < 0)2193 return err;2194 }2195 return 0;2196}2197EXPORT_SYMBOL(snd_wss_mixer);2198 2199const struct snd_pcm_ops *snd_wss_get_pcm_ops(int direction)2200{2201 return direction == SNDRV_PCM_STREAM_PLAYBACK ?2202 &snd_wss_playback_ops : &snd_wss_capture_ops;2203}2204EXPORT_SYMBOL(snd_wss_get_pcm_ops);2205