206 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 Aureal Vortex Soundcard driver.4 5 IO addr collected from asp4core.vxd:6 function address7 0005D5A0 130048 00080674 140049 00080AFF 1281810 11 */12 13#define CHIP_AU882014 15#define CARD_NAME "Aureal Vortex"16#define CARD_NAME_SHORT "au8820"17 18/* Number of ADB and WT channels */19#define NR_ADB 0x1020#define NR_WT 0x2021#define NR_SRC 0x1022#define NR_A3D 0x0023#define NR_MIXIN 0x1024#define NR_MIXOUT 0x1025 26 27/* ADBDMA */28#define VORTEX_ADBDMA_STAT 0x105c0 /* read only, subbuffer, DMA pos */29#define POS_MASK 0x00000fff30#define POS_SHIFT 0x031#define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */32#define ADB_SUBBUF_SHIFT 0xc /* ADB only. */33#define VORTEX_ADBDMA_CTRL 0x10580 /* write only, format, flags, DMA pos */34#define OFFSET_MASK 0x00000fff35#define OFFSET_SHIFT 0x036#define IE_MASK 0x00001000 /* interrupt enable. */37#define IE_SHIFT 0xc38#define DIR_MASK 0x00002000 /* Direction. */39#define DIR_SHIFT 0xd40#define FMT_MASK 0x0003c00041#define FMT_SHIFT 0xe42// The masks and shift also work for the wtdma, if not specified otherwise.43#define VORTEX_ADBDMA_BUFCFG0 0x1040044#define VORTEX_ADBDMA_BUFCFG1 0x1040445#define VORTEX_ADBDMA_BUFBASE 0x1020046#define VORTEX_ADBDMA_START 0x106c0 /* Which subbuffer starts */47#define VORTEX_ADBDMA_STATUS 0x10600 /* stored at AdbDma->this_10 / 2 DWORD in size. */48 49/* ADB */50#define VORTEX_ADB_SR 0x10a00 /* Samplerates enable/disable */51#define VORTEX_ADB_RTBASE 0x1080052#define VORTEX_ADB_RTBASE_COUNT 10353#define VORTEX_ADB_CHNBASE 0x1099c54#define VORTEX_ADB_CHNBASE_COUNT 2255#define ROUTE_MASK 0x3fff56#define ADB_MASK 0x7f57#define ADB_SHIFT 0x758//#define ADB_MIX_MASK 0xf59/* ADB address */60#define OFFSET_ADBDMA 0x0061#define OFFSET_SRCOUT 0x10 /* on channel 0x11 */62#define OFFSET_SRCIN 0x10 /* on channel < 0x11 */63#define OFFSET_MIXOUT 0x20 /* source */64#define OFFSET_MIXIN 0x30 /* sink */65#define OFFSET_CODECIN 0x48 /* ADB source */66#define OFFSET_CODECOUT 0x58 /* ADB sink/target */67#define OFFSET_SPORTOUT 0x60 /* sink */68#define OFFSET_SPORTIN 0x50 /* source */69#define OFFSET_EFXOUT 0x50 /* sink */70#define OFFSET_EFXIN 0x40 /* source */71#define OFFSET_A3DOUT 0x00 /* This card has no HRTF :( */72#define OFFSET_A3DIN 0x0073#define OFFSET_WTOUT 0x58 /* */74 75/* ADB route translate helper */76#define ADB_DMA(x) (x + OFFSET_ADBDMA)77#define ADB_SRCOUT(x) (x + OFFSET_SRCOUT)78#define ADB_SRCIN(x) (x + OFFSET_SRCIN)79#define ADB_MIXOUT(x) (x + OFFSET_MIXOUT)80#define ADB_MIXIN(x) (x + OFFSET_MIXIN)81#define ADB_CODECIN(x) (x + OFFSET_CODECIN)82#define ADB_CODECOUT(x) (x + OFFSET_CODECOUT)83#define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT)84#define ADB_SPORTIN(x) (x + OFFSET_SPORTIN) /* */85#define ADB_A3DOUT(x) (x + OFFSET_A3DOUT) /* 8 A3D blocks */86#define ADB_A3DIN(x) (x + OFFSET_A3DIN)87#define ADB_WTOUT(x,y) (y + OFFSET_WTOUT)88 89/* WTDMA */90#define VORTEX_WTDMA_CTRL 0x10500 /* format, DMA pos */91#define VORTEX_WTDMA_STAT 0x10500 /* DMA subbuf, DMA pos */92#define WT_SUBBUF_MASK (0x3 << WT_SUBBUF_SHIFT)93#define WT_SUBBUF_SHIFT 0x1594#define VORTEX_WTDMA_BUFBASE 0x1000095#define VORTEX_WTDMA_BUFCFG0 0x1030096#define VORTEX_WTDMA_BUFCFG1 0x1030497#define VORTEX_WTDMA_START 0x10640 /* which subbuffer is first */98 99#define VORTEX_WT_BASE 0x9000100 101/* MIXER */102#define VORTEX_MIXER_SR 0x9f00103#define VORTEX_MIXER_CLIP 0x9f80104#define VORTEX_MIXER_CHNBASE 0x9e40105#define VORTEX_MIXER_RTBASE 0x9e00106#define MIXER_RTBASE_SIZE 0x26107#define VORTEX_MIX_ENIN 0x9a00 /* Input enable bits. 4 bits wide. */108#define VORTEX_MIX_SMP 0x9c00109 110/* MIX */111#define VORTEX_MIX_INVOL_A 0x9000 /* in? */112#define VORTEX_MIX_INVOL_B 0x8000 /* out? */113#define VORTEX_MIX_VOL_A 0x9800114#define VORTEX_MIX_VOL_B 0x8800115 116#define VOL_MIN 0x80 /* Input volume when muted. */117#define VOL_MAX 0x7f /* FIXME: Not confirmed! Just guessed. */118 119//#define MIX_OUTL 0xe120//#define MIX_OUTR 0xf121//#define MIX_INL 0xe122//#define MIX_INR 0xf123#define MIX_DEFIGAIN 0x08 /* 0x8 => 6dB */124#define MIX_DEFOGAIN 0x08125 126/* SRC */127#define VORTEX_SRCBLOCK_SR 0xccc0128#define VORTEX_SRC_CHNBASE 0xcc40129#define VORTEX_SRC_RTBASE 0xcc00130#define VORTEX_SRC_SOURCE 0xccc4131#define VORTEX_SRC_SOURCESIZE 0xccc8132#define VORTEX_SRC_U0 0xce00133#define VORTEX_SRC_DRIFT0 0xce80134#define VORTEX_SRC_DRIFT1 0xcec0135#define VORTEX_SRC_U1 0xcf00136#define VORTEX_SRC_DRIFT2 0xcf40137#define VORTEX_SRC_U2 0xcf80138#define VORTEX_SRC_DATA 0xc800139#define VORTEX_SRC_DATA0 0xc000140#define VORTEX_SRC_CONVRATIO 0xce40141//#define SRC_RATIO(x) ((((x<<15)/48000) + 1)/2) /* Playback */142//#define SRC_RATIO2(x) ((((48000<<15)/x) + 1)/2) /* Recording */143 144/* FIFO */145#define VORTEX_FIFO_ADBCTRL 0xf800 /* Control bits. */146#define VORTEX_FIFO_WTCTRL 0xf840147#define FIFO_RDONLY 0x00000001148#define FIFO_CTRL 0x00000002 /* Allow ctrl. ? */149#define FIFO_VALID 0x00000010150#define FIFO_EMPTY 0x00000020151#define FIFO_U0 0x00001000 /* Unknown. */152#define FIFO_U1 0x00010000153#define FIFO_SIZE_BITS 5154#define FIFO_SIZE (1<<FIFO_SIZE_BITS) // 0x20155#define FIFO_MASK (FIFO_SIZE-1) //0x1f /* at shift left 0xc */156#define VORTEX_FIFO_ADBDATA 0xe000157#define VORTEX_FIFO_WTDATA 0xe800158 159/* CODEC */160#define VORTEX_CODEC_CTRL 0x11984161#define VORTEX_CODEC_EN 0x11990162#define EN_CODEC 0x00000300163#define EN_SPORT 0x00030000164#define EN_SPDIF 0x000c0000165#define VORTEX_CODEC_CHN 0x11880166#define VORTEX_CODEC_IO 0x11988167 168#define VORTEX_SPDIF_FLAGS 0x1005c /* FIXME */169#define VORTEX_SPDIF_CFG0 0x119D0170#define VORTEX_SPDIF_CFG1 0x119D4171#define VORTEX_SPDIF_SMPRATE 0x11994172 173/* Sample timer */174#define VORTEX_SMP_TIME 0x11998175 176/* IRQ */177#define VORTEX_IRQ_SOURCE 0x12800 /* Interrupt source flags. */178#define VORTEX_IRQ_CTRL 0x12804 /* Interrupt source mask. */179 180#define VORTEX_STAT 0x12808 /* ?? */181 182#define VORTEX_CTRL 0x1280c183#define CTRL_MIDI_EN 0x00000001184#define CTRL_MIDI_PORT 0x00000060185#define CTRL_GAME_EN 0x00000008186#define CTRL_GAME_PORT 0x00000e00187#define CTRL_IRQ_ENABLE 0x4000188 189/* write: Timer period config / read: TIMER IRQ ack. */190#define VORTEX_IRQ_STAT 0x1199c191 192/* DMA */193#define VORTEX_DMA_BUFFER 0x10200194#define VORTEX_ENGINE_CTRL 0x1060c195#define ENGINE_INIT 0x0L196 197 /* MIDI *//* GAME. */198#define VORTEX_MIDI_DATA 0x11000199#define VORTEX_MIDI_CMD 0x11004 /* Write command / Read status */200#define VORTEX_GAME_LEGACY 0x11008201#define VORTEX_CTRL2 0x1100c202#define CTRL2_GAME_ADCMODE 0x40203#define VORTEX_GAME_AXIS 0x11010204#define AXIS_SIZE 4205#define AXIS_RANGE 0x1fff206