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1/* SPDX-License-Identifier: GPL-2.0 */2/***************************************************************************3 * WT register offsets.4 *5 * Wed Oct 22 13:50:20 20036 * Copyright 2003 mjander7 * mjander@users.sourceforge.org8 ****************************************************************************/9#ifndef _AU88X0_WT_H10#define _AU88X0_WT_H11 12/* WT channels are grouped in banks. Each bank has 0x20 channels. */13/* Bank register address boundary is 0x8000 */14 15#define NR_WT_PB 0x2016 17/* WT bank base register (as dword address). */18#define WT_BAR(x) (((x)&0xffe0)<<0x8)19#define WT_BANK(x) (x>>5)20/* WT Bank registers */21#define WT_CTRL(bank) (((((bank)&1)<<0xd) + 0x00)<<2) /* 0x0000 */22#define WT_SRAMP(bank) (((((bank)&1)<<0xd) + 0x01)<<2) /* 0x0004 */23#define WT_DSREG(bank) (((((bank)&1)<<0xd) + 0x02)<<2) /* 0x0008 */24#define WT_MRAMP(bank) (((((bank)&1)<<0xd) + 0x03)<<2) /* 0x000c */25#define WT_GMODE(bank) (((((bank)&1)<<0xd) + 0x04)<<2) /* 0x0010 */26#define WT_ARAMP(bank) (((((bank)&1)<<0xd) + 0x05)<<2) /* 0x0014 */27/* WT Voice registers */28#define WT_STEREO(voice) ((WT_BAR(voice)+ 0x20 +(((voice)&0x1f)>>1))<<2) /* 0x0080 */29#define WT_MUTE(voice) ((WT_BAR(voice)+ 0x40 +((voice)&0x1f))<<2) /* 0x0100 */30#define WT_RUN(voice) ((WT_BAR(voice)+ 0x60 +((voice)&0x1f))<<2) /* 0x0180 */31/* Some kind of parameters. */32/* PARM0, PARM1 : Filter (0xFF000000), SampleRate (0x0000FFFF) */33/* PARM2, PARM3 : Still unknown */34#define WT_PARM(x,y) (((WT_BAR(x))+ 0x80 +(((x)&0x1f)<<2)+(y))<<2) /* 0x0200 */35#define WT_DELAY(x,y) (((WT_BAR(x))+ 0x100 +(((x)&0x1f)<<2)+(y))<<2) /* 0x0400 */36 37/* Numeric indexes used by SetReg() and GetReg() */38#if 039enum {40 run = 0, /* 0 W 1:run 0:stop */41 parm0, /* 1 W filter, samplerate */42 parm1, /* 2 W filter, samplerate */43 parm2, /* 3 W */44 parm3, /* 4 RW volume. This value is calculated using floating point ops. */45 sramp, /* 5 W */46 mute, /* 6 W 1:mute, 0:unmute */47 gmode, /* 7 RO Looks like only bit0 is used. */48 aramp, /* 8 W */49 mramp, /* 9 W */50 ctrl, /* a W */51 delay, /* b W All 4 values are written at once with same value. */52 dsreg, /* c (R)W */53} wt_reg;54#endif55 56typedef struct {57 u32 parm0; /* this_1E4 */58 u32 parm1; /* this_1E8 */59 u32 parm2; /* this_1EC */60 u32 parm3; /* this_1F0 */61 u32 this_1D0;62} wt_voice_t;63 64#endif /* _AU88X0_WT_H */65 66/* End of file */67