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1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef __SOUND_AZT3328_H3#define __SOUND_AZT3328_H4 5/* "PU" == "power-up value", as tested on PCI168 PCI rev. 106 * "WRITE_ONLY" == register does not indicate actual bit values */7 8/*** main I/O area port indices ***/9/* (only 0x70 of 0x80 bytes saved/restored by Windows driver) */10#define AZF_IO_SIZE_CTRL 0x8011#define AZF_IO_SIZE_CTRL_PM 0x7012 13/* the driver initialisation suggests a layout of 4 areas14 * within the main card control I/O:15 * from 0x00 (playback codec), from 0x20 (recording codec)16 * and from 0x40 (most certainly I2S out codec).17 * And another area from 0x60 to 0x6f (DirectX timer, IRQ management,18 * power management etc.???). */19 20#define AZF_IO_OFFS_CODEC_PLAYBACK 0x0021#define AZF_IO_OFFS_CODEC_CAPTURE 0x2022#define AZF_IO_OFFS_CODEC_I2S_OUT 0x4023 24#define IDX_IO_CODEC_DMA_FLAGS 0x00 /* PU:0x0000 */25 /* able to reactivate output after output muting due to 8/16bit26 * output change, just like 0x0002.27 * 0x0001 is the only bit that's able to start the DMA counter */28 #define DMA_RESUME 0x0001 /* paused if cleared? */29 /* 0x0002 *temporarily* set during DMA stopping. hmm30 * both 0x0002 and 0x0004 set in playback setup. */31 /* able to reactivate output after output muting due to 8/16bit32 * output change, just like 0x0001. */33 #define DMA_RUN_SOMETHING1 0x0002 /* \ alternated (toggled) */34 /* 0x0004: NOT able to reactivate output */35 #define DMA_RUN_SOMETHING2 0x0004 /* / bits */36 #define SOMETHING_ALMOST_ALWAYS_SET 0x0008 /* ???; can be modified */37 #define DMA_EPILOGUE_SOMETHING 0x001038 #define DMA_SOMETHING_ELSE 0x0020 /* ??? */39 #define SOMETHING_UNMODIFIABLE 0xffc0 /* unused? not modifiable */40#define IDX_IO_CODEC_IRQTYPE 0x02 /* PU:0x0001 */41 /* write back to flags in case flags are set, in order to ACK IRQ in handler42 * (bit 1 of port 0x64 indicates interrupt for one of these three types)43 * sometimes in this case it just writes 0xffff to globally ACK all IRQs44 * settings written are not reflected when reading back, though.45 * seems to be IRQ, too (frequently used: port |= 0x07 !), but who knows? */46 #define IRQ_SOMETHING 0x0001 /* something & ACK */47 #define IRQ_FINISHED_DMABUF_1 0x0002 /* 1st dmabuf finished & ACK */48 #define IRQ_FINISHED_DMABUF_2 0x0004 /* 2nd dmabuf finished & ACK */49 #define IRQMASK_SOME_STATUS_1 0x0008 /* \ related bits */50 #define IRQMASK_SOME_STATUS_2 0x0010 /* / (checked together in loop) */51 #define IRQMASK_UNMODIFIABLE 0xffe0 /* unused? not modifiable */52 /* start address of 1st DMA transfer area, PU:0x00000000 */53#define IDX_IO_CODEC_DMA_START_1 0x0454 /* start address of 2nd DMA transfer area, PU:0x00000000 */55#define IDX_IO_CODEC_DMA_START_2 0x0856 /* both lengths of DMA transfer areas, PU:0x0000000057 length1: offset 0x0c, length2: offset 0x0e */58#define IDX_IO_CODEC_DMA_LENGTHS 0x0c59#define IDX_IO_CODEC_DMA_CURRPOS 0x10 /* current DMA position, PU:0x00000000 */60 /* offset within current DMA transfer area, PU:0x0000 */61#define IDX_IO_CODEC_DMA_CURROFS 0x1462#define IDX_IO_CODEC_SOUNDFORMAT 0x16 /* PU:0x0010 */63 /* all unspecified bits can't be modified */64 #define SOUNDFORMAT_FREQUENCY_MASK 0x000f65 #define SOUNDFORMAT_XTAL1 0x0066 #define SOUNDFORMAT_XTAL2 0x0167 /* all _SUSPECTED_ values are not used by Windows drivers, so we don't68 * have any hard facts, only rough measurements.69 * All we know is that the crystal used on the board has 24.576MHz,70 * like many soundcards (which results in the frequencies below when71 * using certain divider values selected by the values below) */72 #define SOUNDFORMAT_FREQ_SUSPECTED_4000 0x0c | SOUNDFORMAT_XTAL173 #define SOUNDFORMAT_FREQ_SUSPECTED_4800 0x0a | SOUNDFORMAT_XTAL174 #define SOUNDFORMAT_FREQ_5510 0x0c | SOUNDFORMAT_XTAL275 #define SOUNDFORMAT_FREQ_6620 0x0a | SOUNDFORMAT_XTAL276 #define SOUNDFORMAT_FREQ_8000 0x00 | SOUNDFORMAT_XTAL1 /* also 0x0e | SOUNDFORMAT_XTAL1? */77 #define SOUNDFORMAT_FREQ_9600 0x08 | SOUNDFORMAT_XTAL178 #define SOUNDFORMAT_FREQ_11025 0x00 | SOUNDFORMAT_XTAL2 /* also 0x0e | SOUNDFORMAT_XTAL2? */79 #define SOUNDFORMAT_FREQ_SUSPECTED_13240 0x08 | SOUNDFORMAT_XTAL2 /* seems to be 6620 *2 */80 #define SOUNDFORMAT_FREQ_16000 0x02 | SOUNDFORMAT_XTAL181 #define SOUNDFORMAT_FREQ_22050 0x02 | SOUNDFORMAT_XTAL282 #define SOUNDFORMAT_FREQ_32000 0x04 | SOUNDFORMAT_XTAL183 #define SOUNDFORMAT_FREQ_44100 0x04 | SOUNDFORMAT_XTAL284 #define SOUNDFORMAT_FREQ_48000 0x06 | SOUNDFORMAT_XTAL185 #define SOUNDFORMAT_FREQ_SUSPECTED_66200 0x06 | SOUNDFORMAT_XTAL2 /* 66200 (13240 * 5); 64000 may have been nicer :-\ */86 #define SOUNDFORMAT_FLAG_16BIT 0x001087 #define SOUNDFORMAT_FLAG_2CHANNELS 0x002088 89 90/* define frequency helpers, for maximum value safety */91enum azf_freq_t {92#define AZF_FREQ(rate) AZF_FREQ_##rate = rate93 AZF_FREQ(4000),94 AZF_FREQ(4800),95 AZF_FREQ(5512),96 AZF_FREQ(6620),97 AZF_FREQ(8000),98 AZF_FREQ(9600),99 AZF_FREQ(11025),100 AZF_FREQ(13240),101 AZF_FREQ(16000),102 AZF_FREQ(22050),103 AZF_FREQ(32000),104 AZF_FREQ(44100),105 AZF_FREQ(48000),106 AZF_FREQ(66200),107#undef AZF_FREQ108};109 110/** DirectX timer, main interrupt area (FIXME: and something else?) **/ 111#define IDX_IO_TIMER_VALUE 0x60 /* found this timer area by pure luck :-) */112 /* timer countdown value; triggers IRQ when timer is finished */113 #define TIMER_VALUE_MASK 0x000fffffUL114 /* activate timer countdown */115 #define TIMER_COUNTDOWN_ENABLE 0x01000000UL116 /* trigger timer IRQ on zero transition */117 #define TIMER_IRQ_ENABLE 0x02000000UL118 /* being set in IRQ handler in case port 0x00 (hmm, not port 0x64!?!?)119 * had 0x0020 set upon IRQ handler */120 #define TIMER_IRQ_ACK 0x04000000UL121#define IDX_IO_IRQSTATUS 0x64122 /* some IRQ bit in here might also be used to signal a power-management timer123 * timeout, to request shutdown of the chip (e.g. AD1815JS has such a thing).124 * OPL3 hardware contains several timers which confusingly in most cases125 * are NOT routed to an IRQ, but some designs (e.g. LM4560) DO support that,126 * so I wouldn't be surprised at all to discover that AZF3328127 * supports that thing as well... */128 129 #define IRQ_PLAYBACK 0x0001130 #define IRQ_RECORDING 0x0002131 #define IRQ_I2S_OUT 0x0004 /* this IS I2S, right!? (untested) */132 #define IRQ_GAMEPORT 0x0008 /* Interrupt of Digital(ly) Enhanced Game Port */133 #define IRQ_MPU401 0x0010134 #define IRQ_TIMER 0x0020 /* DirectX timer */135 #define IRQ_UNKNOWN2 0x0040 /* probably unused, or possibly OPL3 timer? */136 #define IRQ_UNKNOWN3 0x0080 /* probably unused, or possibly OPL3 timer? */137#define IDX_IO_66H 0x66 /* writing 0xffff returns 0x0000 */138 /* this is set to e.g. 0x3ff or 0x300, and writable;139 * maybe some buffer limit, but I couldn't find out more, PU:0x00ff: */140#define IDX_IO_SOME_VALUE 0x68141 #define IO_68_RANDOM_TOGGLE1 0x0100 /* toggles randomly */142 #define IO_68_RANDOM_TOGGLE2 0x0200 /* toggles randomly */143 /* umm, nope, behaviour of these bits changes depending on what we wrote144 * to 0x6b!!145 * And they change upon playback/stop, too:146 * Writing a value to 0x68 will display this exact value during playback,147 * too but when stopped it can fall back to a rather different148 * seemingly random value). Hmm, possibly this is a register which149 * has a remote shadow which needs proper device supply which only exists150 * in case playback is active? Or is this driver-induced?151 */152 153/* this WORD can be set to have bits 0x0028 activated (FIXME: correct??);154 * actually inhibits PCM playback!!! maybe power management??: */155#define IDX_IO_6AH 0x6A /* WRITE_ONLY! */156 /* bit 5: enabling this will activate permanent counting of bytes 2/3157 * at gameport I/O (0xb402/3) (equal values each) and cause158 * gameport legacy I/O at 0x0200 to be _DISABLED_!159 * Is this Digital Enhanced Game Port Enable??? Or maybe it's Testmode160 * for Enhanced Digital Gameport (see 4D Wave DX card): */161 #define IO_6A_SOMETHING1_GAMEPORT 0x0020162 /* bit 8; sure, this _pauses_ playback (later resumes at same spot!),163 * but what the heck is this really about??: */164 #define IO_6A_PAUSE_PLAYBACK_BIT8 0x0100165 /* bit 9; sure, this _pauses_ playback (later resumes at same spot!),166 * but what the heck is this really about??: */167 #define IO_6A_PAUSE_PLAYBACK_BIT9 0x0200168 /* BIT8 and BIT9 are _NOT_ able to affect OPL3 MIDI playback,169 * thus it suggests influence on PCM only!!170 * However OTOH there seems to be no bit anywhere around here171 * which is able to disable OPL3... */172 /* bit 10: enabling this actually changes values at legacy gameport173 * I/O address (0x200); is this enabling of the Digital Enhanced Game Port???174 * Or maybe this simply switches off the NE558 circuit, since enabling this175 * still lets us evaluate button states, but not axis states */176 #define IO_6A_SOMETHING2_GAMEPORT 0x0400177 /* writing 0x0300: causes quite some crackling during178 * PC activity such as switching windows (PCI traffic??179 * --> FIFO/timing settings???) */180 /* writing 0x0100 plus/or 0x0200 inhibits playback */181 /* since the Windows .INF file has Flag_Enable_JoyStick and182 * Flag_Enable_SB_DOS_Emulation directly together, it stands to reason183 * that some other bit in this same register might be responsible184 * for SB DOS Emulation activation (note that the file did NOT define185 * a switch for OPL3!) */186#define IDX_IO_6CH 0x6C /* unknown; fully read-writable */187#define IDX_IO_6EH 0x6E188 /* writing 0xffff returns 0x83fe (or 0x03fe only).189 * writing 0x83 (and only 0x83!!) to 0x6f will cause 0x6c to switch190 * from 0000 to ffff. */191 192/* further I/O indices not saved/restored and not readable after writing,193 * so probably not used */194 195 196/*** Gameport area port indices ***/197/* (only 0x06 of 0x08 bytes saved/restored by Windows driver) */ 198#define AZF_IO_SIZE_GAME 0x08199#define AZF_IO_SIZE_GAME_PM 0x06200 201enum {202 AZF_GAME_LEGACY_IO_PORT = 0x200203};204 205#define IDX_GAME_LEGACY_COMPATIBLE 0x00206 /* in some operation mode, writing anything to this port207 * triggers an interrupt:208 * yup, that's in case IDX_GAME_01H has one of the209 * axis measurement bits enabled210 * (and of course one needs to have GAME_HWCFG_IRQ_ENABLE, too) */211 212#define IDX_GAME_AXES_CONFIG 0x01213 /* NOTE: layout of this register awfully similar (read: "identical??")214 * to AD1815JS.pdf (p.29) */215 216 /* enables axis 1 (X axis) measurement: */217 #define GAME_AXES_ENABLE_1 0x01218 /* enables axis 2 (Y axis) measurement: */219 #define GAME_AXES_ENABLE_2 0x02220 /* enables axis 3 (X axis) measurement: */221 #define GAME_AXES_ENABLE_3 0x04222 /* enables axis 4 (Y axis) measurement: */223 #define GAME_AXES_ENABLE_4 0x08224 /* selects the current axis to read the measured value of225 * (at IDX_GAME_AXIS_VALUE):226 * 00 = axis 1, 01 = axis 2, 10 = axis 3, 11 = axis 4: */227 #define GAME_AXES_READ_MASK 0x30228 /* enable to have the latch continuously accept ADC values229 * (and continuously cause interrupts in case interrupts are enabled);230 * AD1815JS.pdf says it's ~16ms interval there: */231 #define GAME_AXES_LATCH_ENABLE 0x40232 /* joystick data (measured axes) ready for reading: */233 #define GAME_AXES_SAMPLING_READY 0x80234 235 /* NOTE: other card specs (SiS960 and others!) state that the236 * game position latches should be frozen when reading and be freed237 * (== reset?) after reading!!!238 * Freezing most likely means disabling 0x40 (GAME_AXES_LATCH_ENABLE),239 * but how to free the value? */240 /* An internet search for "gameport latch ADC" should provide some insight241 * into how to program such a gameport system. */242 243 /* writing 0xf0 to 01H once reset both counters to 0, in some special mode!?244 * yup, in case 6AH 0x20 is not enabled245 * (and 0x40 is sufficient, 0xf0 is not needed) */246 247#define IDX_GAME_AXIS_VALUE 0x02248 /* R: value of currently configured axis (word value!);249 * W: trigger axis measurement */250 251#define IDX_GAME_HWCONFIG 0x04252 /* note: bits 4 to 7 are never set (== 0) when reading!253 * --> reserved bits? */254 /* enables IRQ notification upon axes measurement ready: */255 #define GAME_HWCFG_IRQ_ENABLE 0x01256 /* these bits choose a different frequency for the257 * internal ADC counter increment.258 * hmm, seems to be a combo of bits:259 * 00 --> standard frequency260 * 10 --> 1/2261 * 01 --> 1/20262 * 11 --> 1/200: */263 #define GAME_HWCFG_ADC_COUNTER_FREQ_MASK 0x06264 265 /* FIXME: these values might be reversed... */266 #define GAME_HWCFG_ADC_COUNTER_FREQ_STD 0267 #define GAME_HWCFG_ADC_COUNTER_FREQ_1_2 1268 #define GAME_HWCFG_ADC_COUNTER_FREQ_1_20 2269 #define GAME_HWCFG_ADC_COUNTER_FREQ_1_200 3270 271 /* enable gameport legacy I/O address (0x200)272 * I was unable to locate any configurability for a different address: */273 #define GAME_HWCFG_LEGACY_ADDRESS_ENABLE 0x08274 275/*** MPU401 ***/276#define AZF_IO_SIZE_MPU 0x04277#define AZF_IO_SIZE_MPU_PM 0x04278 279/*** OPL3 synth ***/280/* (only 0x06 of 0x08 bytes saved/restored by Windows driver) */281#define AZF_IO_SIZE_OPL3 0x08282#define AZF_IO_SIZE_OPL3_PM 0x06283/* hmm, given that a standard OPL3 has 4 registers only,284 * there might be some enhanced functionality lurking at the end285 * (especially since register 0x04 has a "non-empty" value 0xfe) */286 287/*** mixer I/O area port indices ***/288/* (only 0x22 of 0x40 bytes saved/restored by Windows driver)289 * UNFORTUNATELY azf3328 is NOT truly AC97 compliant: see main file intro */290#define AZF_IO_SIZE_MIXER 0x40291#define AZF_IO_SIZE_MIXER_PM 0x22292 293 #define MIXER_VOLUME_RIGHT_MASK 0x001f294 #define MIXER_VOLUME_LEFT_MASK 0x1f00295 #define MIXER_MUTE_MASK 0x8000296#define IDX_MIXER_RESET 0x00 /* does NOT seem to have AC97 ID bits */297#define IDX_MIXER_PLAY_MASTER 0x02298#define IDX_MIXER_MODEMOUT 0x04299#define IDX_MIXER_BASSTREBLE 0x06300 #define MIXER_BASSTREBLE_TREBLE_VOLUME_MASK 0x000e301 #define MIXER_BASSTREBLE_BASS_VOLUME_MASK 0x0e00302#define IDX_MIXER_PCBEEP 0x08303#define IDX_MIXER_MODEMIN 0x0a304#define IDX_MIXER_MIC 0x0c305 #define MIXER_MIC_MICGAIN_20DB_ENHANCEMENT_MASK 0x0040306#define IDX_MIXER_LINEIN 0x0e307#define IDX_MIXER_CDAUDIO 0x10308#define IDX_MIXER_VIDEO 0x12309#define IDX_MIXER_AUX 0x14310#define IDX_MIXER_WAVEOUT 0x16311#define IDX_MIXER_FMSYNTH 0x18312#define IDX_MIXER_REC_SELECT 0x1a313 #define MIXER_REC_SELECT_MIC 0x00314 #define MIXER_REC_SELECT_CD 0x01315 #define MIXER_REC_SELECT_VIDEO 0x02316 #define MIXER_REC_SELECT_AUX 0x03317 #define MIXER_REC_SELECT_LINEIN 0x04318 #define MIXER_REC_SELECT_MIXSTEREO 0x05319 #define MIXER_REC_SELECT_MIXMONO 0x06320 #define MIXER_REC_SELECT_MONOIN 0x07321#define IDX_MIXER_REC_VOLUME 0x1c322#define IDX_MIXER_ADVCTL1 0x1e323 /* unlisted bits are unmodifiable */324 #define MIXER_ADVCTL1_3DWIDTH_MASK 0x000e325 #define MIXER_ADVCTL1_HIFI3D_MASK 0x0300 /* yup, this is missing the high bit that official AC97 contains, plus it doesn't have linear bit value range behaviour but instead acts weirdly (possibly we're dealing with two *different* 3D settings here??) */326#define IDX_MIXER_ADVCTL2 0x20 /* subset of AC97_GENERAL_PURPOSE reg! */327 /* unlisted bits are unmodifiable */328 #define MIXER_ADVCTL2_LPBK 0x0080 /* Loopback mode -- Win driver: "WaveOut3DBypass"? mutes WaveOut at LineOut */329 #define MIXER_ADVCTL2_MS 0x0100 /* Mic Select 0=Mic1, 1=Mic2 -- Win driver: "ModemOutSelect"?? */330 #define MIXER_ADVCTL2_MIX 0x0200 /* Mono output select 0=Mix, 1=Mic; Win driver: "MonoSelectSource"?? */331 #define MIXER_ADVCTL2_3D 0x2000 /* 3D Enhancement 1=on */332 #define MIXER_ADVCTL2_POP 0x8000 /* Pcm Out Path, 0=pre 3D, 1=post 3D */333 334#define IDX_MIXER_SOMETHING30H 0x30 /* used, but unknown??? */335 336/* driver internal flags */337#define SET_CHAN_LEFT 1338#define SET_CHAN_RIGHT 2339 340/* helper macro to align I/O port ranges to 32bit I/O width */341#define AZF_ALIGN(x) (((x) + 3) & (~3))342 343#endif /* __SOUND_AZT3328_H */344