727 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright (c) 2004 James Courtier-Dutton <James@superbug.demon.co.uk>4 * Driver CA0106 chips. e.g. Sound Blaster Audigy LS and Live 24bit5 * Version: 0.0.226 *7 * FEATURES currently supported:8 * See ca0106_main.c for features.9 * 10 * Changelog:11 * Support interrupts per period.12 * Removed noise from Center/LFE channel when in Analog mode.13 * Rename and remove mixer controls.14 * 0.0.615 * Use separate card based DMA buffer for periods table list.16 * 0.0.717 * Change remove and rename ctrls into lists.18 * 0.0.819 * Try to fix capture sources.20 * 0.0.921 * Fix AC3 output.22 * Enable S32_LE format support.23 * 0.0.1024 * Enable playback 48000 and 96000 rates. (Rates other that these do not work, even with "plug:front".)25 * 0.0.1126 * Add Model name recognition.27 * 0.0.1228 * Correct interrupt timing. interrupt at end of period, instead of in the middle of a playback period.29 * Remove redundent "voice" handling.30 * 0.0.1331 * Single trigger call for multi channels.32 * 0.0.1433 * Set limits based on what the sound card hardware can do.34 * playback periods_min=2, periods_max=835 * capture hw constraints require period_size = n * 64 bytes.36 * playback hw constraints require period_size = n * 64 bytes.37 * 0.0.1538 * Separated ca0106.c into separate functional .c files.39 * 0.0.1640 * Implement 192000 sample rate.41 * 0.0.1742 * Add support for SB0410 and SB0413.43 * 0.0.1844 * Modified Copyright message.45 * 0.0.1946 * Added I2C and SPI registers. Filled in interrupt enable.47 * 0.0.2048 * Added GPIO info for SB Live 24bit.49 * 0.0.2150 * Implement support for Line-in capture on SB Live 24bit.51 * 0.0.2252 * Add support for mute control on SB Live 24bit (cards w/ SPI DAC)53 *54 * This code was initially based on code from ALSA's emu10k1x.c which is:55 * Copyright (c) by Francisco Moraes <fmoraes@nc.rr.com>56 */57 58/************************************************************************************************/59/* PCI function 0 registers, address = <val> + PCIBASE0 */60/************************************************************************************************/61 62#define CA0106_PTR 0x00 /* Indexed register set pointer register */63 /* NOTE: The CHANNELNUM and ADDRESS words can */64 /* be modified independently of each other. */65 /* CNL[1:0], ADDR[27:16] */66 67#define CA0106_DATA 0x04 /* Indexed register set data register */68 /* DATA[31:0] */69 70#define CA0106_IPR 0x08 /* Global interrupt pending register */71 /* Clear pending interrupts by writing a 1 to */72 /* the relevant bits and zero to the other bits */73#define IPR_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */74#define IPR_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */75#define IPR_SPDIF_IN_USER 0x00004000 /* SPDIF input user data has 16 more bits */76#define IPR_SPDIF_OUT_USER 0x00002000 /* SPDIF output user data needs 16 more bits */77#define IPR_SPDIF_OUT_FRAME 0x00001000 /* SPDIF frame about to start */78#define IPR_SPI 0x00000800 /* SPI transaction completed */79#define IPR_I2C_EEPROM 0x00000400 /* I2C EEPROM transaction completed */80#define IPR_I2C_DAC 0x00000200 /* I2C DAC transaction completed */81#define IPR_AI 0x00000100 /* Audio pending register changed. See PTR reg 0x76 */82#define IPR_GPI 0x00000080 /* General Purpose input changed */83#define IPR_SRC_LOCKED 0x00000040 /* SRC lock status changed */84#define IPR_SPDIF_STATUS 0x00000020 /* SPDIF status changed */85#define IPR_TIMER2 0x00000010 /* 192000Hz Timer */86#define IPR_TIMER1 0x00000008 /* 44100Hz Timer */87#define IPR_MIDI_RX_A 0x00000004 /* MIDI UART-A Receive buffer non-empty */88#define IPR_MIDI_TX_A 0x00000002 /* MIDI UART-A Transmit buffer empty */89#define IPR_PCI 0x00000001 /* PCI Bus error */90 91#define CA0106_INTE 0x0c /* Interrupt enable register */92 93#define INTE_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */94#define INTE_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */95#define INTE_SPDIF_IN_USER 0x00004000 /* SPDIF input user data has 16 more bits */96#define INTE_SPDIF_OUT_USER 0x00002000 /* SPDIF output user data needs 16 more bits */97#define INTE_SPDIF_OUT_FRAME 0x00001000 /* SPDIF frame about to start */98#define INTE_SPI 0x00000800 /* SPI transaction completed */99#define INTE_I2C_EEPROM 0x00000400 /* I2C EEPROM transaction completed */100#define INTE_I2C_DAC 0x00000200 /* I2C DAC transaction completed */101#define INTE_AI 0x00000100 /* Audio pending register changed. See PTR reg 0x75 */102#define INTE_GPI 0x00000080 /* General Purpose input changed */103#define INTE_SRC_LOCKED 0x00000040 /* SRC lock status changed */104#define INTE_SPDIF_STATUS 0x00000020 /* SPDIF status changed */105#define INTE_TIMER2 0x00000010 /* 192000Hz Timer */106#define INTE_TIMER1 0x00000008 /* 44100Hz Timer */107#define INTE_MIDI_RX_A 0x00000004 /* MIDI UART-A Receive buffer non-empty */108#define INTE_MIDI_TX_A 0x00000002 /* MIDI UART-A Transmit buffer empty */109#define INTE_PCI 0x00000001 /* PCI Bus error */110 111#define CA0106_UNKNOWN10 0x10 /* Unknown ??. Defaults to 0 */112#define CA0106_HCFG 0x14 /* Hardware config register */113 /* 0x1000 causes AC3 to fails. It adds a dither bit. */114 115#define HCFG_STAC 0x10000000 /* Special mode for STAC9460 Codec. */116#define HCFG_CAPTURE_I2S_BYPASS 0x08000000 /* 1 = bypass I2S input async SRC. */117#define HCFG_CAPTURE_SPDIF_BYPASS 0x04000000 /* 1 = bypass SPDIF input async SRC. */118#define HCFG_PLAYBACK_I2S_BYPASS 0x02000000 /* 0 = I2S IN mixer output, 1 = I2S IN1. */119#define HCFG_FORCE_LOCK 0x01000000 /* For test only. Force input SRC tracker to lock. */120#define HCFG_PLAYBACK_ATTENUATION 0x00006000 /* Playback attenuation mask. 0 = 0dB, 1 = 6dB, 2 = 12dB, 3 = Mute. */121#define HCFG_PLAYBACK_DITHER 0x00001000 /* 1 = Add dither bit to all playback channels. */122#define HCFG_PLAYBACK_S32_LE 0x00000800 /* 1 = S32_LE, 0 = S16_LE */123#define HCFG_CAPTURE_S32_LE 0x00000400 /* 1 = S32_LE, 0 = S16_LE (S32_LE current not working) */124#define HCFG_8_CHANNEL_PLAY 0x00000200 /* 1 = 8 channels, 0 = 2 channels per substream.*/125#define HCFG_8_CHANNEL_CAPTURE 0x00000100 /* 1 = 8 channels, 0 = 2 channels per substream.*/126#define HCFG_MONO 0x00000080 /* 1 = I2S Input mono */127#define HCFG_I2S_OUTPUT 0x00000010 /* 1 = I2S Output disabled */128#define HCFG_AC97 0x00000008 /* 0 = AC97 1.0, 1 = AC97 2.0 */129#define HCFG_LOCK_PLAYBACK_CACHE 0x00000004 /* 1 = Cancel bustmaster accesses to soundcache */130 /* NOTE: This should generally never be used. */131#define HCFG_LOCK_CAPTURE_CACHE 0x00000002 /* 1 = Cancel bustmaster accesses to soundcache */132 /* NOTE: This should generally never be used. */133#define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */134 /* Should be set to 1 when the EMU10K1 is */135 /* completely initialized. */136#define CA0106_GPIO 0x18 /* Defaults: 005f03a3-Analog, 005f02a2-SPDIF. */137 /* Here pins 0,1,2,3,4,,6 are output. 5,7 are input */138 /* For the Audigy LS, pin 0 (or bit 8) controls the SPDIF/Analog jack. */139 /* SB Live 24bit:140 * bit 8 0 = SPDIF in and out / 1 = Analog (Mic or Line)-in.141 * bit 9 0 = Mute / 1 = Analog out.142 * bit 10 0 = Line-in / 1 = Mic-in.143 * bit 11 0 = ? / 1 = ?144 * bit 12 0 = 48 Khz / 1 = 96 Khz Analog out on SB Live 24bit.145 * bit 13 0 = ? / 1 = ?146 * bit 14 0 = Mute / 1 = Analog out147 * bit 15 0 = ? / 1 = ?148 * Both bit 9 and bit 14 have to be set for analog sound to work on the SB Live 24bit.149 */150 /* 8 general purpose programmable In/Out pins.151 * GPI [8:0] Read only. Default 0.152 * GPO [15:8] Default 0x9. (Default to SPDIF jack enabled for SPDIF)153 * GPO Enable [23:16] Default 0x0f. Setting a bit to 1, causes the pin to be an output pin.154 */155#define CA0106_AC97DATA 0x1c /* AC97 register set data register (16 bit) */156 157#define CA0106_AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */158 159/********************************************************************************************************/160/* CA0106 pointer-offset register set, accessed through the PTR and DATA registers */161/********************************************************************************************************/162 163/* Initially all registers from 0x00 to 0x3f have zero contents. */164#define PLAYBACK_LIST_ADDR 0x00 /* Base DMA address of a list of pointers to each period/size */165 /* One list entry: 4 bytes for DMA address, 166 * 4 bytes for period_size << 16.167 * One list entry is 8 bytes long.168 * One list entry for each period in the buffer.169 */170 /* ADDR[31:0], Default: 0x0 */171#define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */172 /* SIZE[21:16], Default: 0x8 */173#define PLAYBACK_LIST_PTR 0x02 /* Pointer to the current period being played */174 /* PTR[5:0], Default: 0x0 */175#define PLAYBACK_UNKNOWN3 0x03 /* Not used ?? */176#define PLAYBACK_DMA_ADDR 0x04 /* Playback DMA address */177 /* DMA[31:0], Default: 0x0 */178#define PLAYBACK_PERIOD_SIZE 0x05 /* Playback period size. win2000 uses 0x04000000 */179 /* SIZE[31:16], Default: 0x0 */180#define PLAYBACK_POINTER 0x06 /* Playback period pointer. Used with PLAYBACK_LIST_PTR to determine buffer position currently in DAC */181 /* POINTER[15:0], Default: 0x0 */182#define PLAYBACK_PERIOD_END_ADDR 0x07 /* Playback fifo end address */183 /* END_ADDR[15:0], FLAG[16] 0 = don't stop, 1 = stop */184#define PLAYBACK_FIFO_OFFSET_ADDRESS 0x08 /* Current fifo offset address [21:16] */185 /* Cache size valid [5:0] */186#define PLAYBACK_UNKNOWN9 0x09 /* 0x9 to 0xf Unused */187#define CAPTURE_DMA_ADDR 0x10 /* Capture DMA address */188 /* DMA[31:0], Default: 0x0 */189#define CAPTURE_BUFFER_SIZE 0x11 /* Capture buffer size */190 /* SIZE[31:16], Default: 0x0 */191#define CAPTURE_POINTER 0x12 /* Capture buffer pointer. Sample currently in ADC */192 /* POINTER[15:0], Default: 0x0 */193#define CAPTURE_FIFO_OFFSET_ADDRESS 0x13 /* Current fifo offset address [21:16] */194 /* Cache size valid [5:0] */195#define PLAYBACK_LAST_SAMPLE 0x20 /* The sample currently being played */196/* 0x21 - 0x3f unused */197#define BASIC_INTERRUPT 0x40 /* Used by both playback and capture interrupt handler */198 /* Playback (0x1<<channel_id) */199 /* Capture (0x100<<channel_id) */200 /* Playback sample rate 96000 = 0x20000 */201 /* Start Playback [3:0] (one bit per channel)202 * Start Capture [11:8] (one bit per channel)203 * Playback rate [23:16] (2 bits per channel) (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)204 * Playback mixer in enable [27:24] (one bit per channel)205 * Playback mixer out enable [31:28] (one bit per channel)206 */207/* The Digital out jack is shared with the Center/LFE Analogue output. 208 * The jack has 4 poles. I will call 1 - Tip, 2 - Next to 1, 3 - Next to 2, 4 - Next to 3209 * For Analogue: 1 -> Center Speaker, 2 -> Sub Woofer, 3 -> Ground, 4 -> Ground210 * For Digital: 1 -> Front SPDIF, 2 -> Rear SPDIF, 3 -> Center/Subwoofer SPDIF, 4 -> Ground.211 * Standard 4 pole Video A/V cable with RCA outputs: 1 -> White, 2 -> Yellow, 3 -> Shield on all three, 4 -> Red.212 * So, from this you can see that you cannot use a Standard 4 pole Video A/V cable with the SB Audigy LS card.213 */214/* The Front SPDIF PCM gets mixed with samples from the AC97 codec, so can only work for Stereo PCM and not AC3/DTS215 * The Rear SPDIF can be used for Stereo PCM and also AC3/DTS216 * The Center/LFE SPDIF cannot be used for AC3/DTS, but can be used for Stereo PCM.217 * Summary: For ALSA we use the Rear channel for SPDIF Digital AC3/DTS output218 */219/* A standard 2 pole mono mini-jack to RCA plug can be used for SPDIF Stereo PCM output from the Front channel.220 * A standard 3 pole stereo mini-jack to 2 RCA plugs can be used for SPDIF AC3/DTS and Stereo PCM output utilising the Rear channel and just one of the RCA plugs. 221 */222#define SPCS0 0x41 /* SPDIF output Channel Status 0 register. For Rear. default=0x02108004, non-audio=0x02108006 */223#define SPCS1 0x42 /* SPDIF output Channel Status 1 register. For Front */224#define SPCS2 0x43 /* SPDIF output Channel Status 2 register. For Center/LFE */225#define SPCS3 0x44 /* SPDIF output Channel Status 3 register. Unknown */226 /* When Channel set to 0: */227#define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */228#define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */229#define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */230#define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */231#define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */232#define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */233#define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */234#define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */235#define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */236#define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */237#define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */238#define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */239#define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */240#define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */241#define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */242#define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */243#define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */244#define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */245#define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */246#define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */247#define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */248#define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */249#define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */250 251 /* When Channel set to 1: */252#define SPCS_WORD_LENGTH_MASK 0x0000000f /* Word Length Mask */253#define SPCS_WORD_LENGTH_16 0x00000008 /* Word Length 16 bit */254#define SPCS_WORD_LENGTH_17 0x00000006 /* Word Length 17 bit */255#define SPCS_WORD_LENGTH_18 0x00000004 /* Word Length 18 bit */256#define SPCS_WORD_LENGTH_19 0x00000002 /* Word Length 19 bit */257#define SPCS_WORD_LENGTH_20A 0x0000000a /* Word Length 20 bit */258#define SPCS_WORD_LENGTH_20 0x00000009 /* Word Length 20 bit (both 0xa and 0x9 are 20 bit) */259#define SPCS_WORD_LENGTH_21 0x00000007 /* Word Length 21 bit */260#define SPCS_WORD_LENGTH_22 0x00000005 /* Word Length 22 bit */261#define SPCS_WORD_LENGTH_23 0x00000003 /* Word Length 23 bit */262#define SPCS_WORD_LENGTH_24 0x0000000b /* Word Length 24 bit */263#define SPCS_ORIGINAL_SAMPLE_RATE_MASK 0x000000f0 /* Original Sample rate */264#define SPCS_ORIGINAL_SAMPLE_RATE_NONE 0x00000000 /* Original Sample rate not indicated */265#define SPCS_ORIGINAL_SAMPLE_RATE_16000 0x00000010 /* Original Sample rate */266#define SPCS_ORIGINAL_SAMPLE_RATE_RES1 0x00000020 /* Original Sample rate */267#define SPCS_ORIGINAL_SAMPLE_RATE_32000 0x00000030 /* Original Sample rate */268#define SPCS_ORIGINAL_SAMPLE_RATE_12000 0x00000040 /* Original Sample rate */269#define SPCS_ORIGINAL_SAMPLE_RATE_11025 0x00000050 /* Original Sample rate */270#define SPCS_ORIGINAL_SAMPLE_RATE_8000 0x00000060 /* Original Sample rate */271#define SPCS_ORIGINAL_SAMPLE_RATE_RES2 0x00000070 /* Original Sample rate */272#define SPCS_ORIGINAL_SAMPLE_RATE_192000 0x00000080 /* Original Sample rate */273#define SPCS_ORIGINAL_SAMPLE_RATE_24000 0x00000090 /* Original Sample rate */274#define SPCS_ORIGINAL_SAMPLE_RATE_96000 0x000000a0 /* Original Sample rate */275#define SPCS_ORIGINAL_SAMPLE_RATE_48000 0x000000b0 /* Original Sample rate */276#define SPCS_ORIGINAL_SAMPLE_RATE_176400 0x000000c0 /* Original Sample rate */277#define SPCS_ORIGINAL_SAMPLE_RATE_22050 0x000000d0 /* Original Sample rate */278#define SPCS_ORIGINAL_SAMPLE_RATE_88200 0x000000e0 /* Original Sample rate */279#define SPCS_ORIGINAL_SAMPLE_RATE_44100 0x000000f0 /* Original Sample rate */280 281#define SPDIF_SELECT1 0x45 /* Enables SPDIF or Analogue outputs 0-SPDIF, 0xf00-Analogue */282 /* 0x100 - Front, 0x800 - Rear, 0x200 - Center/LFE.283 * But as the jack is shared, use 0xf00.284 * The Windows2000 driver uses 0x0000000f for both digital and analog.285 * 0xf00 introduces interesting noises onto the Center/LFE.286 * If you turn the volume up, you hear computer noise,287 * e.g. mouse moving, changing between app windows etc.288 * So, I am going to set this to 0x0000000f all the time now,289 * same as the windows driver does.290 * Use register SPDIF_SELECT2(0x72) to switch between SPDIF and Analog.291 */292 /* When Channel = 0:293 * Wide SPDIF format [3:0] (one bit for each channel) (0=20bit, 1=24bit)294 * Tristate SPDIF Output [11:8] (one bit for each channel) (0=Not tristate, 1=Tristate)295 * SPDIF Bypass enable [19:16] (one bit for each channel) (0=Not bypass, 1=Bypass)296 */297 /* When Channel = 1:298 * SPDIF 0 User data [7:0]299 * SPDIF 1 User data [15:8]300 * SPDIF 0 User data [23:16]301 * SPDIF 0 User data [31:24]302 * User data can be sent by using the SPDIF output frame pending and SPDIF output user bit interrupts.303 */304#define WATERMARK 0x46 /* Test bit to indicate cache usage level */305#define SPDIF_INPUT_STATUS 0x49 /* SPDIF Input status register. Bits the same as SPCS.306 * When Channel = 0: Bits the same as SPCS channel 0.307 * When Channel = 1: Bits the same as SPCS channel 1.308 * When Channel = 2:309 * SPDIF Input User data [16:0]310 * SPDIF Input Frame count [21:16]311 */312#define CAPTURE_CACHE_DATA 0x50 /* 0x50-0x5f Recorded samples. */313#define CAPTURE_SOURCE 0x60 /* Capture Source 0 = MIC */314#define CAPTURE_SOURCE_CHANNEL0 0xf0000000 /* Mask for selecting the Capture sources */315#define CAPTURE_SOURCE_CHANNEL1 0x0f000000 /* 0 - SPDIF mixer output. */316#define CAPTURE_SOURCE_CHANNEL2 0x00f00000 /* 1 - What you hear or . 2 - ?? */317#define CAPTURE_SOURCE_CHANNEL3 0x000f0000 /* 3 - Mic in, Line in, TAD in, Aux in. */318#define CAPTURE_SOURCE_RECORD_MAP 0x0000ffff /* Default 0x00e4 */319 /* Record Map [7:0] (2 bits per channel) 0=mapped to channel 0, 1=mapped to channel 1, 2=mapped to channel2, 3=mapped to channel3 320 * Record source select for channel 0 [18:16]321 * Record source select for channel 1 [22:20]322 * Record source select for channel 2 [26:24]323 * Record source select for channel 3 [30:28]324 * 0 - SPDIF mixer output.325 * 1 - i2s mixer output.326 * 2 - SPDIF input.327 * 3 - i2s input.328 * 4 - AC97 capture.329 * 5 - SRC output.330 */331#define CAPTURE_VOLUME1 0x61 /* Capture volume per channel 0-3 */332#define CAPTURE_VOLUME2 0x62 /* Capture volume per channel 4-7 */333 334#define PLAYBACK_ROUTING1 0x63 /* Playback routing of channels 0-7. Effects AC3 output. Default 0x32765410 */335#define ROUTING1_REAR 0x77000000 /* Channel_id 0 sends to 10, Channel_id 1 sends to 32 */336#define ROUTING1_NULL 0x00770000 /* Channel_id 2 sends to 54, Channel_id 3 sends to 76 */337#define ROUTING1_CENTER_LFE 0x00007700 /* 0x32765410 means, send Channel_id 0 to FRONT, Channel_id 1 to REAR */338#define ROUTING1_FRONT 0x00000077 /* Channel_id 2 to CENTER_LFE, Channel_id 3 to NULL. */339 /* Channel_id's handle stereo channels. Channel X is a single mono channel */340 /* Host is input from the PCI bus. */341 /* Host channel 0 [2:0] -> SPDIF Mixer/Router channel 0-7.342 * Host channel 1 [6:4] -> SPDIF Mixer/Router channel 0-7.343 * Host channel 2 [10:8] -> SPDIF Mixer/Router channel 0-7.344 * Host channel 3 [14:12] -> SPDIF Mixer/Router channel 0-7.345 * Host channel 4 [18:16] -> SPDIF Mixer/Router channel 0-7.346 * Host channel 5 [22:20] -> SPDIF Mixer/Router channel 0-7.347 * Host channel 6 [26:24] -> SPDIF Mixer/Router channel 0-7.348 * Host channel 7 [30:28] -> SPDIF Mixer/Router channel 0-7.349 */350 351#define PLAYBACK_ROUTING2 0x64 /* Playback Routing . Feeding Capture channels back into Playback. Effects AC3 output. Default 0x76767676 */352 /* SRC is input from the capture inputs. */353 /* SRC channel 0 [2:0] -> SPDIF Mixer/Router channel 0-7.354 * SRC channel 1 [6:4] -> SPDIF Mixer/Router channel 0-7.355 * SRC channel 2 [10:8] -> SPDIF Mixer/Router channel 0-7.356 * SRC channel 3 [14:12] -> SPDIF Mixer/Router channel 0-7.357 * SRC channel 4 [18:16] -> SPDIF Mixer/Router channel 0-7.358 * SRC channel 5 [22:20] -> SPDIF Mixer/Router channel 0-7.359 * SRC channel 6 [26:24] -> SPDIF Mixer/Router channel 0-7.360 * SRC channel 7 [30:28] -> SPDIF Mixer/Router channel 0-7.361 */362 363#define PLAYBACK_MUTE 0x65 /* Unknown. While playing 0x0, while silent 0x00fc0000 */364 /* SPDIF Mixer input control:365 * Invert SRC to SPDIF Mixer [7-0] (One bit per channel)366 * Invert Host to SPDIF Mixer [15:8] (One bit per channel)367 * SRC to SPDIF Mixer disable [23:16] (One bit per channel)368 * Host to SPDIF Mixer disable [31:24] (One bit per channel)369 */370#define PLAYBACK_VOLUME1 0x66 /* Playback SPDIF volume per channel. Set to the same PLAYBACK_VOLUME(0x6a) */371 /* PLAYBACK_VOLUME1 must be set to 30303030 for SPDIF AC3 Playback */372 /* SPDIF mixer input volume. 0=12dB, 0x30=0dB, 0xFE=-51.5dB, 0xff=Mute */373 /* One register for each of the 4 stereo streams. */374 /* SRC Right volume [7:0]375 * SRC Left volume [15:8]376 * Host Right volume [23:16]377 * Host Left volume [31:24]378 */379#define CAPTURE_ROUTING1 0x67 /* Capture Routing. Default 0x32765410 */380 /* Similar to register 0x63, except that the destination is the I2S mixer instead of the SPDIF mixer. I.E. Outputs to the Analog outputs instead of SPDIF. */381#define CAPTURE_ROUTING2 0x68 /* Unknown Routing. Default 0x76767676 */382 /* Similar to register 0x64, except that the destination is the I2S mixer instead of the SPDIF mixer. I.E. Outputs to the Analog outputs instead of SPDIF. */383#define CAPTURE_MUTE 0x69 /* Unknown. While capturing 0x0, while silent 0x00fc0000 */384 /* Similar to register 0x65, except that the destination is the I2S mixer instead of the SPDIF mixer. I.E. Outputs to the Analog outputs instead of SPDIF. */385#define PLAYBACK_VOLUME2 0x6a /* Playback Analog volume per channel. Does not effect AC3 output */386 /* Similar to register 0x66, except that the destination is the I2S mixer instead of the SPDIF mixer. I.E. Outputs to the Analog outputs instead of SPDIF. */387#define UNKNOWN6b 0x6b /* Unknown. Readonly. Default 00400000 00400000 00400000 00400000 */388#define MIDI_UART_A_DATA 0x6c /* Midi Uart A Data */389#define MIDI_UART_A_CMD 0x6d /* Midi Uart A Command/Status */390#define MIDI_UART_B_DATA 0x6e /* Midi Uart B Data (currently unused) */391#define MIDI_UART_B_CMD 0x6f /* Midi Uart B Command/Status (currently unused) */392 393/* unique channel identifier for midi->channel */394 395#define CA0106_MIDI_CHAN_A 0x1396#define CA0106_MIDI_CHAN_B 0x2397 398/* from mpu401 */399 400#define CA0106_MIDI_INPUT_AVAIL 0x80401#define CA0106_MIDI_OUTPUT_READY 0x40402#define CA0106_MPU401_RESET 0xff403#define CA0106_MPU401_ENTER_UART 0x3f404#define CA0106_MPU401_ACK 0xfe405 406#define SAMPLE_RATE_TRACKER_STATUS 0x70 /* Readonly. Default 00108000 00108000 00500000 00500000 */407 /* Estimated sample rate [19:0] Relative to 48kHz. 0x8000 = 1.0408 * Rate Locked [20]409 * SPDIF Locked [21] For SPDIF channel only.410 * Valid Audio [22] For SPDIF channel only.411 */412#define CAPTURE_CONTROL 0x71 /* Some sort of routing. default = 40c81000 30303030 30300000 00700000 */413 /* Channel_id 0: 0x40c81000 must be changed to 0x40c80000 for SPDIF AC3 input or output. */414 /* Channel_id 1: 0xffffffff(mute) 0x30303030(max) controls CAPTURE feedback into PLAYBACK. */415 /* Sample rate output control register Channel=0416 * Sample output rate [1:0] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)417 * Sample input rate [3:2] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz)418 * SRC input source select [4] 0=Audio from digital mixer, 1=Audio from analog source.419 * Record rate [9:8] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz)420 * Record mixer output enable [12:10] 421 * I2S input rate master mode [15:14] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)422 * I2S output rate [17:16] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)423 * I2S output source select [18] (0=Audio from host, 1=Audio from SRC)424 * Record mixer I2S enable [20:19] (enable/disable i2sin1 and i2sin0)425 * I2S output master clock select [21] (0=256*I2S output rate, 1=512*I2S output rate.)426 * I2S input master clock select [22] (0=256*I2S input rate, 1=512*I2S input rate.)427 * I2S input mode [23] (0=Slave, 1=Master)428 * SPDIF output rate [25:24] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)429 * SPDIF output source select [26] (0=host, 1=SRC)430 * Not used [27]431 * Record Source 0 input [29:28] (0=SPDIF in, 1=I2S in, 2=AC97 Mic, 3=AC97 PCM)432 * Record Source 1 input [31:30] (0=SPDIF in, 1=I2S in, 2=AC97 Mic, 3=AC97 PCM)433 */ 434 /* Sample rate output control register Channel=1435 * I2S Input 0 volume Right [7:0]436 * I2S Input 0 volume Left [15:8]437 * I2S Input 1 volume Right [23:16]438 * I2S Input 1 volume Left [31:24]439 */440 /* Sample rate output control register Channel=2441 * SPDIF Input volume Right [23:16]442 * SPDIF Input volume Left [31:24]443 */444 /* Sample rate output control register Channel=3445 * No used446 */447#define SPDIF_SELECT2 0x72 /* Some sort of routing. Channel_id 0 only. default = 0x0f0f003f. Analog 0x000b0000, Digital 0x0b000000 */448#define ROUTING2_FRONT_MASK 0x00010000 /* Enable for Front speakers. */449#define ROUTING2_CENTER_LFE_MASK 0x00020000 /* Enable for Center/LFE speakers. */450#define ROUTING2_REAR_MASK 0x00080000 /* Enable for Rear speakers. */451 /* Audio output control452 * AC97 output enable [5:0]453 * I2S output enable [19:16]454 * SPDIF output enable [27:24]455 */ 456#define UNKNOWN73 0x73 /* Unknown. Readonly. Default 0x0 */457#define CHIP_VERSION 0x74 /* P17 Chip version. Channel_id 0 only. Default 00000071 */458#define EXTENDED_INT_MASK 0x75 /* Used by both playback and capture interrupt handler */459 /* Sets which Interrupts are enabled. */460 /* 0x00000001 = Half period. Playback.461 * 0x00000010 = Full period. Playback.462 * 0x00000100 = Half buffer. Playback.463 * 0x00001000 = Full buffer. Playback.464 * 0x00010000 = Half buffer. Capture.465 * 0x00100000 = Full buffer. Capture.466 * Capture can only do 2 periods.467 * 0x01000000 = End audio. Playback.468 * 0x40000000 = Half buffer Playback,Caputre xrun.469 * 0x80000000 = Full buffer Playback,Caputre xrun.470 */471#define EXTENDED_INT 0x76 /* Used by both playback and capture interrupt handler */472 /* Shows which interrupts are active at the moment. */473 /* Same bit layout as EXTENDED_INT_MASK */474#define COUNTER77 0x77 /* Counter range 0 to 0x3fffff, 192000 counts per second. */475#define COUNTER78 0x78 /* Counter range 0 to 0x3fffff, 44100 counts per second. */476#define EXTENDED_INT_TIMER 0x79 /* Channel_id 0 only. Used by both playback and capture interrupt handler */477 /* Causes interrupts based on timer intervals. */478#define SPI 0x7a /* SPI: Serial Interface Register */479#define I2C_A 0x7b /* I2C Address. 32 bit */480#define I2C_D0 0x7c /* I2C Data Port 0. 32 bit */481#define I2C_D1 0x7d /* I2C Data Port 1. 32 bit */482//I2C values483#define I2C_A_ADC_ADD_MASK 0x000000fe //The address is a 7 bit address484#define I2C_A_ADC_RW_MASK 0x00000001 //bit mask for R/W485#define I2C_A_ADC_TRANS_MASK 0x00000010 //Bit mask for I2c address DAC value486#define I2C_A_ADC_ABORT_MASK 0x00000020 //Bit mask for I2C transaction abort flag487#define I2C_A_ADC_LAST_MASK 0x00000040 //Bit mask for Last word transaction488#define I2C_A_ADC_BYTE_MASK 0x00000080 //Bit mask for Byte Mode489 490#define I2C_A_ADC_ADD 0x00000034 //This is the Device address for ADC 491#define I2C_A_ADC_READ 0x00000001 //To perform a read operation492#define I2C_A_ADC_START 0x00000100 //Start I2C transaction493#define I2C_A_ADC_ABORT 0x00000200 //I2C transaction abort494#define I2C_A_ADC_LAST 0x00000400 //I2C last transaction495#define I2C_A_ADC_BYTE 0x00000800 //I2C one byte mode496 497#define I2C_D_ADC_REG_MASK 0xfe000000 //ADC address register 498#define I2C_D_ADC_DAT_MASK 0x01ff0000 //ADC data register499 500#define ADC_TIMEOUT 0x00000007 //ADC Timeout Clock Disable501#define ADC_IFC_CTRL 0x0000000b //ADC Interface Control502#define ADC_MASTER 0x0000000c //ADC Master Mode Control503#define ADC_POWER 0x0000000d //ADC PowerDown Control504#define ADC_ATTEN_ADCL 0x0000000e //ADC Attenuation ADCL505#define ADC_ATTEN_ADCR 0x0000000f //ADC Attenuation ADCR506#define ADC_ALC_CTRL1 0x00000010 //ADC ALC Control 1507#define ADC_ALC_CTRL2 0x00000011 //ADC ALC Control 2508#define ADC_ALC_CTRL3 0x00000012 //ADC ALC Control 3509#define ADC_NOISE_CTRL 0x00000013 //ADC Noise Gate Control510#define ADC_LIMIT_CTRL 0x00000014 //ADC Limiter Control511#define ADC_MUX 0x00000015 //ADC Mux offset512 513#if 0514/* FIXME: Not tested yet. */515#define ADC_GAIN_MASK 0x000000ff //Mask for ADC Gain516#define ADC_ZERODB 0x000000cf //Value to set ADC to 0dB517#define ADC_MUTE_MASK 0x000000c0 //Mask for ADC mute518#define ADC_MUTE 0x000000c0 //Value to mute ADC519#define ADC_OSR 0x00000008 //Mask for ADC oversample rate select520#define ADC_TIMEOUT_DISABLE 0x00000008 //Value and mask to disable Timeout clock521#define ADC_HPF_DISABLE 0x00000100 //Value and mask to disable High pass filter522#define ADC_TRANWIN_MASK 0x00000070 //Mask for Length of Transient Window523#endif524 525#define ADC_MUX_MASK 0x0000000f //Mask for ADC Mux526#define ADC_MUX_PHONE 0x00000001 //Value to select TAD at ADC Mux (Not used)527#define ADC_MUX_MIC 0x00000002 //Value to select Mic at ADC Mux528#define ADC_MUX_LINEIN 0x00000004 //Value to select LineIn at ADC Mux529#define ADC_MUX_AUX 0x00000008 //Value to select Aux at ADC Mux530 531#define SET_CHANNEL 0 /* Testing channel outputs 0=Front, 1=Center/LFE, 2=Unknown, 3=Rear */532#define PCM_FRONT_CHANNEL 0533#define PCM_REAR_CHANNEL 1534#define PCM_CENTER_LFE_CHANNEL 2535#define PCM_UNKNOWN_CHANNEL 3536#define CONTROL_FRONT_CHANNEL 0537#define CONTROL_REAR_CHANNEL 3538#define CONTROL_CENTER_LFE_CHANNEL 1539#define CONTROL_UNKNOWN_CHANNEL 2540 541 542/* Based on WM8768 Datasheet Rev 4.2 page 32 */543#define SPI_REG_MASK 0x1ff /* 16-bit SPI writes have a 7-bit address */544#define SPI_REG_SHIFT 9 /* followed by 9 bits of data */545 546#define SPI_LDA1_REG 0 /* digital attenuation */547#define SPI_RDA1_REG 1548#define SPI_LDA2_REG 4549#define SPI_RDA2_REG 5550#define SPI_LDA3_REG 6551#define SPI_RDA3_REG 7552#define SPI_LDA4_REG 13553#define SPI_RDA4_REG 14554#define SPI_MASTDA_REG 8555 556#define SPI_DA_BIT_UPDATE (1<<8) /* update attenuation values */557#define SPI_DA_BIT_0dB 0xff /* 0 dB */558#define SPI_DA_BIT_infdB 0x00 /* inf dB attenuation (mute) */559 560#define SPI_PL_REG 2561#define SPI_PL_BIT_L_M (0<<5) /* left channel = mute */562#define SPI_PL_BIT_L_L (1<<5) /* left channel = left */563#define SPI_PL_BIT_L_R (2<<5) /* left channel = right */564#define SPI_PL_BIT_L_C (3<<5) /* left channel = (L+R)/2 */565#define SPI_PL_BIT_R_M (0<<7) /* right channel = mute */566#define SPI_PL_BIT_R_L (1<<7) /* right channel = left */567#define SPI_PL_BIT_R_R (2<<7) /* right channel = right */568#define SPI_PL_BIT_R_C (3<<7) /* right channel = (L+R)/2 */569#define SPI_IZD_REG 2570#define SPI_IZD_BIT (0<<4) /* infinite zero detect */571 572#define SPI_FMT_REG 3573#define SPI_FMT_BIT_RJ (0<<0) /* right justified mode */574#define SPI_FMT_BIT_LJ (1<<0) /* left justified mode */575#define SPI_FMT_BIT_I2S (2<<0) /* I2S mode */576#define SPI_FMT_BIT_DSP (3<<0) /* DSP Modes A or B */577#define SPI_LRP_REG 3578#define SPI_LRP_BIT (1<<2) /* invert LRCLK polarity */579#define SPI_BCP_REG 3580#define SPI_BCP_BIT (1<<3) /* invert BCLK polarity */581#define SPI_IWL_REG 3582#define SPI_IWL_BIT_16 (0<<4) /* 16-bit world length */583#define SPI_IWL_BIT_20 (1<<4) /* 20-bit world length */584#define SPI_IWL_BIT_24 (2<<4) /* 24-bit world length */585#define SPI_IWL_BIT_32 (3<<4) /* 32-bit world length */586 587#define SPI_MS_REG 10588#define SPI_MS_BIT (1<<5) /* master mode */589#define SPI_RATE_REG 10 /* only applies in master mode */590#define SPI_RATE_BIT_128 (0<<6) /* MCLK = LRCLK * 128 */591#define SPI_RATE_BIT_192 (1<<6)592#define SPI_RATE_BIT_256 (2<<6)593#define SPI_RATE_BIT_384 (3<<6)594#define SPI_RATE_BIT_512 (4<<6)595#define SPI_RATE_BIT_768 (5<<6)596 597/* They really do label the bit for the 4th channel "4" and not "3" */598#define SPI_DMUTE0_REG 9599#define SPI_DMUTE1_REG 9600#define SPI_DMUTE2_REG 9601#define SPI_DMUTE4_REG 15602#define SPI_DMUTE0_BIT (1<<3)603#define SPI_DMUTE1_BIT (1<<4)604#define SPI_DMUTE2_BIT (1<<5)605#define SPI_DMUTE4_BIT (1<<2)606 607#define SPI_PHASE0_REG 3608#define SPI_PHASE1_REG 3609#define SPI_PHASE2_REG 3610#define SPI_PHASE4_REG 15611#define SPI_PHASE0_BIT (1<<6)612#define SPI_PHASE1_BIT (1<<7)613#define SPI_PHASE2_BIT (1<<8)614#define SPI_PHASE4_BIT (1<<3)615 616#define SPI_PDWN_REG 2 /* power down all DACs */617#define SPI_PDWN_BIT (1<<2)618#define SPI_DACD0_REG 10 /* power down individual DACs */619#define SPI_DACD1_REG 10620#define SPI_DACD2_REG 10621#define SPI_DACD4_REG 15622#define SPI_DACD0_BIT (1<<1)623#define SPI_DACD1_BIT (1<<2)624#define SPI_DACD2_BIT (1<<3)625#define SPI_DACD4_BIT (1<<0) /* datasheet error says it's 1 */626 627#define SPI_PWRDNALL_REG 10 /* power down everything */628#define SPI_PWRDNALL_BIT (1<<4)629 630#include "ca_midi.h"631 632struct snd_ca0106;633 634struct snd_ca0106_channel {635 struct snd_ca0106 *emu;636 int number;637 int use;638 void (*interrupt)(struct snd_ca0106 *emu, struct snd_ca0106_channel *channel);639 struct snd_ca0106_pcm *epcm;640};641 642struct snd_ca0106_pcm {643 struct snd_ca0106 *emu;644 struct snd_pcm_substream *substream;645 int channel_id;646 unsigned short running;647};648 649struct snd_ca0106_details {650 u32 serial;651 char * name;652 int ac97; /* ac97 = 0 -> Select MIC, Line in, TAD in, AUX in.653 ac97 = 1 -> Default to AC97 in. */654 int gpio_type; /* gpio_type = 1 -> shared mic-in/line-in655 gpio_type = 2 -> shared side-out/line-in. */656 int i2c_adc; /* with i2c_adc=1, the driver adds some capture volume657 controls, phone, mic, line-in and aux. */658 u16 spi_dac; /* spi_dac = 0 -> no spi interface for DACs659 spi_dac = 0x<front><rear><center-lfe><side>660 -> specifies DAC id for each channel pair. */661};662 663// definition of the chip-specific record664struct snd_ca0106 {665 struct snd_card *card;666 const struct snd_ca0106_details *details;667 struct pci_dev *pci;668 669 unsigned long port;670 int irq;671 672 unsigned int serial; /* serial number */673 unsigned short model; /* subsystem id */674 675 spinlock_t emu_lock;676 677 struct snd_ac97 *ac97;678 struct snd_pcm *pcm[4];679 680 struct snd_ca0106_channel playback_channels[4];681 struct snd_ca0106_channel capture_channels[4];682 u32 spdif_bits[4]; /* s/pdif out default setup */683 u32 spdif_str_bits[4]; /* s/pdif out per-stream setup */684 int spdif_enable;685 int capture_source;686 int i2c_capture_source;687 u8 i2c_capture_volume[4][2];688 int capture_mic_line_in;689 690 struct snd_dma_buffer *buffer;691 692 struct snd_ca_midi midi;693 struct snd_ca_midi midi2;694 695 u16 spi_dac_reg[16];696 697#ifdef CONFIG_PM_SLEEP698#define NUM_SAVED_VOLUMES 9699 unsigned int saved_vol[NUM_SAVED_VOLUMES];700#endif701};702 703int snd_ca0106_mixer(struct snd_ca0106 *emu);704int snd_ca0106_proc_init(struct snd_ca0106 * emu);705 706unsigned int snd_ca0106_ptr_read(struct snd_ca0106 * emu, 707 unsigned int reg, 708 unsigned int chn);709 710void snd_ca0106_ptr_write(struct snd_ca0106 *emu, 711 unsigned int reg, 712 unsigned int chn, 713 unsigned int data);714 715int snd_ca0106_i2c_write(struct snd_ca0106 *emu, u32 reg, u32 value);716 717int snd_ca0106_spi_write(struct snd_ca0106 * emu,718 unsigned int data);719 720#ifdef CONFIG_PM_SLEEP721void snd_ca0106_mixer_suspend(struct snd_ca0106 *chip);722void snd_ca0106_mixer_resume(struct snd_ca0106 *chip);723#else724#define snd_ca0106_mixer_suspend(chip) do { } while (0)725#define snd_ca0106_mixer_resume(chip) do { } while (0)726#endif727