1997 lines · c
1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * Driver for Cirrus Logic CS4281 based PCI soundcard4 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,5 */6 7#include <linux/io.h>8#include <linux/delay.h>9#include <linux/interrupt.h>10#include <linux/init.h>11#include <linux/pci.h>12#include <linux/slab.h>13#include <linux/gameport.h>14#include <linux/module.h>15#include <sound/core.h>16#include <sound/control.h>17#include <sound/pcm.h>18#include <sound/rawmidi.h>19#include <sound/ac97_codec.h>20#include <sound/tlv.h>21#include <sound/opl3.h>22#include <sound/initval.h>23 24 25MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");26MODULE_DESCRIPTION("Cirrus Logic CS4281");27MODULE_LICENSE("GPL");28 29static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */30static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */31static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */32static bool dual_codec[SNDRV_CARDS]; /* dual codec */33 34module_param_array(index, int, NULL, 0444);35MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");36module_param_array(id, charp, NULL, 0444);37MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");38module_param_array(enable, bool, NULL, 0444);39MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");40module_param_array(dual_codec, bool, NULL, 0444);41MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");42 43/*44 * Direct registers45 */46 47#define CS4281_BA0_SIZE 0x100048#define CS4281_BA1_SIZE 0x1000049 50/*51 * BA0 registers52 */53#define BA0_HISR 0x0000 /* Host Interrupt Status Register */54#define BA0_HISR_INTENA (1<<31) /* Internal Interrupt Enable Bit */55#define BA0_HISR_MIDI (1<<22) /* MIDI port interrupt */56#define BA0_HISR_FIFOI (1<<20) /* FIFO polled interrupt */57#define BA0_HISR_DMAI (1<<18) /* DMA interrupt (half or end) */58#define BA0_HISR_FIFO(c) (1<<(12+(c))) /* FIFO channel interrupt */59#define BA0_HISR_DMA(c) (1<<(8+(c))) /* DMA channel interrupt */60#define BA0_HISR_GPPI (1<<5) /* General Purpose Input (Primary chip) */61#define BA0_HISR_GPSI (1<<4) /* General Purpose Input (Secondary chip) */62#define BA0_HISR_GP3I (1<<3) /* GPIO3 pin Interrupt */63#define BA0_HISR_GP1I (1<<2) /* GPIO1 pin Interrupt */64#define BA0_HISR_VUPI (1<<1) /* VOLUP pin Interrupt */65#define BA0_HISR_VDNI (1<<0) /* VOLDN pin Interrupt */66 67#define BA0_HICR 0x0008 /* Host Interrupt Control Register */68#define BA0_HICR_CHGM (1<<1) /* INTENA Change Mask */69#define BA0_HICR_IEV (1<<0) /* INTENA Value */70#define BA0_HICR_EOI (3<<0) /* End of Interrupt command */71 72#define BA0_HIMR 0x000c /* Host Interrupt Mask Register */73 /* Use same contants as for BA0_HISR */74 75#define BA0_IIER 0x0010 /* ISA Interrupt Enable Register */76 77#define BA0_HDSR0 0x00f0 /* Host DMA Engine 0 Status Register */78#define BA0_HDSR1 0x00f4 /* Host DMA Engine 1 Status Register */79#define BA0_HDSR2 0x00f8 /* Host DMA Engine 2 Status Register */80#define BA0_HDSR3 0x00fc /* Host DMA Engine 3 Status Register */81 82#define BA0_HDSR_CH1P (1<<25) /* Channel 1 Pending */83#define BA0_HDSR_CH2P (1<<24) /* Channel 2 Pending */84#define BA0_HDSR_DHTC (1<<17) /* DMA Half Terminal Count */85#define BA0_HDSR_DTC (1<<16) /* DMA Terminal Count */86#define BA0_HDSR_DRUN (1<<15) /* DMA Running */87#define BA0_HDSR_RQ (1<<7) /* Pending Request */88 89#define BA0_DCA0 0x0110 /* Host DMA Engine 0 Current Address */90#define BA0_DCC0 0x0114 /* Host DMA Engine 0 Current Count */91#define BA0_DBA0 0x0118 /* Host DMA Engine 0 Base Address */92#define BA0_DBC0 0x011c /* Host DMA Engine 0 Base Count */93#define BA0_DCA1 0x0120 /* Host DMA Engine 1 Current Address */94#define BA0_DCC1 0x0124 /* Host DMA Engine 1 Current Count */95#define BA0_DBA1 0x0128 /* Host DMA Engine 1 Base Address */96#define BA0_DBC1 0x012c /* Host DMA Engine 1 Base Count */97#define BA0_DCA2 0x0130 /* Host DMA Engine 2 Current Address */98#define BA0_DCC2 0x0134 /* Host DMA Engine 2 Current Count */99#define BA0_DBA2 0x0138 /* Host DMA Engine 2 Base Address */100#define BA0_DBC2 0x013c /* Host DMA Engine 2 Base Count */101#define BA0_DCA3 0x0140 /* Host DMA Engine 3 Current Address */102#define BA0_DCC3 0x0144 /* Host DMA Engine 3 Current Count */103#define BA0_DBA3 0x0148 /* Host DMA Engine 3 Base Address */104#define BA0_DBC3 0x014c /* Host DMA Engine 3 Base Count */105#define BA0_DMR0 0x0150 /* Host DMA Engine 0 Mode */106#define BA0_DCR0 0x0154 /* Host DMA Engine 0 Command */107#define BA0_DMR1 0x0158 /* Host DMA Engine 1 Mode */108#define BA0_DCR1 0x015c /* Host DMA Engine 1 Command */109#define BA0_DMR2 0x0160 /* Host DMA Engine 2 Mode */110#define BA0_DCR2 0x0164 /* Host DMA Engine 2 Command */111#define BA0_DMR3 0x0168 /* Host DMA Engine 3 Mode */112#define BA0_DCR3 0x016c /* Host DMA Engine 3 Command */113 114#define BA0_DMR_DMA (1<<29) /* Enable DMA mode */115#define BA0_DMR_POLL (1<<28) /* Enable poll mode */116#define BA0_DMR_TBC (1<<25) /* Transfer By Channel */117#define BA0_DMR_CBC (1<<24) /* Count By Channel (0 = frame resolution) */118#define BA0_DMR_SWAPC (1<<22) /* Swap Left/Right Channels */119#define BA0_DMR_SIZE20 (1<<20) /* Sample is 20-bit */120#define BA0_DMR_USIGN (1<<19) /* Unsigned */121#define BA0_DMR_BEND (1<<18) /* Big Endian */122#define BA0_DMR_MONO (1<<17) /* Mono */123#define BA0_DMR_SIZE8 (1<<16) /* Sample is 8-bit */124#define BA0_DMR_TYPE_DEMAND (0<<6)125#define BA0_DMR_TYPE_SINGLE (1<<6)126#define BA0_DMR_TYPE_BLOCK (2<<6)127#define BA0_DMR_TYPE_CASCADE (3<<6) /* Not supported */128#define BA0_DMR_DEC (1<<5) /* Access Increment (0) or Decrement (1) */129#define BA0_DMR_AUTO (1<<4) /* Auto-Initialize */130#define BA0_DMR_TR_VERIFY (0<<2) /* Verify Transfer */131#define BA0_DMR_TR_WRITE (1<<2) /* Write Transfer */132#define BA0_DMR_TR_READ (2<<2) /* Read Transfer */133 134#define BA0_DCR_HTCIE (1<<17) /* Half Terminal Count Interrupt */135#define BA0_DCR_TCIE (1<<16) /* Terminal Count Interrupt */136#define BA0_DCR_MSK (1<<0) /* DMA Mask bit */137 138#define BA0_FCR0 0x0180 /* FIFO Control 0 */139#define BA0_FCR1 0x0184 /* FIFO Control 1 */140#define BA0_FCR2 0x0188 /* FIFO Control 2 */141#define BA0_FCR3 0x018c /* FIFO Control 3 */142 143#define BA0_FCR_FEN (1<<31) /* FIFO Enable bit */144#define BA0_FCR_DACZ (1<<30) /* DAC Zero */145#define BA0_FCR_PSH (1<<29) /* Previous Sample Hold */146#define BA0_FCR_RS(x) (((x)&0x1f)<<24) /* Right Slot Mapping */147#define BA0_FCR_LS(x) (((x)&0x1f)<<16) /* Left Slot Mapping */148#define BA0_FCR_SZ(x) (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */149#define BA0_FCR_OF(x) (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */150 151#define BA0_FPDR0 0x0190 /* FIFO Polled Data 0 */152#define BA0_FPDR1 0x0194 /* FIFO Polled Data 1 */153#define BA0_FPDR2 0x0198 /* FIFO Polled Data 2 */154#define BA0_FPDR3 0x019c /* FIFO Polled Data 3 */155 156#define BA0_FCHS 0x020c /* FIFO Channel Status */157#define BA0_FCHS_RCO(x) (1<<(7+(((x)&3)<<3))) /* Right Channel Out */158#define BA0_FCHS_LCO(x) (1<<(6+(((x)&3)<<3))) /* Left Channel Out */159#define BA0_FCHS_MRP(x) (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */160#define BA0_FCHS_FE(x) (1<<(4+(((x)&3)<<3))) /* FIFO Empty */161#define BA0_FCHS_FF(x) (1<<(3+(((x)&3)<<3))) /* FIFO Full */162#define BA0_FCHS_IOR(x) (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */163#define BA0_FCHS_RCI(x) (1<<(1+(((x)&3)<<3))) /* Right Channel In */164#define BA0_FCHS_LCI(x) (1<<(0+(((x)&3)<<3))) /* Left Channel In */165 166#define BA0_FSIC0 0x0210 /* FIFO Status and Interrupt Control 0 */167#define BA0_FSIC1 0x0214 /* FIFO Status and Interrupt Control 1 */168#define BA0_FSIC2 0x0218 /* FIFO Status and Interrupt Control 2 */169#define BA0_FSIC3 0x021c /* FIFO Status and Interrupt Control 3 */170 171#define BA0_FSIC_FIC(x) (((x)&0x7f)<<24) /* FIFO Interrupt Count */172#define BA0_FSIC_FORIE (1<<23) /* FIFO OverRun Interrupt Enable */173#define BA0_FSIC_FURIE (1<<22) /* FIFO UnderRun Interrupt Enable */174#define BA0_FSIC_FSCIE (1<<16) /* FIFO Sample Count Interrupt Enable */175#define BA0_FSIC_FSC(x) (((x)&0x7f)<<8) /* FIFO Sample Count */176#define BA0_FSIC_FOR (1<<7) /* FIFO OverRun */177#define BA0_FSIC_FUR (1<<6) /* FIFO UnderRun */178#define BA0_FSIC_FSCR (1<<0) /* FIFO Sample Count Reached */179 180#define BA0_PMCS 0x0344 /* Power Management Control/Status */181#define BA0_CWPR 0x03e0 /* Configuration Write Protect */182 183#define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */184#define BA0_EPPMC_FPDN (1<<14) /* Full Power DowN */185 186#define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */187 188#define BA0_SPMC 0x03ec /* Serial Port Power Management Control (& ASDIN2 enable) */189#define BA0_SPMC_GIPPEN (1<<15) /* GP INT Primary PME# Enable */190#define BA0_SPMC_GISPEN (1<<14) /* GP INT Secondary PME# Enable */191#define BA0_SPMC_EESPD (1<<9) /* EEPROM Serial Port Disable */192#define BA0_SPMC_ASDI2E (1<<8) /* ASDIN2 Enable */193#define BA0_SPMC_ASDO (1<<7) /* Asynchronous ASDOUT Assertion */194#define BA0_SPMC_WUP2 (1<<3) /* Wakeup for Secondary Input */195#define BA0_SPMC_WUP1 (1<<2) /* Wakeup for Primary Input */196#define BA0_SPMC_ASYNC (1<<1) /* Asynchronous ASYNC Assertion */197#define BA0_SPMC_RSTN (1<<0) /* Reset Not! */198 199#define BA0_CFLR 0x03f0 /* Configuration Load Register (EEPROM or BIOS) */200#define BA0_CFLR_DEFAULT 0x00000001 /* CFLR must be in AC97 link mode */201#define BA0_IISR 0x03f4 /* ISA Interrupt Select */202#define BA0_TMS 0x03f8 /* Test Register */203#define BA0_SSVID 0x03fc /* Subsystem ID register */204 205#define BA0_CLKCR1 0x0400 /* Clock Control Register 1 */206#define BA0_CLKCR1_CLKON (1<<25) /* Read Only */207#define BA0_CLKCR1_DLLRDY (1<<24) /* DLL Ready */208#define BA0_CLKCR1_DLLOS (1<<6) /* DLL Output Select */209#define BA0_CLKCR1_SWCE (1<<5) /* Clock Enable */210#define BA0_CLKCR1_DLLP (1<<4) /* DLL PowerUp */211#define BA0_CLKCR1_DLLSS (((x)&3)<<3) /* DLL Source Select */212 213#define BA0_FRR 0x0410 /* Feature Reporting Register */214#define BA0_SLT12O 0x041c /* Slot 12 GPIO Output Register for AC-Link */215 216#define BA0_SERMC 0x0420 /* Serial Port Master Control */217#define BA0_SERMC_FCRN (1<<27) /* Force Codec Ready Not */218#define BA0_SERMC_ODSEN2 (1<<25) /* On-Demand Support Enable ASDIN2 */219#define BA0_SERMC_ODSEN1 (1<<24) /* On-Demand Support Enable ASDIN1 */220#define BA0_SERMC_SXLB (1<<21) /* ASDIN2 to ASDOUT Loopback */221#define BA0_SERMC_SLB (1<<20) /* ASDOUT to ASDIN2 Loopback */222#define BA0_SERMC_LOVF (1<<19) /* Loopback Output Valid Frame bit */223#define BA0_SERMC_TCID(x) (((x)&3)<<16) /* Target Secondary Codec ID */224#define BA0_SERMC_PXLB (5<<1) /* Primary Port External Loopback */225#define BA0_SERMC_PLB (4<<1) /* Primary Port Internal Loopback */226#define BA0_SERMC_PTC (7<<1) /* Port Timing Configuration */227#define BA0_SERMC_PTC_AC97 (1<<1) /* AC97 mode */228#define BA0_SERMC_MSPE (1<<0) /* Master Serial Port Enable */229 230#define BA0_SERC1 0x0428 /* Serial Port Configuration 1 */231#define BA0_SERC1_SO1F(x) (((x)&7)>>1) /* Primary Output Port Format */232#define BA0_SERC1_AC97 (1<<1)233#define BA0_SERC1_SO1EN (1<<0) /* Primary Output Port Enable */234 235#define BA0_SERC2 0x042c /* Serial Port Configuration 2 */236#define BA0_SERC2_SI1F(x) (((x)&7)>>1) /* Primary Input Port Format */237#define BA0_SERC2_AC97 (1<<1)238#define BA0_SERC2_SI1EN (1<<0) /* Primary Input Port Enable */239 240#define BA0_SLT12M 0x045c /* Slot 12 Monitor Register for Primary AC-Link */241 242#define BA0_ACCTL 0x0460 /* AC'97 Control */243#define BA0_ACCTL_TC (1<<6) /* Target Codec */244#define BA0_ACCTL_CRW (1<<4) /* 0=Write, 1=Read Command */245#define BA0_ACCTL_DCV (1<<3) /* Dynamic Command Valid */246#define BA0_ACCTL_VFRM (1<<2) /* Valid Frame */247#define BA0_ACCTL_ESYN (1<<1) /* Enable Sync */248 249#define BA0_ACSTS 0x0464 /* AC'97 Status */250#define BA0_ACSTS_VSTS (1<<1) /* Valid Status */251#define BA0_ACSTS_CRDY (1<<0) /* Codec Ready */252 253#define BA0_ACOSV 0x0468 /* AC'97 Output Slot Valid */254#define BA0_ACOSV_SLV(x) (1<<((x)-3))255 256#define BA0_ACCAD 0x046c /* AC'97 Command Address */257#define BA0_ACCDA 0x0470 /* AC'97 Command Data */258 259#define BA0_ACISV 0x0474 /* AC'97 Input Slot Valid */260#define BA0_ACISV_SLV(x) (1<<((x)-3))261 262#define BA0_ACSAD 0x0478 /* AC'97 Status Address */263#define BA0_ACSDA 0x047c /* AC'97 Status Data */264#define BA0_JSPT 0x0480 /* Joystick poll/trigger */265#define BA0_JSCTL 0x0484 /* Joystick control */266#define BA0_JSC1 0x0488 /* Joystick control */267#define BA0_JSC2 0x048c /* Joystick control */268#define BA0_JSIO 0x04a0269 270#define BA0_MIDCR 0x0490 /* MIDI Control */271#define BA0_MIDCR_MRST (1<<5) /* Reset MIDI Interface */272#define BA0_MIDCR_MLB (1<<4) /* MIDI Loop Back Enable */273#define BA0_MIDCR_TIE (1<<3) /* MIDI Transmuit Interrupt Enable */274#define BA0_MIDCR_RIE (1<<2) /* MIDI Receive Interrupt Enable */275#define BA0_MIDCR_RXE (1<<1) /* MIDI Receive Enable */276#define BA0_MIDCR_TXE (1<<0) /* MIDI Transmit Enable */277 278#define BA0_MIDCMD 0x0494 /* MIDI Command (wo) */279 280#define BA0_MIDSR 0x0494 /* MIDI Status (ro) */281#define BA0_MIDSR_RDA (1<<15) /* Sticky bit (RBE 1->0) */282#define BA0_MIDSR_TBE (1<<14) /* Sticky bit (TBF 0->1) */283#define BA0_MIDSR_RBE (1<<7) /* Receive Buffer Empty */284#define BA0_MIDSR_TBF (1<<6) /* Transmit Buffer Full */285 286#define BA0_MIDWP 0x0498 /* MIDI Write */287#define BA0_MIDRP 0x049c /* MIDI Read (ro) */288 289#define BA0_AODSD1 0x04a8 /* AC'97 On-Demand Slot Disable for primary link (ro) */290#define BA0_AODSD1_NDS(x) (1<<((x)-3))291 292#define BA0_AODSD2 0x04ac /* AC'97 On-Demand Slot Disable for secondary link (ro) */293#define BA0_AODSD2_NDS(x) (1<<((x)-3))294 295#define BA0_CFGI 0x04b0 /* Configure Interface (EEPROM interface) */296#define BA0_SLT12M2 0x04dc /* Slot 12 Monitor Register 2 for secondary AC-link */297#define BA0_ACSTS2 0x04e4 /* AC'97 Status Register 2 */298#define BA0_ACISV2 0x04f4 /* AC'97 Input Slot Valid Register 2 */299#define BA0_ACSAD2 0x04f8 /* AC'97 Status Address Register 2 */300#define BA0_ACSDA2 0x04fc /* AC'97 Status Data Register 2 */301#define BA0_FMSR 0x0730 /* FM Synthesis Status (ro) */302#define BA0_B0AP 0x0730 /* FM Bank 0 Address Port (wo) */303#define BA0_FMDP 0x0734 /* FM Data Port */304#define BA0_B1AP 0x0738 /* FM Bank 1 Address Port */305#define BA0_B1DP 0x073c /* FM Bank 1 Data Port */306 307#define BA0_SSPM 0x0740 /* Sound System Power Management */308#define BA0_SSPM_MIXEN (1<<6) /* Playback SRC + FM/Wavetable MIX */309#define BA0_SSPM_CSRCEN (1<<5) /* Capture Sample Rate Converter Enable */310#define BA0_SSPM_PSRCEN (1<<4) /* Playback Sample Rate Converter Enable */311#define BA0_SSPM_JSEN (1<<3) /* Joystick Enable */312#define BA0_SSPM_ACLEN (1<<2) /* Serial Port Engine and AC-Link Enable */313#define BA0_SSPM_FMEN (1<<1) /* FM Synthesis Block Enable */314 315#define BA0_DACSR 0x0744 /* DAC Sample Rate - Playback SRC */316#define BA0_ADCSR 0x0748 /* ADC Sample Rate - Capture SRC */317 318#define BA0_SSCR 0x074c /* Sound System Control Register */319#define BA0_SSCR_HVS1 (1<<23) /* Hardwave Volume Step (0=1,1=2) */320#define BA0_SSCR_MVCS (1<<19) /* Master Volume Codec Select */321#define BA0_SSCR_MVLD (1<<18) /* Master Volume Line Out Disable */322#define BA0_SSCR_MVAD (1<<17) /* Master Volume Alternate Out Disable */323#define BA0_SSCR_MVMD (1<<16) /* Master Volume Mono Out Disable */324#define BA0_SSCR_XLPSRC (1<<8) /* External SRC Loopback Mode */325#define BA0_SSCR_LPSRC (1<<7) /* SRC Loopback Mode */326#define BA0_SSCR_CDTX (1<<5) /* CD Transfer Data */327#define BA0_SSCR_HVC (1<<3) /* Harware Volume Control Enable */328 329#define BA0_FMLVC 0x0754 /* FM Synthesis Left Volume Control */330#define BA0_FMRVC 0x0758 /* FM Synthesis Right Volume Control */331#define BA0_SRCSA 0x075c /* SRC Slot Assignments */332#define BA0_PPLVC 0x0760 /* PCM Playback Left Volume Control */333#define BA0_PPRVC 0x0764 /* PCM Playback Right Volume Control */334#define BA0_PASR 0x0768 /* playback sample rate */335#define BA0_CASR 0x076C /* capture sample rate */336 337/* Source Slot Numbers - Playback */338#define SRCSLOT_LEFT_PCM_PLAYBACK 0339#define SRCSLOT_RIGHT_PCM_PLAYBACK 1340#define SRCSLOT_PHONE_LINE_1_DAC 2341#define SRCSLOT_CENTER_PCM_PLAYBACK 3342#define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK 4343#define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK 5344#define SRCSLOT_LFE_PCM_PLAYBACK 6345#define SRCSLOT_PHONE_LINE_2_DAC 7346#define SRCSLOT_HEADSET_DAC 8347#define SRCSLOT_LEFT_WT 29 /* invalid for BA0_SRCSA */348#define SRCSLOT_RIGHT_WT 30 /* invalid for BA0_SRCSA */349 350/* Source Slot Numbers - Capture */351#define SRCSLOT_LEFT_PCM_RECORD 10352#define SRCSLOT_RIGHT_PCM_RECORD 11353#define SRCSLOT_PHONE_LINE_1_ADC 12354#define SRCSLOT_MIC_ADC 13355#define SRCSLOT_PHONE_LINE_2_ADC 17356#define SRCSLOT_HEADSET_ADC 18357#define SRCSLOT_SECONDARY_LEFT_PCM_RECORD 20358#define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD 21359#define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC 22360#define SRCSLOT_SECONDARY_MIC_ADC 23361#define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC 27362#define SRCSLOT_SECONDARY_HEADSET_ADC 28363 364/* Source Slot Numbers - Others */365#define SRCSLOT_POWER_DOWN 31366 367/* MIDI modes */368#define CS4281_MODE_OUTPUT (1<<0)369#define CS4281_MODE_INPUT (1<<1)370 371/* joystick bits */372/* Bits for JSPT */373#define JSPT_CAX 0x00000001374#define JSPT_CAY 0x00000002375#define JSPT_CBX 0x00000004376#define JSPT_CBY 0x00000008377#define JSPT_BA1 0x00000010378#define JSPT_BA2 0x00000020379#define JSPT_BB1 0x00000040380#define JSPT_BB2 0x00000080381 382/* Bits for JSCTL */383#define JSCTL_SP_MASK 0x00000003384#define JSCTL_SP_SLOW 0x00000000385#define JSCTL_SP_MEDIUM_SLOW 0x00000001386#define JSCTL_SP_MEDIUM_FAST 0x00000002387#define JSCTL_SP_FAST 0x00000003388#define JSCTL_ARE 0x00000004389 390/* Data register pairs masks */391#define JSC1_Y1V_MASK 0x0000FFFF392#define JSC1_X1V_MASK 0xFFFF0000393#define JSC1_Y1V_SHIFT 0394#define JSC1_X1V_SHIFT 16395#define JSC2_Y2V_MASK 0x0000FFFF396#define JSC2_X2V_MASK 0xFFFF0000397#define JSC2_Y2V_SHIFT 0398#define JSC2_X2V_SHIFT 16399 400/* JS GPIO */401#define JSIO_DAX 0x00000001402#define JSIO_DAY 0x00000002403#define JSIO_DBX 0x00000004404#define JSIO_DBY 0x00000008405#define JSIO_AXOE 0x00000010406#define JSIO_AYOE 0x00000020407#define JSIO_BXOE 0x00000040408#define JSIO_BYOE 0x00000080409 410/*411 *412 */413 414struct cs4281_dma {415 struct snd_pcm_substream *substream;416 unsigned int regDBA; /* offset to DBA register */417 unsigned int regDCA; /* offset to DCA register */418 unsigned int regDBC; /* offset to DBC register */419 unsigned int regDCC; /* offset to DCC register */420 unsigned int regDMR; /* offset to DMR register */421 unsigned int regDCR; /* offset to DCR register */422 unsigned int regHDSR; /* offset to HDSR register */423 unsigned int regFCR; /* offset to FCR register */424 unsigned int regFSIC; /* offset to FSIC register */425 unsigned int valDMR; /* DMA mode */426 unsigned int valDCR; /* DMA command */427 unsigned int valFCR; /* FIFO control */428 unsigned int fifo_offset; /* FIFO offset within BA1 */429 unsigned char left_slot; /* FIFO left slot */430 unsigned char right_slot; /* FIFO right slot */431 int frag; /* period number */432};433 434#define SUSPEND_REGISTERS 20435 436struct cs4281 {437 int irq;438 439 void __iomem *ba0; /* virtual (accessible) address */440 void __iomem *ba1; /* virtual (accessible) address */441 unsigned long ba0_addr;442 unsigned long ba1_addr;443 444 int dual_codec;445 446 struct snd_ac97_bus *ac97_bus;447 struct snd_ac97 *ac97;448 struct snd_ac97 *ac97_secondary;449 450 struct pci_dev *pci;451 struct snd_card *card;452 struct snd_pcm *pcm;453 struct snd_rawmidi *rmidi;454 struct snd_rawmidi_substream *midi_input;455 struct snd_rawmidi_substream *midi_output;456 457 struct cs4281_dma dma[4];458 459 unsigned char src_left_play_slot;460 unsigned char src_right_play_slot;461 unsigned char src_left_rec_slot;462 unsigned char src_right_rec_slot;463 464 unsigned int spurious_dhtc_irq;465 unsigned int spurious_dtc_irq;466 467 spinlock_t reg_lock;468 unsigned int midcr;469 unsigned int uartm;470 471 struct gameport *gameport;472 473 u32 suspend_regs[SUSPEND_REGISTERS];474};475 476static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id);477 478static const struct pci_device_id snd_cs4281_ids[] = {479 { PCI_VDEVICE(CIRRUS, 0x6005), 0, }, /* CS4281 */480 { 0, }481};482 483MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);484 485/*486 * constants487 */488 489#define CS4281_FIFO_SIZE 32490 491/*492 * common I/O routines493 */494 495static inline void snd_cs4281_pokeBA0(struct cs4281 *chip, unsigned long offset,496 unsigned int val)497{498 writel(val, chip->ba0 + offset);499}500 501static inline unsigned int snd_cs4281_peekBA0(struct cs4281 *chip, unsigned long offset)502{503 return readl(chip->ba0 + offset);504}505 506static void snd_cs4281_ac97_write(struct snd_ac97 *ac97,507 unsigned short reg, unsigned short val)508{509 /*510 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address511 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97512 * 3. Write ACCTL = Control Register = 460h for initiating the write513 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h514 * 5. if DCV not cleared, break and return error515 */516 struct cs4281 *chip = ac97->private_data;517 int count;518 519 /*520 * Setup the AC97 control registers on the CS461x to send the521 * appropriate command to the AC97 to perform the read.522 * ACCAD = Command Address Register = 46Ch523 * ACCDA = Command Data Register = 470h524 * ACCTL = Control Register = 460h525 * set DCV - will clear when process completed526 * reset CRW - Write command527 * set VFRM - valid frame enabled528 * set ESYN - ASYNC generation enabled529 * set RSTN - ARST# inactive, AC97 codec not reset530 */531 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);532 snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);533 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |534 BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));535 for (count = 0; count < 2000; count++) {536 /*537 * First, we want to wait for a short time.538 */539 udelay(10);540 /*541 * Now, check to see if the write has completed.542 * ACCTL = 460h, DCV should be reset by now and 460h = 07h543 */544 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {545 return;546 }547 }548 dev_err(chip->card->dev,549 "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);550}551 552static unsigned short snd_cs4281_ac97_read(struct snd_ac97 *ac97,553 unsigned short reg)554{555 struct cs4281 *chip = ac97->private_data;556 int count;557 unsigned short result;558 // FIXME: volatile is necessary in the following due to a bug of559 // some gcc versions560 volatile int ac97_num = ((volatile struct snd_ac97 *)ac97)->num;561 562 /*563 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address564 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 565 * 3. Write ACCTL = Control Register = 460h for initiating the write566 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h567 * 5. if DCV not cleared, break and return error568 * 6. Read ACSTS = Status Register = 464h, check VSTS bit569 */570 571 snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);572 573 /*574 * Setup the AC97 control registers on the CS461x to send the575 * appropriate command to the AC97 to perform the read.576 * ACCAD = Command Address Register = 46Ch577 * ACCDA = Command Data Register = 470h578 * ACCTL = Control Register = 460h579 * set DCV - will clear when process completed580 * set CRW - Read command581 * set VFRM - valid frame enabled582 * set ESYN - ASYNC generation enabled583 * set RSTN - ARST# inactive, AC97 codec not reset584 */585 586 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);587 snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);588 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |589 BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |590 (ac97_num ? BA0_ACCTL_TC : 0));591 592 593 /*594 * Wait for the read to occur.595 */596 for (count = 0; count < 500; count++) {597 /*598 * First, we want to wait for a short time.599 */600 udelay(10);601 /*602 * Now, check to see if the read has completed.603 * ACCTL = 460h, DCV should be reset by now and 460h = 17h604 */605 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))606 goto __ok1;607 }608 609 dev_err(chip->card->dev,610 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);611 result = 0xffff;612 goto __end;613 614 __ok1:615 /*616 * Wait for the valid status bit to go active.617 */618 for (count = 0; count < 100; count++) {619 /*620 * Read the AC97 status register.621 * ACSTS = Status Register = 464h622 * VSTS - Valid Status623 */624 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)625 goto __ok2;626 udelay(10);627 }628 629 dev_err(chip->card->dev,630 "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);631 result = 0xffff;632 goto __end;633 634 __ok2:635 /*636 * Read the data returned from the AC97 register.637 * ACSDA = Status Data Register = 474h638 */639 result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);640 641 __end:642 return result;643}644 645/*646 * PCM part647 */648 649static int snd_cs4281_trigger(struct snd_pcm_substream *substream, int cmd)650{651 struct cs4281_dma *dma = substream->runtime->private_data;652 struct cs4281 *chip = snd_pcm_substream_chip(substream);653 654 spin_lock(&chip->reg_lock);655 switch (cmd) {656 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:657 dma->valDCR |= BA0_DCR_MSK;658 dma->valFCR |= BA0_FCR_FEN;659 break;660 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:661 dma->valDCR &= ~BA0_DCR_MSK;662 dma->valFCR &= ~BA0_FCR_FEN;663 break;664 case SNDRV_PCM_TRIGGER_START:665 case SNDRV_PCM_TRIGGER_RESUME:666 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);667 dma->valDMR |= BA0_DMR_DMA;668 dma->valDCR &= ~BA0_DCR_MSK;669 dma->valFCR |= BA0_FCR_FEN;670 break;671 case SNDRV_PCM_TRIGGER_STOP:672 case SNDRV_PCM_TRIGGER_SUSPEND:673 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);674 dma->valDCR |= BA0_DCR_MSK;675 dma->valFCR &= ~BA0_FCR_FEN;676 /* Leave wave playback FIFO enabled for FM */677 if (dma->regFCR != BA0_FCR0)678 dma->valFCR &= ~BA0_FCR_FEN;679 break;680 default:681 spin_unlock(&chip->reg_lock);682 return -EINVAL;683 }684 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);685 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);686 snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);687 spin_unlock(&chip->reg_lock);688 return 0;689}690 691static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)692{693 unsigned int val;694 695 if (real_rate)696 *real_rate = rate;697 /* special "hardcoded" rates */698 switch (rate) {699 case 8000: return 5;700 case 11025: return 4;701 case 16000: return 3;702 case 22050: return 2;703 case 44100: return 1;704 case 48000: return 0;705 default:706 break;707 }708 val = 1536000 / rate;709 if (real_rate)710 *real_rate = 1536000 / val;711 return val;712}713 714static void snd_cs4281_mode(struct cs4281 *chip, struct cs4281_dma *dma,715 struct snd_pcm_runtime *runtime,716 int capture, int src)717{718 int rec_mono;719 720 dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |721 (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);722 if (runtime->channels == 1)723 dma->valDMR |= BA0_DMR_MONO;724 if (snd_pcm_format_unsigned(runtime->format) > 0)725 dma->valDMR |= BA0_DMR_USIGN;726 if (snd_pcm_format_big_endian(runtime->format) > 0)727 dma->valDMR |= BA0_DMR_BEND;728 switch (snd_pcm_format_width(runtime->format)) {729 case 8: dma->valDMR |= BA0_DMR_SIZE8;730 if (runtime->channels == 1)731 dma->valDMR |= BA0_DMR_SWAPC;732 break;733 case 32: dma->valDMR |= BA0_DMR_SIZE20; break;734 }735 dma->frag = 0; /* for workaround */736 dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;737 if (runtime->buffer_size != runtime->period_size)738 dma->valDCR |= BA0_DCR_HTCIE;739 /* Initialize DMA */740 snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);741 snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);742 rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;743 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |744 (chip->src_right_play_slot << 8) |745 (chip->src_left_rec_slot << 16) |746 ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));747 if (!src)748 goto __skip_src;749 if (!capture) {750 if (dma->left_slot == chip->src_left_play_slot) {751 unsigned int val = snd_cs4281_rate(runtime->rate, NULL);752 snd_BUG_ON(dma->right_slot != chip->src_right_play_slot);753 snd_cs4281_pokeBA0(chip, BA0_DACSR, val);754 }755 } else {756 if (dma->left_slot == chip->src_left_rec_slot) {757 unsigned int val = snd_cs4281_rate(runtime->rate, NULL);758 snd_BUG_ON(dma->right_slot != chip->src_right_rec_slot);759 snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);760 }761 }762 __skip_src:763 /* Deactivate wave playback FIFO before changing slot assignments */764 if (dma->regFCR == BA0_FCR0)765 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);766 /* Initialize FIFO */767 dma->valFCR = BA0_FCR_LS(dma->left_slot) |768 BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |769 BA0_FCR_SZ(CS4281_FIFO_SIZE) |770 BA0_FCR_OF(dma->fifo_offset);771 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));772 /* Activate FIFO again for FM playback */773 if (dma->regFCR == BA0_FCR0)774 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);775 /* Clear FIFO Status and Interrupt Control Register */776 snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);777}778 779static int snd_cs4281_playback_prepare(struct snd_pcm_substream *substream)780{781 struct snd_pcm_runtime *runtime = substream->runtime;782 struct cs4281_dma *dma = runtime->private_data;783 struct cs4281 *chip = snd_pcm_substream_chip(substream);784 785 spin_lock_irq(&chip->reg_lock);786 snd_cs4281_mode(chip, dma, runtime, 0, 1);787 spin_unlock_irq(&chip->reg_lock);788 return 0;789}790 791static int snd_cs4281_capture_prepare(struct snd_pcm_substream *substream)792{793 struct snd_pcm_runtime *runtime = substream->runtime;794 struct cs4281_dma *dma = runtime->private_data;795 struct cs4281 *chip = snd_pcm_substream_chip(substream);796 797 spin_lock_irq(&chip->reg_lock);798 snd_cs4281_mode(chip, dma, runtime, 1, 1);799 spin_unlock_irq(&chip->reg_lock);800 return 0;801}802 803static snd_pcm_uframes_t snd_cs4281_pointer(struct snd_pcm_substream *substream)804{805 struct snd_pcm_runtime *runtime = substream->runtime;806 struct cs4281_dma *dma = runtime->private_data;807 struct cs4281 *chip = snd_pcm_substream_chip(substream);808 809 /*810 dev_dbg(chip->card->dev,811 "DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n",812 snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size,813 jiffies);814 */815 return runtime->buffer_size -816 snd_cs4281_peekBA0(chip, dma->regDCC) - 1;817}818 819static const struct snd_pcm_hardware snd_cs4281_playback =820{821 .info = SNDRV_PCM_INFO_MMAP |822 SNDRV_PCM_INFO_INTERLEAVED |823 SNDRV_PCM_INFO_MMAP_VALID |824 SNDRV_PCM_INFO_PAUSE |825 SNDRV_PCM_INFO_RESUME,826 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |827 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |828 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |829 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |830 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,831 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,832 .rate_min = 4000,833 .rate_max = 48000,834 .channels_min = 1,835 .channels_max = 2,836 .buffer_bytes_max = (512*1024),837 .period_bytes_min = 64,838 .period_bytes_max = (512*1024),839 .periods_min = 1,840 .periods_max = 2,841 .fifo_size = CS4281_FIFO_SIZE,842};843 844static const struct snd_pcm_hardware snd_cs4281_capture =845{846 .info = SNDRV_PCM_INFO_MMAP |847 SNDRV_PCM_INFO_INTERLEAVED |848 SNDRV_PCM_INFO_MMAP_VALID |849 SNDRV_PCM_INFO_PAUSE |850 SNDRV_PCM_INFO_RESUME,851 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |852 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |853 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |854 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |855 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,856 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,857 .rate_min = 4000,858 .rate_max = 48000,859 .channels_min = 1,860 .channels_max = 2,861 .buffer_bytes_max = (512*1024),862 .period_bytes_min = 64,863 .period_bytes_max = (512*1024),864 .periods_min = 1,865 .periods_max = 2,866 .fifo_size = CS4281_FIFO_SIZE,867};868 869static int snd_cs4281_playback_open(struct snd_pcm_substream *substream)870{871 struct cs4281 *chip = snd_pcm_substream_chip(substream);872 struct snd_pcm_runtime *runtime = substream->runtime;873 struct cs4281_dma *dma;874 875 dma = &chip->dma[0];876 dma->substream = substream;877 dma->left_slot = 0;878 dma->right_slot = 1;879 runtime->private_data = dma;880 runtime->hw = snd_cs4281_playback;881 /* should be detected from the AC'97 layer, but it seems882 that although CS4297A rev B reports 18-bit ADC resolution,883 samples are 20-bit */884 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);885 return 0;886}887 888static int snd_cs4281_capture_open(struct snd_pcm_substream *substream)889{890 struct cs4281 *chip = snd_pcm_substream_chip(substream);891 struct snd_pcm_runtime *runtime = substream->runtime;892 struct cs4281_dma *dma;893 894 dma = &chip->dma[1];895 dma->substream = substream;896 dma->left_slot = 10;897 dma->right_slot = 11;898 runtime->private_data = dma;899 runtime->hw = snd_cs4281_capture;900 /* should be detected from the AC'97 layer, but it seems901 that although CS4297A rev B reports 18-bit ADC resolution,902 samples are 20-bit */903 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);904 return 0;905}906 907static int snd_cs4281_playback_close(struct snd_pcm_substream *substream)908{909 struct cs4281_dma *dma = substream->runtime->private_data;910 911 dma->substream = NULL;912 return 0;913}914 915static int snd_cs4281_capture_close(struct snd_pcm_substream *substream)916{917 struct cs4281_dma *dma = substream->runtime->private_data;918 919 dma->substream = NULL;920 return 0;921}922 923static const struct snd_pcm_ops snd_cs4281_playback_ops = {924 .open = snd_cs4281_playback_open,925 .close = snd_cs4281_playback_close,926 .prepare = snd_cs4281_playback_prepare,927 .trigger = snd_cs4281_trigger,928 .pointer = snd_cs4281_pointer,929};930 931static const struct snd_pcm_ops snd_cs4281_capture_ops = {932 .open = snd_cs4281_capture_open,933 .close = snd_cs4281_capture_close,934 .prepare = snd_cs4281_capture_prepare,935 .trigger = snd_cs4281_trigger,936 .pointer = snd_cs4281_pointer,937};938 939static int snd_cs4281_pcm(struct cs4281 *chip, int device)940{941 struct snd_pcm *pcm;942 int err;943 944 err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);945 if (err < 0)946 return err;947 948 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);949 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);950 951 pcm->private_data = chip;952 pcm->info_flags = 0;953 strcpy(pcm->name, "CS4281");954 chip->pcm = pcm;955 956 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev,957 64*1024, 512*1024);958 959 return 0;960}961 962/*963 * Mixer section964 */965 966#define CS_VOL_MASK 0x1f967 968static int snd_cs4281_info_volume(struct snd_kcontrol *kcontrol,969 struct snd_ctl_elem_info *uinfo)970{971 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;972 uinfo->count = 2;973 uinfo->value.integer.min = 0;974 uinfo->value.integer.max = CS_VOL_MASK;975 return 0;976}977 978static int snd_cs4281_get_volume(struct snd_kcontrol *kcontrol,979 struct snd_ctl_elem_value *ucontrol)980{981 struct cs4281 *chip = snd_kcontrol_chip(kcontrol);982 int regL = (kcontrol->private_value >> 16) & 0xffff;983 int regR = kcontrol->private_value & 0xffff;984 int volL, volR;985 986 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);987 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);988 989 ucontrol->value.integer.value[0] = volL;990 ucontrol->value.integer.value[1] = volR;991 return 0;992}993 994static int snd_cs4281_put_volume(struct snd_kcontrol *kcontrol,995 struct snd_ctl_elem_value *ucontrol)996{997 struct cs4281 *chip = snd_kcontrol_chip(kcontrol);998 int change = 0;999 int regL = (kcontrol->private_value >> 16) & 0xffff;1000 int regR = kcontrol->private_value & 0xffff;1001 int volL, volR;1002 1003 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);1004 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);1005 1006 if (ucontrol->value.integer.value[0] != volL) {1007 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);1008 snd_cs4281_pokeBA0(chip, regL, volL);1009 change = 1;1010 }1011 if (ucontrol->value.integer.value[1] != volR) {1012 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);1013 snd_cs4281_pokeBA0(chip, regR, volR);1014 change = 1;1015 }1016 return change;1017}1018 1019static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -4650, 150, 0);1020 1021static const struct snd_kcontrol_new snd_cs4281_fm_vol =1022{1023 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,1024 .name = "Synth Playback Volume",1025 .info = snd_cs4281_info_volume, 1026 .get = snd_cs4281_get_volume,1027 .put = snd_cs4281_put_volume, 1028 .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC),1029 .tlv = { .p = db_scale_dsp },1030};1031 1032static const struct snd_kcontrol_new snd_cs4281_pcm_vol =1033{1034 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,1035 .name = "PCM Stream Playback Volume",1036 .info = snd_cs4281_info_volume, 1037 .get = snd_cs4281_get_volume,1038 .put = snd_cs4281_put_volume, 1039 .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC),1040 .tlv = { .p = db_scale_dsp },1041};1042 1043static void snd_cs4281_mixer_free_ac97_bus(struct snd_ac97_bus *bus)1044{1045 struct cs4281 *chip = bus->private_data;1046 chip->ac97_bus = NULL;1047}1048 1049static void snd_cs4281_mixer_free_ac97(struct snd_ac97 *ac97)1050{1051 struct cs4281 *chip = ac97->private_data;1052 if (ac97->num)1053 chip->ac97_secondary = NULL;1054 else1055 chip->ac97 = NULL;1056}1057 1058static int snd_cs4281_mixer(struct cs4281 *chip)1059{1060 struct snd_card *card = chip->card;1061 struct snd_ac97_template ac97;1062 int err;1063 static const struct snd_ac97_bus_ops ops = {1064 .write = snd_cs4281_ac97_write,1065 .read = snd_cs4281_ac97_read,1066 };1067 1068 err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus);1069 if (err < 0)1070 return err;1071 chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;1072 1073 memset(&ac97, 0, sizeof(ac97));1074 ac97.private_data = chip;1075 ac97.private_free = snd_cs4281_mixer_free_ac97;1076 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97);1077 if (err < 0)1078 return err;1079 if (chip->dual_codec) {1080 ac97.num = 1;1081 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary);1082 if (err < 0)1083 return err;1084 }1085 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip));1086 if (err < 0)1087 return err;1088 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip));1089 if (err < 0)1090 return err;1091 return 0;1092}1093 1094 1095/*1096 * proc interface1097 */1098 1099static void snd_cs4281_proc_read(struct snd_info_entry *entry, 1100 struct snd_info_buffer *buffer)1101{1102 struct cs4281 *chip = entry->private_data;1103 1104 snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");1105 snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq);1106 snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq);1107}1108 1109static ssize_t snd_cs4281_BA0_read(struct snd_info_entry *entry,1110 void *file_private_data,1111 struct file *file, char __user *buf,1112 size_t count, loff_t pos)1113{1114 struct cs4281 *chip = entry->private_data;1115 1116 if (copy_to_user_fromio(buf, chip->ba0 + pos, count))1117 return -EFAULT;1118 return count;1119}1120 1121static ssize_t snd_cs4281_BA1_read(struct snd_info_entry *entry,1122 void *file_private_data,1123 struct file *file, char __user *buf,1124 size_t count, loff_t pos)1125{1126 struct cs4281 *chip = entry->private_data;1127 1128 if (copy_to_user_fromio(buf, chip->ba1 + pos, count))1129 return -EFAULT;1130 return count;1131}1132 1133static const struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {1134 .read = snd_cs4281_BA0_read,1135};1136 1137static const struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {1138 .read = snd_cs4281_BA1_read,1139};1140 1141static void snd_cs4281_proc_init(struct cs4281 *chip)1142{1143 struct snd_info_entry *entry;1144 1145 snd_card_ro_proc_new(chip->card, "cs4281", chip, snd_cs4281_proc_read);1146 if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {1147 entry->content = SNDRV_INFO_CONTENT_DATA;1148 entry->private_data = chip;1149 entry->c.ops = &snd_cs4281_proc_ops_BA0;1150 entry->size = CS4281_BA0_SIZE;1151 }1152 if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {1153 entry->content = SNDRV_INFO_CONTENT_DATA;1154 entry->private_data = chip;1155 entry->c.ops = &snd_cs4281_proc_ops_BA1;1156 entry->size = CS4281_BA1_SIZE;1157 }1158}1159 1160/*1161 * joystick support1162 */1163 1164#if IS_REACHABLE(CONFIG_GAMEPORT)1165 1166static void snd_cs4281_gameport_trigger(struct gameport *gameport)1167{1168 struct cs4281 *chip = gameport_get_port_data(gameport);1169 1170 if (snd_BUG_ON(!chip))1171 return;1172 snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);1173}1174 1175static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)1176{1177 struct cs4281 *chip = gameport_get_port_data(gameport);1178 1179 if (snd_BUG_ON(!chip))1180 return 0;1181 return snd_cs4281_peekBA0(chip, BA0_JSPT);1182}1183 1184#ifdef COOKED_MODE1185static int snd_cs4281_gameport_cooked_read(struct gameport *gameport,1186 int *axes, int *buttons)1187{1188 struct cs4281 *chip = gameport_get_port_data(gameport);1189 unsigned js1, js2, jst;1190 1191 if (snd_BUG_ON(!chip))1192 return 0;1193 1194 js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);1195 js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);1196 jst = snd_cs4281_peekBA0(chip, BA0_JSPT);1197 1198 *buttons = (~jst >> 4) & 0x0F; 1199 1200 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;1201 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;1202 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;1203 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;1204 1205 for (jst = 0; jst < 4; ++jst)1206 if (axes[jst] == 0xFFFF) axes[jst] = -1;1207 return 0;1208}1209#else1210#define snd_cs4281_gameport_cooked_read NULL1211#endif1212 1213static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)1214{1215 switch (mode) {1216#ifdef COOKED_MODE1217 case GAMEPORT_MODE_COOKED:1218 return 0;1219#endif1220 case GAMEPORT_MODE_RAW:1221 return 0;1222 default:1223 return -1;1224 }1225 return 0;1226}1227 1228static int snd_cs4281_create_gameport(struct cs4281 *chip)1229{1230 struct gameport *gp;1231 1232 chip->gameport = gp = gameport_allocate_port();1233 if (!gp) {1234 dev_err(chip->card->dev,1235 "cannot allocate memory for gameport\n");1236 return -ENOMEM;1237 }1238 1239 gameport_set_name(gp, "CS4281 Gameport");1240 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));1241 gameport_set_dev_parent(gp, &chip->pci->dev);1242 gp->open = snd_cs4281_gameport_open;1243 gp->read = snd_cs4281_gameport_read;1244 gp->trigger = snd_cs4281_gameport_trigger;1245 gp->cooked_read = snd_cs4281_gameport_cooked_read;1246 gameport_set_port_data(gp, chip);1247 1248 snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?1249 snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);1250 1251 gameport_register_port(gp);1252 1253 return 0;1254}1255 1256static void snd_cs4281_free_gameport(struct cs4281 *chip)1257{1258 if (chip->gameport) {1259 gameport_unregister_port(chip->gameport);1260 chip->gameport = NULL;1261 }1262}1263#else1264static inline int snd_cs4281_create_gameport(struct cs4281 *chip) { return -ENOSYS; }1265static inline void snd_cs4281_free_gameport(struct cs4281 *chip) { }1266#endif /* IS_REACHABLE(CONFIG_GAMEPORT) */1267 1268static void snd_cs4281_free(struct snd_card *card)1269{1270 struct cs4281 *chip = card->private_data;1271 1272 snd_cs4281_free_gameport(chip);1273 1274 /* Mask interrupts */1275 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);1276 /* Stop the DLL Clock logic. */1277 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);1278 /* Sound System Power Management - Turn Everything OFF */1279 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);1280}1281 1282static int snd_cs4281_chip_init(struct cs4281 *chip); /* defined below */1283 1284static int snd_cs4281_create(struct snd_card *card,1285 struct pci_dev *pci,1286 int dual_codec)1287{1288 struct cs4281 *chip = card->private_data;1289 int err;1290 1291 err = pcim_enable_device(pci);1292 if (err < 0)1293 return err;1294 spin_lock_init(&chip->reg_lock);1295 chip->card = card;1296 chip->pci = pci;1297 chip->irq = -1;1298 pci_set_master(pci);1299 if (dual_codec < 0 || dual_codec > 3) {1300 dev_err(card->dev, "invalid dual_codec option %d\n", dual_codec);1301 dual_codec = 0;1302 }1303 chip->dual_codec = dual_codec;1304 1305 err = pcim_iomap_regions(pci, 0x03, "CS4281"); /* 2 BARs */1306 if (err < 0)1307 return err;1308 chip->ba0_addr = pci_resource_start(pci, 0);1309 chip->ba1_addr = pci_resource_start(pci, 1);1310 1311 chip->ba0 = pcim_iomap_table(pci)[0];1312 chip->ba1 = pcim_iomap_table(pci)[1];1313 1314 if (devm_request_irq(&pci->dev, pci->irq, snd_cs4281_interrupt,1315 IRQF_SHARED, KBUILD_MODNAME, chip)) {1316 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);1317 return -ENOMEM;1318 }1319 chip->irq = pci->irq;1320 card->sync_irq = chip->irq;1321 card->private_free = snd_cs4281_free;1322 1323 err = snd_cs4281_chip_init(chip);1324 if (err)1325 return err;1326 1327 snd_cs4281_proc_init(chip);1328 return 0;1329}1330 1331static int snd_cs4281_chip_init(struct cs4281 *chip)1332{1333 unsigned int tmp;1334 unsigned long end_time;1335 int retry_count = 2;1336 1337 /* Having EPPMC.FPDN=1 prevent proper chip initialisation */1338 tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);1339 if (tmp & BA0_EPPMC_FPDN)1340 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);1341 1342 __retry:1343 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);1344 if (tmp != BA0_CFLR_DEFAULT) {1345 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);1346 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);1347 if (tmp != BA0_CFLR_DEFAULT) {1348 dev_err(chip->card->dev,1349 "CFLR setup failed (0x%x)\n", tmp);1350 return -EIO;1351 }1352 }1353 1354 /* Set the 'Configuration Write Protect' register1355 * to 4281h. Allows vendor-defined configuration1356 * space between 0e4h and 0ffh to be written. */ 1357 snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);1358 1359 tmp = snd_cs4281_peekBA0(chip, BA0_SERC1);1360 if (tmp != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {1361 dev_err(chip->card->dev,1362 "SERC1 AC'97 check failed (0x%x)\n", tmp);1363 return -EIO;1364 }1365 tmp = snd_cs4281_peekBA0(chip, BA0_SERC2);1366 if (tmp != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {1367 dev_err(chip->card->dev,1368 "SERC2 AC'97 check failed (0x%x)\n", tmp);1369 return -EIO;1370 }1371 1372 /* Sound System Power Management */1373 snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |1374 BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |1375 BA0_SSPM_ACLEN | BA0_SSPM_FMEN);1376 1377 /* Serial Port Power Management */1378 /* Blast the clock control register to zero so that the1379 * PLL starts out in a known state, and blast the master serial1380 * port control register to zero so that the serial ports also1381 * start out in a known state. */1382 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);1383 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);1384 1385 /* Make ESYN go to zero to turn off1386 * the Sync pulse on the AC97 link. */1387 snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);1388 udelay(50);1389 1390 /* Drive the ARST# pin low for a minimum of 1uS (as defined in the AC971391 * spec) and then drive it high. This is done for non AC97 modes since1392 * there might be logic external to the CS4281 that uses the ARST# line1393 * for a reset. */1394 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);1395 udelay(50);1396 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);1397 msleep(50);1398 1399 if (chip->dual_codec)1400 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);1401 1402 /*1403 * Set the serial port timing configuration.1404 */1405 snd_cs4281_pokeBA0(chip, BA0_SERMC,1406 (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |1407 BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);1408 1409 /*1410 * Start the DLL Clock logic.1411 */1412 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);1413 msleep(50);1414 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);1415 1416 /*1417 * Wait for the DLL ready signal from the clock logic.1418 */1419 end_time = jiffies + HZ;1420 do {1421 /*1422 * Read the AC97 status register to see if we've seen a CODEC1423 * signal from the AC97 codec.1424 */1425 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)1426 goto __ok0;1427 schedule_timeout_uninterruptible(1);1428 } while (time_after_eq(end_time, jiffies));1429 1430 dev_err(chip->card->dev, "DLLRDY not seen\n");1431 return -EIO;1432 1433 __ok0:1434 1435 /*1436 * The first thing we do here is to enable sync generation. As soon1437 * as we start receiving bit clock, we'll start producing the SYNC1438 * signal.1439 */1440 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);1441 1442 /*1443 * Wait for the codec ready signal from the AC97 codec.1444 */1445 end_time = jiffies + HZ;1446 do {1447 /*1448 * Read the AC97 status register to see if we've seen a CODEC1449 * signal from the AC97 codec.1450 */1451 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)1452 goto __ok1;1453 schedule_timeout_uninterruptible(1);1454 } while (time_after_eq(end_time, jiffies));1455 1456 dev_err(chip->card->dev,1457 "never read codec ready from AC'97 (0x%x)\n",1458 snd_cs4281_peekBA0(chip, BA0_ACSTS));1459 return -EIO;1460 1461 __ok1:1462 if (chip->dual_codec) {1463 end_time = jiffies + HZ;1464 do {1465 if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)1466 goto __codec2_ok;1467 schedule_timeout_uninterruptible(1);1468 } while (time_after_eq(end_time, jiffies));1469 dev_info(chip->card->dev,1470 "secondary codec doesn't respond. disable it...\n");1471 chip->dual_codec = 0;1472 __codec2_ok: ;1473 }1474 1475 /*1476 * Assert the valid frame signal so that we can start sending commands1477 * to the AC97 codec.1478 */1479 1480 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);1481 1482 /*1483 * Wait until we've sampled input slots 3 and 4 as valid, meaning that1484 * the codec is pumping ADC data across the AC-link.1485 */1486 1487 end_time = jiffies + HZ;1488 do {1489 /*1490 * Read the input slot valid register and see if input slots 31491 * 4 are valid yet.1492 */1493 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))1494 goto __ok2;1495 schedule_timeout_uninterruptible(1);1496 } while (time_after_eq(end_time, jiffies));1497 1498 if (--retry_count > 0)1499 goto __retry;1500 dev_err(chip->card->dev, "never read ISV3 and ISV4 from AC'97\n");1501 return -EIO;1502 1503 __ok2:1504 1505 /*1506 * Now, assert valid frame and the slot 3 and 4 valid bits. This will1507 * commense the transfer of digital audio data to the AC97 codec.1508 */1509 snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));1510 1511 /*1512 * Initialize DMA structures1513 */1514 for (tmp = 0; tmp < 4; tmp++) {1515 struct cs4281_dma *dma = &chip->dma[tmp];1516 dma->regDBA = BA0_DBA0 + (tmp * 0x10);1517 dma->regDCA = BA0_DCA0 + (tmp * 0x10);1518 dma->regDBC = BA0_DBC0 + (tmp * 0x10);1519 dma->regDCC = BA0_DCC0 + (tmp * 0x10);1520 dma->regDMR = BA0_DMR0 + (tmp * 8);1521 dma->regDCR = BA0_DCR0 + (tmp * 8);1522 dma->regHDSR = BA0_HDSR0 + (tmp * 4);1523 dma->regFCR = BA0_FCR0 + (tmp * 4);1524 dma->regFSIC = BA0_FSIC0 + (tmp * 4);1525 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;1526 snd_cs4281_pokeBA0(chip, dma->regFCR,1527 BA0_FCR_LS(31) |1528 BA0_FCR_RS(31) |1529 BA0_FCR_SZ(CS4281_FIFO_SIZE) |1530 BA0_FCR_OF(dma->fifo_offset));1531 }1532 1533 chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */1534 chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */1535 chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */1536 chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */1537 1538 /* Activate wave playback FIFO for FM playback */1539 chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |1540 BA0_FCR_RS(1) |1541 BA0_FCR_SZ(CS4281_FIFO_SIZE) |1542 BA0_FCR_OF(chip->dma[0].fifo_offset);1543 snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);1544 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |1545 (chip->src_right_play_slot << 8) |1546 (chip->src_left_rec_slot << 16) |1547 (chip->src_right_rec_slot << 24));1548 1549 /* Initialize digital volume */1550 snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);1551 snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);1552 1553 /* Enable IRQs */1554 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);1555 /* Unmask interrupts */1556 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(1557 BA0_HISR_MIDI |1558 BA0_HISR_DMAI |1559 BA0_HISR_DMA(0) |1560 BA0_HISR_DMA(1) |1561 BA0_HISR_DMA(2) |1562 BA0_HISR_DMA(3)));1563 1564 return 0;1565}1566 1567/*1568 * MIDI section1569 */1570 1571static void snd_cs4281_midi_reset(struct cs4281 *chip)1572{1573 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);1574 udelay(100);1575 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);1576}1577 1578static int snd_cs4281_midi_input_open(struct snd_rawmidi_substream *substream)1579{1580 struct cs4281 *chip = substream->rmidi->private_data;1581 1582 spin_lock_irq(&chip->reg_lock);1583 chip->midcr |= BA0_MIDCR_RXE;1584 chip->midi_input = substream;1585 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {1586 snd_cs4281_midi_reset(chip);1587 } else {1588 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);1589 }1590 spin_unlock_irq(&chip->reg_lock);1591 return 0;1592}1593 1594static int snd_cs4281_midi_input_close(struct snd_rawmidi_substream *substream)1595{1596 struct cs4281 *chip = substream->rmidi->private_data;1597 1598 spin_lock_irq(&chip->reg_lock);1599 chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);1600 chip->midi_input = NULL;1601 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {1602 snd_cs4281_midi_reset(chip);1603 } else {1604 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);1605 }1606 chip->uartm &= ~CS4281_MODE_INPUT;1607 spin_unlock_irq(&chip->reg_lock);1608 return 0;1609}1610 1611static int snd_cs4281_midi_output_open(struct snd_rawmidi_substream *substream)1612{1613 struct cs4281 *chip = substream->rmidi->private_data;1614 1615 spin_lock_irq(&chip->reg_lock);1616 chip->uartm |= CS4281_MODE_OUTPUT;1617 chip->midcr |= BA0_MIDCR_TXE;1618 chip->midi_output = substream;1619 if (!(chip->uartm & CS4281_MODE_INPUT)) {1620 snd_cs4281_midi_reset(chip);1621 } else {1622 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);1623 }1624 spin_unlock_irq(&chip->reg_lock);1625 return 0;1626}1627 1628static int snd_cs4281_midi_output_close(struct snd_rawmidi_substream *substream)1629{1630 struct cs4281 *chip = substream->rmidi->private_data;1631 1632 spin_lock_irq(&chip->reg_lock);1633 chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);1634 chip->midi_output = NULL;1635 if (!(chip->uartm & CS4281_MODE_INPUT)) {1636 snd_cs4281_midi_reset(chip);1637 } else {1638 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);1639 }1640 chip->uartm &= ~CS4281_MODE_OUTPUT;1641 spin_unlock_irq(&chip->reg_lock);1642 return 0;1643}1644 1645static void snd_cs4281_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)1646{1647 unsigned long flags;1648 struct cs4281 *chip = substream->rmidi->private_data;1649 1650 spin_lock_irqsave(&chip->reg_lock, flags);1651 if (up) {1652 if ((chip->midcr & BA0_MIDCR_RIE) == 0) {1653 chip->midcr |= BA0_MIDCR_RIE;1654 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);1655 }1656 } else {1657 if (chip->midcr & BA0_MIDCR_RIE) {1658 chip->midcr &= ~BA0_MIDCR_RIE;1659 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);1660 }1661 }1662 spin_unlock_irqrestore(&chip->reg_lock, flags);1663}1664 1665static void snd_cs4281_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)1666{1667 unsigned long flags;1668 struct cs4281 *chip = substream->rmidi->private_data;1669 unsigned char byte;1670 1671 spin_lock_irqsave(&chip->reg_lock, flags);1672 if (up) {1673 if ((chip->midcr & BA0_MIDCR_TIE) == 0) {1674 chip->midcr |= BA0_MIDCR_TIE;1675 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */1676 while ((chip->midcr & BA0_MIDCR_TIE) &&1677 (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {1678 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {1679 chip->midcr &= ~BA0_MIDCR_TIE;1680 } else {1681 snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);1682 }1683 }1684 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);1685 }1686 } else {1687 if (chip->midcr & BA0_MIDCR_TIE) {1688 chip->midcr &= ~BA0_MIDCR_TIE;1689 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);1690 }1691 }1692 spin_unlock_irqrestore(&chip->reg_lock, flags);1693}1694 1695static const struct snd_rawmidi_ops snd_cs4281_midi_output =1696{1697 .open = snd_cs4281_midi_output_open,1698 .close = snd_cs4281_midi_output_close,1699 .trigger = snd_cs4281_midi_output_trigger,1700};1701 1702static const struct snd_rawmidi_ops snd_cs4281_midi_input =1703{1704 .open = snd_cs4281_midi_input_open,1705 .close = snd_cs4281_midi_input_close,1706 .trigger = snd_cs4281_midi_input_trigger,1707};1708 1709static int snd_cs4281_midi(struct cs4281 *chip, int device)1710{1711 struct snd_rawmidi *rmidi;1712 int err;1713 1714 err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi);1715 if (err < 0)1716 return err;1717 strcpy(rmidi->name, "CS4281");1718 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);1719 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);1720 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;1721 rmidi->private_data = chip;1722 chip->rmidi = rmidi;1723 return 0;1724}1725 1726/*1727 * Interrupt handler1728 */1729 1730static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id)1731{1732 struct cs4281 *chip = dev_id;1733 unsigned int status, dma, val;1734 struct cs4281_dma *cdma;1735 1736 if (chip == NULL)1737 return IRQ_NONE;1738 status = snd_cs4281_peekBA0(chip, BA0_HISR);1739 if ((status & 0x7fffffff) == 0) {1740 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);1741 return IRQ_NONE;1742 }1743 1744 if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {1745 for (dma = 0; dma < 4; dma++)1746 if (status & BA0_HISR_DMA(dma)) {1747 cdma = &chip->dma[dma];1748 spin_lock(&chip->reg_lock);1749 /* ack DMA IRQ */1750 val = snd_cs4281_peekBA0(chip, cdma->regHDSR);1751 /* workaround, sometimes CS4281 acknowledges */1752 /* end or middle transfer position twice */1753 cdma->frag++;1754 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {1755 cdma->frag--;1756 chip->spurious_dhtc_irq++;1757 spin_unlock(&chip->reg_lock);1758 continue;1759 }1760 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {1761 cdma->frag--;1762 chip->spurious_dtc_irq++;1763 spin_unlock(&chip->reg_lock);1764 continue;1765 }1766 spin_unlock(&chip->reg_lock);1767 snd_pcm_period_elapsed(cdma->substream);1768 }1769 }1770 1771 if ((status & BA0_HISR_MIDI) && chip->rmidi) {1772 unsigned char c;1773 1774 spin_lock(&chip->reg_lock);1775 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {1776 c = snd_cs4281_peekBA0(chip, BA0_MIDRP);1777 if ((chip->midcr & BA0_MIDCR_RIE) == 0)1778 continue;1779 snd_rawmidi_receive(chip->midi_input, &c, 1);1780 }1781 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {1782 if ((chip->midcr & BA0_MIDCR_TIE) == 0)1783 break;1784 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {1785 chip->midcr &= ~BA0_MIDCR_TIE;1786 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);1787 break;1788 }1789 snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);1790 }1791 spin_unlock(&chip->reg_lock);1792 }1793 1794 /* EOI to the PCI part... reenables interrupts */1795 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);1796 1797 return IRQ_HANDLED;1798}1799 1800 1801/*1802 * OPL3 command1803 */1804static void snd_cs4281_opl3_command(struct snd_opl3 *opl3, unsigned short cmd,1805 unsigned char val)1806{1807 unsigned long flags;1808 struct cs4281 *chip = opl3->private_data;1809 void __iomem *port;1810 1811 if (cmd & OPL3_RIGHT)1812 port = chip->ba0 + BA0_B1AP; /* right port */1813 else1814 port = chip->ba0 + BA0_B0AP; /* left port */1815 1816 spin_lock_irqsave(&opl3->reg_lock, flags);1817 1818 writel((unsigned int)cmd, port);1819 udelay(10);1820 1821 writel((unsigned int)val, port + 4);1822 udelay(30);1823 1824 spin_unlock_irqrestore(&opl3->reg_lock, flags);1825}1826 1827static int __snd_cs4281_probe(struct pci_dev *pci,1828 const struct pci_device_id *pci_id)1829{1830 static int dev;1831 struct snd_card *card;1832 struct cs4281 *chip;1833 struct snd_opl3 *opl3;1834 int err;1835 1836 if (dev >= SNDRV_CARDS)1837 return -ENODEV;1838 if (!enable[dev]) {1839 dev++;1840 return -ENOENT;1841 }1842 1843 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,1844 sizeof(*chip), &card);1845 if (err < 0)1846 return err;1847 chip = card->private_data;1848 1849 err = snd_cs4281_create(card, pci, dual_codec[dev]);1850 if (err < 0)1851 return err;1852 1853 err = snd_cs4281_mixer(chip);1854 if (err < 0)1855 return err;1856 err = snd_cs4281_pcm(chip, 0);1857 if (err < 0)1858 return err;1859 err = snd_cs4281_midi(chip, 0);1860 if (err < 0)1861 return err;1862 err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3);1863 if (err < 0)1864 return err;1865 opl3->private_data = chip;1866 opl3->command = snd_cs4281_opl3_command;1867 snd_opl3_init(opl3);1868 err = snd_opl3_hwdep_new(opl3, 0, 1, NULL);1869 if (err < 0)1870 return err;1871 snd_cs4281_create_gameport(chip);1872 strcpy(card->driver, "CS4281");1873 strcpy(card->shortname, "Cirrus Logic CS4281");1874 sprintf(card->longname, "%s at 0x%lx, irq %d",1875 card->shortname,1876 chip->ba0_addr,1877 chip->irq);1878 1879 err = snd_card_register(card);1880 if (err < 0)1881 return err;1882 1883 pci_set_drvdata(pci, card);1884 dev++;1885 return 0;1886}1887 1888static int snd_cs4281_probe(struct pci_dev *pci,1889 const struct pci_device_id *pci_id)1890{1891 return snd_card_free_on_error(&pci->dev, __snd_cs4281_probe(pci, pci_id));1892}1893 1894/*1895 * Power Management1896 */1897static const int saved_regs[SUSPEND_REGISTERS] = {1898 BA0_JSCTL,1899 BA0_GPIOR,1900 BA0_SSCR,1901 BA0_MIDCR,1902 BA0_SRCSA,1903 BA0_PASR,1904 BA0_CASR,1905 BA0_DACSR,1906 BA0_ADCSR,1907 BA0_FMLVC,1908 BA0_FMRVC,1909 BA0_PPLVC,1910 BA0_PPRVC,1911};1912 1913#define CLKCR1_CKRA 0x00010000L1914 1915static int cs4281_suspend(struct device *dev)1916{1917 struct snd_card *card = dev_get_drvdata(dev);1918 struct cs4281 *chip = card->private_data;1919 u32 ulCLK;1920 unsigned int i;1921 1922 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);1923 snd_ac97_suspend(chip->ac97);1924 snd_ac97_suspend(chip->ac97_secondary);1925 1926 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);1927 ulCLK |= CLKCR1_CKRA;1928 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);1929 1930 /* Disable interrupts. */1931 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);1932 1933 /* remember the status registers */1934 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)1935 if (saved_regs[i])1936 chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);1937 1938 /* Turn off the serial ports. */1939 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);1940 1941 /* Power off FM, Joystick, AC link, */1942 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);1943 1944 /* DLL off. */1945 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);1946 1947 /* AC link off. */1948 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);1949 1950 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);1951 ulCLK &= ~CLKCR1_CKRA;1952 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);1953 return 0;1954}1955 1956static int cs4281_resume(struct device *dev)1957{1958 struct snd_card *card = dev_get_drvdata(dev);1959 struct cs4281 *chip = card->private_data;1960 unsigned int i;1961 u32 ulCLK;1962 1963 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);1964 ulCLK |= CLKCR1_CKRA;1965 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);1966 1967 snd_cs4281_chip_init(chip);1968 1969 /* restore the status registers */1970 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)1971 if (saved_regs[i])1972 snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);1973 1974 snd_ac97_resume(chip->ac97);1975 snd_ac97_resume(chip->ac97_secondary);1976 1977 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);1978 ulCLK &= ~CLKCR1_CKRA;1979 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);1980 1981 snd_power_change_state(card, SNDRV_CTL_POWER_D0);1982 return 0;1983}1984 1985static DEFINE_SIMPLE_DEV_PM_OPS(cs4281_pm, cs4281_suspend, cs4281_resume);1986 1987static struct pci_driver cs4281_driver = {1988 .name = KBUILD_MODNAME,1989 .id_table = snd_cs4281_ids,1990 .probe = snd_cs4281_probe,1991 .driver = {1992 .pm = &cs4281_pm,1993 },1994};1995 1996module_pci_driver(cs4281_driver);1997