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1/* SPDX-License-Identifier: GPL-2.0-or-later */2#ifndef __SOUND_CS46XX_H3#define __SOUND_CS46XX_H4 5/*6 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,7 * Cirrus Logic, Inc.8 * Definitions for Cirrus Logic CS46xx chips9 */10 11#include <sound/pcm.h>12#include <sound/pcm-indirect.h>13#include <sound/rawmidi.h>14#include <sound/ac97_codec.h>15#include "cs46xx_dsp_spos.h"16 17/*18 * Direct registers19 */20 21/*22 * The following define the offsets of the registers accessed via base address23 * register zero on the CS46xx part.24 */25#define BA0_HISR 0x0000000026#define BA0_HSR0 0x0000000427#define BA0_HICR 0x0000000828#define BA0_DMSR 0x0000010029#define BA0_HSAR 0x0000011030#define BA0_HDAR 0x0000011431#define BA0_HDMR 0x0000011832#define BA0_HDCR 0x0000011C33#define BA0_PFMC 0x0000020034#define BA0_PFCV1 0x0000020435#define BA0_PFCV2 0x0000020836#define BA0_PCICFG00 0x0000030037#define BA0_PCICFG04 0x0000030438#define BA0_PCICFG08 0x0000030839#define BA0_PCICFG0C 0x0000030C40#define BA0_PCICFG10 0x0000031041#define BA0_PCICFG14 0x0000031442#define BA0_PCICFG18 0x0000031843#define BA0_PCICFG1C 0x0000031C44#define BA0_PCICFG20 0x0000032045#define BA0_PCICFG24 0x0000032446#define BA0_PCICFG28 0x0000032847#define BA0_PCICFG2C 0x0000032C48#define BA0_PCICFG30 0x0000033049#define BA0_PCICFG34 0x0000033450#define BA0_PCICFG38 0x0000033851#define BA0_PCICFG3C 0x0000033C52#define BA0_CLKCR1 0x0000040053#define BA0_CLKCR2 0x0000040454#define BA0_PLLM 0x0000040855#define BA0_PLLCC 0x0000040C56#define BA0_FRR 0x00000410 57#define BA0_CFL1 0x0000041458#define BA0_CFL2 0x0000041859#define BA0_SERMC1 0x0000042060#define BA0_SERMC2 0x0000042461#define BA0_SERC1 0x0000042862#define BA0_SERC2 0x0000042C63#define BA0_SERC3 0x0000043064#define BA0_SERC4 0x0000043465#define BA0_SERC5 0x0000043866#define BA0_SERBSP 0x0000043C67#define BA0_SERBST 0x0000044068#define BA0_SERBCM 0x0000044469#define BA0_SERBAD 0x0000044870#define BA0_SERBCF 0x0000044C71#define BA0_SERBWP 0x0000045072#define BA0_SERBRP 0x0000045473#ifndef NO_CS461274#define BA0_ASER_FADDR 0x0000045875#endif76#define BA0_ACCTL 0x0000046077#define BA0_ACSTS 0x0000046478#define BA0_ACOSV 0x0000046879#define BA0_ACCAD 0x0000046C80#define BA0_ACCDA 0x0000047081#define BA0_ACISV 0x0000047482#define BA0_ACSAD 0x0000047883#define BA0_ACSDA 0x0000047C84#define BA0_JSPT 0x0000048085#define BA0_JSCTL 0x0000048486#define BA0_JSC1 0x0000048887#define BA0_JSC2 0x0000048C88#define BA0_MIDCR 0x0000049089#define BA0_MIDSR 0x0000049490#define BA0_MIDWP 0x0000049891#define BA0_MIDRP 0x0000049C92#define BA0_JSIO 0x000004A093#ifndef NO_CS461294#define BA0_ASER_MASTER 0x000004A495#endif96#define BA0_CFGI 0x000004B097#define BA0_SSVID 0x000004B498#define BA0_GPIOR 0x000004B899#ifndef NO_CS4612100#define BA0_EGPIODR 0x000004BC101#define BA0_EGPIOPTR 0x000004C0102#define BA0_EGPIOTR 0x000004C4103#define BA0_EGPIOWR 0x000004C8104#define BA0_EGPIOSR 0x000004CC105#define BA0_SERC6 0x000004D0106#define BA0_SERC7 0x000004D4107#define BA0_SERACC 0x000004D8108#define BA0_ACCTL2 0x000004E0109#define BA0_ACSTS2 0x000004E4110#define BA0_ACOSV2 0x000004E8111#define BA0_ACCAD2 0x000004EC112#define BA0_ACCDA2 0x000004F0113#define BA0_ACISV2 0x000004F4114#define BA0_ACSAD2 0x000004F8115#define BA0_ACSDA2 0x000004FC116#define BA0_IOTAC0 0x00000500117#define BA0_IOTAC1 0x00000504118#define BA0_IOTAC2 0x00000508119#define BA0_IOTAC3 0x0000050C120#define BA0_IOTAC4 0x00000510121#define BA0_IOTAC5 0x00000514122#define BA0_IOTAC6 0x00000518123#define BA0_IOTAC7 0x0000051C124#define BA0_IOTAC8 0x00000520125#define BA0_IOTAC9 0x00000524126#define BA0_IOTAC10 0x00000528127#define BA0_IOTAC11 0x0000052C128#define BA0_IOTFR0 0x00000540129#define BA0_IOTFR1 0x00000544130#define BA0_IOTFR2 0x00000548131#define BA0_IOTFR3 0x0000054C132#define BA0_IOTFR4 0x00000550133#define BA0_IOTFR5 0x00000554134#define BA0_IOTFR6 0x00000558135#define BA0_IOTFR7 0x0000055C136#define BA0_IOTFIFO 0x00000580137#define BA0_IOTRRD 0x00000584138#define BA0_IOTFP 0x00000588139#define BA0_IOTCR 0x0000058C140#define BA0_DPCID 0x00000590141#define BA0_DPCIA 0x00000594142#define BA0_DPCIC 0x00000598143#define BA0_PCPCIR 0x00000600144#define BA0_PCPCIG 0x00000604145#define BA0_PCPCIEN 0x00000608146#define BA0_EPCIPMC 0x00000610147#endif148 149/*150 * The following define the offsets of the registers and memories accessed via151 * base address register one on the CS46xx part.152 */153#define BA1_SP_DMEM0 0x00000000154#define BA1_SP_DMEM1 0x00010000155#define BA1_SP_PMEM 0x00020000156#define BA1_SP_REG 0x00030000157#define BA1_SPCR 0x00030000158#define BA1_DREG 0x00030004159#define BA1_DSRWP 0x00030008160#define BA1_TWPR 0x0003000C161#define BA1_SPWR 0x00030010162#define BA1_SPIR 0x00030014163#define BA1_FGR1 0x00030020164#define BA1_SPCS 0x00030028165#define BA1_SDSR 0x0003002C166#define BA1_FRMT 0x00030030167#define BA1_FRCC 0x00030034168#define BA1_FRSC 0x00030038169#define BA1_OMNI_MEM 0x000E0000170 171 172/*173 * The following defines are for the flags in the host interrupt status174 * register.175 */176#define HISR_VC_MASK 0x0000FFFF177#define HISR_VC0 0x00000001178#define HISR_VC1 0x00000002179#define HISR_VC2 0x00000004180#define HISR_VC3 0x00000008181#define HISR_VC4 0x00000010182#define HISR_VC5 0x00000020183#define HISR_VC6 0x00000040184#define HISR_VC7 0x00000080185#define HISR_VC8 0x00000100186#define HISR_VC9 0x00000200187#define HISR_VC10 0x00000400188#define HISR_VC11 0x00000800189#define HISR_VC12 0x00001000190#define HISR_VC13 0x00002000191#define HISR_VC14 0x00004000192#define HISR_VC15 0x00008000193#define HISR_INT0 0x00010000194#define HISR_INT1 0x00020000195#define HISR_DMAI 0x00040000196#define HISR_FROVR 0x00080000197#define HISR_MIDI 0x00100000198#ifdef NO_CS4612199#define HISR_RESERVED 0x0FE00000200#else201#define HISR_SBINT 0x00200000202#define HISR_RESERVED 0x0FC00000203#endif204#define HISR_H0P 0x40000000205#define HISR_INTENA 0x80000000206 207/*208 * The following defines are for the flags in the host signal register 0.209 */210#define HSR0_VC_MASK 0xFFFFFFFF211#define HSR0_VC16 0x00000001212#define HSR0_VC17 0x00000002213#define HSR0_VC18 0x00000004214#define HSR0_VC19 0x00000008215#define HSR0_VC20 0x00000010216#define HSR0_VC21 0x00000020217#define HSR0_VC22 0x00000040218#define HSR0_VC23 0x00000080219#define HSR0_VC24 0x00000100220#define HSR0_VC25 0x00000200221#define HSR0_VC26 0x00000400222#define HSR0_VC27 0x00000800223#define HSR0_VC28 0x00001000224#define HSR0_VC29 0x00002000225#define HSR0_VC30 0x00004000226#define HSR0_VC31 0x00008000227#define HSR0_VC32 0x00010000228#define HSR0_VC33 0x00020000229#define HSR0_VC34 0x00040000230#define HSR0_VC35 0x00080000231#define HSR0_VC36 0x00100000232#define HSR0_VC37 0x00200000233#define HSR0_VC38 0x00400000234#define HSR0_VC39 0x00800000235#define HSR0_VC40 0x01000000236#define HSR0_VC41 0x02000000237#define HSR0_VC42 0x04000000238#define HSR0_VC43 0x08000000239#define HSR0_VC44 0x10000000240#define HSR0_VC45 0x20000000241#define HSR0_VC46 0x40000000242#define HSR0_VC47 0x80000000243 244/*245 * The following defines are for the flags in the host interrupt control246 * register.247 */248#define HICR_IEV 0x00000001249#define HICR_CHGM 0x00000002250 251/*252 * The following defines are for the flags in the DMA status register.253 */254#define DMSR_HP 0x00000001255#define DMSR_HR 0x00000002256#define DMSR_SP 0x00000004257#define DMSR_SR 0x00000008258 259/*260 * The following defines are for the flags in the host DMA source address261 * register.262 */263#define HSAR_HOST_ADDR_MASK 0xFFFFFFFF264#define HSAR_DSP_ADDR_MASK 0x0000FFFF265#define HSAR_MEMID_MASK 0x000F0000266#define HSAR_MEMID_SP_DMEM0 0x00000000267#define HSAR_MEMID_SP_DMEM1 0x00010000268#define HSAR_MEMID_SP_PMEM 0x00020000269#define HSAR_MEMID_SP_DEBUG 0x00030000270#define HSAR_MEMID_OMNI_MEM 0x000E0000271#define HSAR_END 0x40000000272#define HSAR_ERR 0x80000000273 274/*275 * The following defines are for the flags in the host DMA destination address276 * register.277 */278#define HDAR_HOST_ADDR_MASK 0xFFFFFFFF279#define HDAR_DSP_ADDR_MASK 0x0000FFFF280#define HDAR_MEMID_MASK 0x000F0000281#define HDAR_MEMID_SP_DMEM0 0x00000000282#define HDAR_MEMID_SP_DMEM1 0x00010000283#define HDAR_MEMID_SP_PMEM 0x00020000284#define HDAR_MEMID_SP_DEBUG 0x00030000285#define HDAR_MEMID_OMNI_MEM 0x000E0000286#define HDAR_END 0x40000000287#define HDAR_ERR 0x80000000288 289/*290 * The following defines are for the flags in the host DMA control register.291 */292#define HDMR_AC_MASK 0x0000F000293#define HDMR_AC_8_16 0x00001000294#define HDMR_AC_M_S 0x00002000295#define HDMR_AC_B_L 0x00004000296#define HDMR_AC_S_U 0x00008000297 298/*299 * The following defines are for the flags in the host DMA control register.300 */301#define HDCR_COUNT_MASK 0x000003FF302#define HDCR_DONE 0x00004000303#define HDCR_OPT 0x00008000304#define HDCR_WBD 0x00400000305#define HDCR_WBS 0x00800000306#define HDCR_DMS_MASK 0x07000000307#define HDCR_DMS_LINEAR 0x00000000308#define HDCR_DMS_16_DWORDS 0x01000000309#define HDCR_DMS_32_DWORDS 0x02000000310#define HDCR_DMS_64_DWORDS 0x03000000311#define HDCR_DMS_128_DWORDS 0x04000000312#define HDCR_DMS_256_DWORDS 0x05000000313#define HDCR_DMS_512_DWORDS 0x06000000314#define HDCR_DMS_1024_DWORDS 0x07000000315#define HDCR_DH 0x08000000316#define HDCR_SMS_MASK 0x70000000317#define HDCR_SMS_LINEAR 0x00000000318#define HDCR_SMS_16_DWORDS 0x10000000319#define HDCR_SMS_32_DWORDS 0x20000000320#define HDCR_SMS_64_DWORDS 0x30000000321#define HDCR_SMS_128_DWORDS 0x40000000322#define HDCR_SMS_256_DWORDS 0x50000000323#define HDCR_SMS_512_DWORDS 0x60000000324#define HDCR_SMS_1024_DWORDS 0x70000000325#define HDCR_SH 0x80000000326#define HDCR_COUNT_SHIFT 0327 328/*329 * The following defines are for the flags in the performance monitor control330 * register.331 */332#define PFMC_C1SS_MASK 0x0000001F333#define PFMC_C1EV 0x00000020334#define PFMC_C1RS 0x00008000335#define PFMC_C2SS_MASK 0x001F0000336#define PFMC_C2EV 0x00200000337#define PFMC_C2RS 0x80000000338#define PFMC_C1SS_SHIFT 0339#define PFMC_C2SS_SHIFT 16340#define PFMC_BUS_GRANT 0341#define PFMC_GRANT_AFTER_REQ 1342#define PFMC_TRANSACTION 2343#define PFMC_DWORD_TRANSFER 3344#define PFMC_SLAVE_READ 4345#define PFMC_SLAVE_WRITE 5346#define PFMC_PREEMPTION 6347#define PFMC_DISCONNECT_RETRY 7348#define PFMC_INTERRUPT 8349#define PFMC_BUS_OWNERSHIP 9350#define PFMC_TRANSACTION_LAG 10351#define PFMC_PCI_CLOCK 11352#define PFMC_SERIAL_CLOCK 12353#define PFMC_SP_CLOCK 13354 355/*356 * The following defines are for the flags in the performance counter value 1357 * register.358 */359#define PFCV1_PC1V_MASK 0xFFFFFFFF360#define PFCV1_PC1V_SHIFT 0361 362/*363 * The following defines are for the flags in the performance counter value 2364 * register.365 */366#define PFCV2_PC2V_MASK 0xFFFFFFFF367#define PFCV2_PC2V_SHIFT 0368 369/*370 * The following defines are for the flags in the clock control register 1.371 */372#define CLKCR1_OSCS 0x00000001373#define CLKCR1_OSCP 0x00000002374#define CLKCR1_PLLSS_MASK 0x0000000C375#define CLKCR1_PLLSS_SERIAL 0x00000000376#define CLKCR1_PLLSS_CRYSTAL 0x00000004377#define CLKCR1_PLLSS_PCI 0x00000008378#define CLKCR1_PLLSS_RESERVED 0x0000000C379#define CLKCR1_PLLP 0x00000010380#define CLKCR1_SWCE 0x00000020381#define CLKCR1_PLLOS 0x00000040382 383/*384 * The following defines are for the flags in the clock control register 2.385 */386#define CLKCR2_PDIVS_MASK 0x0000000F387#define CLKCR2_PDIVS_1 0x00000001388#define CLKCR2_PDIVS_2 0x00000002389#define CLKCR2_PDIVS_4 0x00000004390#define CLKCR2_PDIVS_7 0x00000007391#define CLKCR2_PDIVS_8 0x00000008392#define CLKCR2_PDIVS_16 0x00000000393 394/*395 * The following defines are for the flags in the PLL multiplier register.396 */397#define PLLM_MASK 0x000000FF398#define PLLM_SHIFT 0399 400/*401 * The following defines are for the flags in the PLL capacitor coefficient402 * register.403 */404#define PLLCC_CDR_MASK 0x00000007405#ifndef NO_CS4610406#define PLLCC_CDR_240_350_MHZ 0x00000000407#define PLLCC_CDR_184_265_MHZ 0x00000001408#define PLLCC_CDR_144_205_MHZ 0x00000002409#define PLLCC_CDR_111_160_MHZ 0x00000003410#define PLLCC_CDR_87_123_MHZ 0x00000004411#define PLLCC_CDR_67_96_MHZ 0x00000005412#define PLLCC_CDR_52_74_MHZ 0x00000006413#define PLLCC_CDR_45_58_MHZ 0x00000007414#endif415#ifndef NO_CS4612416#define PLLCC_CDR_271_398_MHZ 0x00000000417#define PLLCC_CDR_227_330_MHZ 0x00000001418#define PLLCC_CDR_167_239_MHZ 0x00000002419#define PLLCC_CDR_150_215_MHZ 0x00000003420#define PLLCC_CDR_107_154_MHZ 0x00000004421#define PLLCC_CDR_98_140_MHZ 0x00000005422#define PLLCC_CDR_73_104_MHZ 0x00000006423#define PLLCC_CDR_63_90_MHZ 0x00000007424#endif425#define PLLCC_LPF_MASK 0x000000F8426#ifndef NO_CS4610427#define PLLCC_LPF_23850_60000_KHZ 0x00000000428#define PLLCC_LPF_7960_26290_KHZ 0x00000008429#define PLLCC_LPF_4160_10980_KHZ 0x00000018430#define PLLCC_LPF_1740_4580_KHZ 0x00000038431#define PLLCC_LPF_724_1910_KHZ 0x00000078432#define PLLCC_LPF_317_798_KHZ 0x000000F8433#endif434#ifndef NO_CS4612435#define PLLCC_LPF_25580_64530_KHZ 0x00000000436#define PLLCC_LPF_14360_37270_KHZ 0x00000008437#define PLLCC_LPF_6100_16020_KHZ 0x00000018438#define PLLCC_LPF_2540_6690_KHZ 0x00000038439#define PLLCC_LPF_1050_2780_KHZ 0x00000078440#define PLLCC_LPF_450_1160_KHZ 0x000000F8441#endif442 443/*444 * The following defines are for the flags in the feature reporting register.445 */446#define FRR_FAB_MASK 0x00000003447#define FRR_MASK_MASK 0x0000001C448#ifdef NO_CS4612449#define FRR_CFOP_MASK 0x000000E0450#else451#define FRR_CFOP_MASK 0x00000FE0452#endif453#define FRR_CFOP_NOT_DVD 0x00000020454#define FRR_CFOP_A3D 0x00000040455#define FRR_CFOP_128_PIN 0x00000080456#ifndef NO_CS4612457#define FRR_CFOP_CS4280 0x00000800458#endif459#define FRR_FAB_SHIFT 0460#define FRR_MASK_SHIFT 2461#define FRR_CFOP_SHIFT 5462 463/*464 * The following defines are for the flags in the configuration load 1465 * register.466 */467#define CFL1_CLOCK_SOURCE_MASK 0x00000003468#define CFL1_CLOCK_SOURCE_CS423X 0x00000000469#define CFL1_CLOCK_SOURCE_AC97 0x00000001470#define CFL1_CLOCK_SOURCE_CRYSTAL 0x00000002471#define CFL1_CLOCK_SOURCE_DUAL_AC97 0x00000003472#define CFL1_VALID_DATA_MASK 0x000000FF473 474/*475 * The following defines are for the flags in the configuration load 2476 * register.477 */478#define CFL2_VALID_DATA_MASK 0x000000FF479 480/*481 * The following defines are for the flags in the serial port master control482 * register 1.483 */484#define SERMC1_MSPE 0x00000001485#define SERMC1_PTC_MASK 0x0000000E486#define SERMC1_PTC_CS423X 0x00000000487#define SERMC1_PTC_AC97 0x00000002488#define SERMC1_PTC_DAC 0x00000004489#define SERMC1_PLB 0x00000010490#define SERMC1_XLB 0x00000020491 492/*493 * The following defines are for the flags in the serial port master control494 * register 2.495 */496#define SERMC2_LROE 0x00000001497#define SERMC2_MCOE 0x00000002498#define SERMC2_MCDIV 0x00000004499 500/*501 * The following defines are for the flags in the serial port 1 configuration502 * register.503 */504#define SERC1_SO1EN 0x00000001505#define SERC1_SO1F_MASK 0x0000000E506#define SERC1_SO1F_CS423X 0x00000000507#define SERC1_SO1F_AC97 0x00000002508#define SERC1_SO1F_DAC 0x00000004509#define SERC1_SO1F_SPDIF 0x00000006510 511/*512 * The following defines are for the flags in the serial port 2 configuration513 * register.514 */515#define SERC2_SI1EN 0x00000001516#define SERC2_SI1F_MASK 0x0000000E517#define SERC2_SI1F_CS423X 0x00000000518#define SERC2_SI1F_AC97 0x00000002519#define SERC2_SI1F_ADC 0x00000004520#define SERC2_SI1F_SPDIF 0x00000006521 522/*523 * The following defines are for the flags in the serial port 3 configuration524 * register.525 */526#define SERC3_SO2EN 0x00000001527#define SERC3_SO2F_MASK 0x00000006528#define SERC3_SO2F_DAC 0x00000000529#define SERC3_SO2F_SPDIF 0x00000002530 531/*532 * The following defines are for the flags in the serial port 4 configuration533 * register.534 */535#define SERC4_SO3EN 0x00000001536#define SERC4_SO3F_MASK 0x00000006537#define SERC4_SO3F_DAC 0x00000000538#define SERC4_SO3F_SPDIF 0x00000002539 540/*541 * The following defines are for the flags in the serial port 5 configuration542 * register.543 */544#define SERC5_SI2EN 0x00000001545#define SERC5_SI2F_MASK 0x00000006546#define SERC5_SI2F_ADC 0x00000000547#define SERC5_SI2F_SPDIF 0x00000002548 549/*550 * The following defines are for the flags in the serial port backdoor sample551 * pointer register.552 */553#define SERBSP_FSP_MASK 0x0000000F554#define SERBSP_FSP_SHIFT 0555 556/*557 * The following defines are for the flags in the serial port backdoor status558 * register.559 */560#define SERBST_RRDY 0x00000001561#define SERBST_WBSY 0x00000002562 563/*564 * The following defines are for the flags in the serial port backdoor command565 * register.566 */567#define SERBCM_RDC 0x00000001568#define SERBCM_WRC 0x00000002569 570/*571 * The following defines are for the flags in the serial port backdoor address572 * register.573 */574#ifdef NO_CS4612575#define SERBAD_FAD_MASK 0x000000FF576#else577#define SERBAD_FAD_MASK 0x000001FF578#endif579#define SERBAD_FAD_SHIFT 0580 581/*582 * The following defines are for the flags in the serial port backdoor583 * configuration register.584 */585#define SERBCF_HBP 0x00000001586 587/*588 * The following defines are for the flags in the serial port backdoor write589 * port register.590 */591#define SERBWP_FWD_MASK 0x000FFFFF592#define SERBWP_FWD_SHIFT 0593 594/*595 * The following defines are for the flags in the serial port backdoor read596 * port register.597 */598#define SERBRP_FRD_MASK 0x000FFFFF599#define SERBRP_FRD_SHIFT 0600 601/*602 * The following defines are for the flags in the async FIFO address register.603 */604#ifndef NO_CS4612605#define ASER_FADDR_A1_MASK 0x000001FF606#define ASER_FADDR_EN1 0x00008000607#define ASER_FADDR_A2_MASK 0x01FF0000608#define ASER_FADDR_EN2 0x80000000609#define ASER_FADDR_A1_SHIFT 0610#define ASER_FADDR_A2_SHIFT 16611#endif612 613/*614 * The following defines are for the flags in the AC97 control register.615 */616#define ACCTL_RSTN 0x00000001617#define ACCTL_ESYN 0x00000002618#define ACCTL_VFRM 0x00000004619#define ACCTL_DCV 0x00000008620#define ACCTL_CRW 0x00000010621#define ACCTL_ASYN 0x00000020622#ifndef NO_CS4612623#define ACCTL_TC 0x00000040624#endif625 626/*627 * The following defines are for the flags in the AC97 status register.628 */629#define ACSTS_CRDY 0x00000001630#define ACSTS_VSTS 0x00000002631#ifndef NO_CS4612632#define ACSTS_WKUP 0x00000004633#endif634 635/*636 * The following defines are for the flags in the AC97 output slot valid637 * register.638 */639#define ACOSV_SLV3 0x00000001640#define ACOSV_SLV4 0x00000002641#define ACOSV_SLV5 0x00000004642#define ACOSV_SLV6 0x00000008643#define ACOSV_SLV7 0x00000010644#define ACOSV_SLV8 0x00000020645#define ACOSV_SLV9 0x00000040646#define ACOSV_SLV10 0x00000080647#define ACOSV_SLV11 0x00000100648#define ACOSV_SLV12 0x00000200649 650/*651 * The following defines are for the flags in the AC97 command address652 * register.653 */654#define ACCAD_CI_MASK 0x0000007F655#define ACCAD_CI_SHIFT 0656 657/*658 * The following defines are for the flags in the AC97 command data register.659 */660#define ACCDA_CD_MASK 0x0000FFFF661#define ACCDA_CD_SHIFT 0662 663/*664 * The following defines are for the flags in the AC97 input slot valid665 * register.666 */667#define ACISV_ISV3 0x00000001668#define ACISV_ISV4 0x00000002669#define ACISV_ISV5 0x00000004670#define ACISV_ISV6 0x00000008671#define ACISV_ISV7 0x00000010672#define ACISV_ISV8 0x00000020673#define ACISV_ISV9 0x00000040674#define ACISV_ISV10 0x00000080675#define ACISV_ISV11 0x00000100676#define ACISV_ISV12 0x00000200677 678/*679 * The following defines are for the flags in the AC97 status address680 * register.681 */682#define ACSAD_SI_MASK 0x0000007F683#define ACSAD_SI_SHIFT 0684 685/*686 * The following defines are for the flags in the AC97 status data register.687 */688#define ACSDA_SD_MASK 0x0000FFFF689#define ACSDA_SD_SHIFT 0690 691/*692 * The following defines are for the flags in the joystick poll/trigger693 * register.694 */695#define JSPT_CAX 0x00000001696#define JSPT_CAY 0x00000002697#define JSPT_CBX 0x00000004698#define JSPT_CBY 0x00000008699#define JSPT_BA1 0x00000010700#define JSPT_BA2 0x00000020701#define JSPT_BB1 0x00000040702#define JSPT_BB2 0x00000080703 704/*705 * The following defines are for the flags in the joystick control register.706 */707#define JSCTL_SP_MASK 0x00000003708#define JSCTL_SP_SLOW 0x00000000709#define JSCTL_SP_MEDIUM_SLOW 0x00000001710#define JSCTL_SP_MEDIUM_FAST 0x00000002711#define JSCTL_SP_FAST 0x00000003712#define JSCTL_ARE 0x00000004713 714/*715 * The following defines are for the flags in the joystick coordinate pair 1716 * readback register.717 */718#define JSC1_Y1V_MASK 0x0000FFFF719#define JSC1_X1V_MASK 0xFFFF0000720#define JSC1_Y1V_SHIFT 0721#define JSC1_X1V_SHIFT 16722 723/*724 * The following defines are for the flags in the joystick coordinate pair 2725 * readback register.726 */727#define JSC2_Y2V_MASK 0x0000FFFF728#define JSC2_X2V_MASK 0xFFFF0000729#define JSC2_Y2V_SHIFT 0730#define JSC2_X2V_SHIFT 16731 732/*733 * The following defines are for the flags in the MIDI control register.734 */735#define MIDCR_TXE 0x00000001 /* Enable transmitting. */736#define MIDCR_RXE 0x00000002 /* Enable receiving. */737#define MIDCR_RIE 0x00000004 /* Interrupt upon tx ready. */738#define MIDCR_TIE 0x00000008 /* Interrupt upon rx ready. */739#define MIDCR_MLB 0x00000010 /* Enable midi loopback. */740#define MIDCR_MRST 0x00000020 /* Reset interface. */741 742/*743 * The following defines are for the flags in the MIDI status register.744 */745#define MIDSR_TBF 0x00000001 /* Tx FIFO is full. */746#define MIDSR_RBE 0x00000002 /* Rx FIFO is empty. */747 748/*749 * The following defines are for the flags in the MIDI write port register.750 */751#define MIDWP_MWD_MASK 0x000000FF752#define MIDWP_MWD_SHIFT 0753 754/*755 * The following defines are for the flags in the MIDI read port register.756 */757#define MIDRP_MRD_MASK 0x000000FF758#define MIDRP_MRD_SHIFT 0759 760/*761 * The following defines are for the flags in the joystick GPIO register.762 */763#define JSIO_DAX 0x00000001764#define JSIO_DAY 0x00000002765#define JSIO_DBX 0x00000004766#define JSIO_DBY 0x00000008767#define JSIO_AXOE 0x00000010768#define JSIO_AYOE 0x00000020769#define JSIO_BXOE 0x00000040770#define JSIO_BYOE 0x00000080771 772/*773 * The following defines are for the flags in the master async/sync serial774 * port enable register.775 */776#ifndef NO_CS4612777#define ASER_MASTER_ME 0x00000001778#endif779 780/*781 * The following defines are for the flags in the configuration interface782 * register.783 */784#define CFGI_CLK 0x00000001785#define CFGI_DOUT 0x00000002786#define CFGI_DIN_EEN 0x00000004787#define CFGI_EELD 0x00000008788 789/*790 * The following defines are for the flags in the subsystem ID and vendor ID791 * register.792 */793#define SSVID_VID_MASK 0x0000FFFF794#define SSVID_SID_MASK 0xFFFF0000795#define SSVID_VID_SHIFT 0796#define SSVID_SID_SHIFT 16797 798/*799 * The following defines are for the flags in the GPIO pin interface register.800 */801#define GPIOR_VOLDN 0x00000001802#define GPIOR_VOLUP 0x00000002803#define GPIOR_SI2D 0x00000004804#define GPIOR_SI2OE 0x00000008805 806/*807 * The following defines are for the flags in the extended GPIO pin direction808 * register.809 */810#ifndef NO_CS4612811#define EGPIODR_GPOE0 0x00000001812#define EGPIODR_GPOE1 0x00000002813#define EGPIODR_GPOE2 0x00000004814#define EGPIODR_GPOE3 0x00000008815#define EGPIODR_GPOE4 0x00000010816#define EGPIODR_GPOE5 0x00000020817#define EGPIODR_GPOE6 0x00000040818#define EGPIODR_GPOE7 0x00000080819#define EGPIODR_GPOE8 0x00000100820#endif821 822/*823 * The following defines are for the flags in the extended GPIO pin polarity/824 * type register.825 */826#ifndef NO_CS4612827#define EGPIOPTR_GPPT0 0x00000001828#define EGPIOPTR_GPPT1 0x00000002829#define EGPIOPTR_GPPT2 0x00000004830#define EGPIOPTR_GPPT3 0x00000008831#define EGPIOPTR_GPPT4 0x00000010832#define EGPIOPTR_GPPT5 0x00000020833#define EGPIOPTR_GPPT6 0x00000040834#define EGPIOPTR_GPPT7 0x00000080835#define EGPIOPTR_GPPT8 0x00000100836#endif837 838/*839 * The following defines are for the flags in the extended GPIO pin sticky840 * register.841 */842#ifndef NO_CS4612843#define EGPIOTR_GPS0 0x00000001844#define EGPIOTR_GPS1 0x00000002845#define EGPIOTR_GPS2 0x00000004846#define EGPIOTR_GPS3 0x00000008847#define EGPIOTR_GPS4 0x00000010848#define EGPIOTR_GPS5 0x00000020849#define EGPIOTR_GPS6 0x00000040850#define EGPIOTR_GPS7 0x00000080851#define EGPIOTR_GPS8 0x00000100852#endif853 854/*855 * The following defines are for the flags in the extended GPIO ping wakeup856 * register.857 */858#ifndef NO_CS4612859#define EGPIOWR_GPW0 0x00000001860#define EGPIOWR_GPW1 0x00000002861#define EGPIOWR_GPW2 0x00000004862#define EGPIOWR_GPW3 0x00000008863#define EGPIOWR_GPW4 0x00000010864#define EGPIOWR_GPW5 0x00000020865#define EGPIOWR_GPW6 0x00000040866#define EGPIOWR_GPW7 0x00000080867#define EGPIOWR_GPW8 0x00000100868#endif869 870/*871 * The following defines are for the flags in the extended GPIO pin status872 * register.873 */874#ifndef NO_CS4612875#define EGPIOSR_GPS0 0x00000001876#define EGPIOSR_GPS1 0x00000002877#define EGPIOSR_GPS2 0x00000004878#define EGPIOSR_GPS3 0x00000008879#define EGPIOSR_GPS4 0x00000010880#define EGPIOSR_GPS5 0x00000020881#define EGPIOSR_GPS6 0x00000040882#define EGPIOSR_GPS7 0x00000080883#define EGPIOSR_GPS8 0x00000100884#endif885 886/*887 * The following defines are for the flags in the serial port 6 configuration888 * register.889 */890#ifndef NO_CS4612891#define SERC6_ASDO2EN 0x00000001892#endif893 894/*895 * The following defines are for the flags in the serial port 7 configuration896 * register.897 */898#ifndef NO_CS4612899#define SERC7_ASDI2EN 0x00000001900#define SERC7_POSILB 0x00000002901#define SERC7_SIPOLB 0x00000004902#define SERC7_SOSILB 0x00000008903#define SERC7_SISOLB 0x00000010904#endif905 906/*907 * The following defines are for the flags in the serial port AC link908 * configuration register.909 */910#ifndef NO_CS4612911#define SERACC_CHIP_TYPE_MASK 0x00000001912#define SERACC_CHIP_TYPE_1_03 0x00000000913#define SERACC_CHIP_TYPE_2_0 0x00000001914#define SERACC_TWO_CODECS 0x00000002915#define SERACC_MDM 0x00000004916#define SERACC_HSP 0x00000008917#define SERACC_ODT 0x00000010 /* only CS4630 */918#endif919 920/*921 * The following defines are for the flags in the AC97 control register 2.922 */923#ifndef NO_CS4612924#define ACCTL2_RSTN 0x00000001925#define ACCTL2_ESYN 0x00000002926#define ACCTL2_VFRM 0x00000004927#define ACCTL2_DCV 0x00000008928#define ACCTL2_CRW 0x00000010929#define ACCTL2_ASYN 0x00000020930#endif931 932/*933 * The following defines are for the flags in the AC97 status register 2.934 */935#ifndef NO_CS4612936#define ACSTS2_CRDY 0x00000001937#define ACSTS2_VSTS 0x00000002938#endif939 940/*941 * The following defines are for the flags in the AC97 output slot valid942 * register 2.943 */944#ifndef NO_CS4612945#define ACOSV2_SLV3 0x00000001946#define ACOSV2_SLV4 0x00000002947#define ACOSV2_SLV5 0x00000004948#define ACOSV2_SLV6 0x00000008949#define ACOSV2_SLV7 0x00000010950#define ACOSV2_SLV8 0x00000020951#define ACOSV2_SLV9 0x00000040952#define ACOSV2_SLV10 0x00000080953#define ACOSV2_SLV11 0x00000100954#define ACOSV2_SLV12 0x00000200955#endif956 957/*958 * The following defines are for the flags in the AC97 command address959 * register 2.960 */961#ifndef NO_CS4612962#define ACCAD2_CI_MASK 0x0000007F963#define ACCAD2_CI_SHIFT 0964#endif965 966/*967 * The following defines are for the flags in the AC97 command data register968 * 2.969 */970#ifndef NO_CS4612971#define ACCDA2_CD_MASK 0x0000FFFF972#define ACCDA2_CD_SHIFT 0 973#endif974 975/*976 * The following defines are for the flags in the AC97 input slot valid977 * register 2.978 */979#ifndef NO_CS4612980#define ACISV2_ISV3 0x00000001981#define ACISV2_ISV4 0x00000002982#define ACISV2_ISV5 0x00000004983#define ACISV2_ISV6 0x00000008984#define ACISV2_ISV7 0x00000010985#define ACISV2_ISV8 0x00000020986#define ACISV2_ISV9 0x00000040987#define ACISV2_ISV10 0x00000080988#define ACISV2_ISV11 0x00000100989#define ACISV2_ISV12 0x00000200990#endif991 992/*993 * The following defines are for the flags in the AC97 status address994 * register 2.995 */996#ifndef NO_CS4612997#define ACSAD2_SI_MASK 0x0000007F998#define ACSAD2_SI_SHIFT 0999#endif1000 1001/*1002 * The following defines are for the flags in the AC97 status data register 2.1003 */1004#ifndef NO_CS46121005#define ACSDA2_SD_MASK 0x0000FFFF1006#define ACSDA2_SD_SHIFT 01007#endif1008 1009/*1010 * The following defines are for the flags in the I/O trap address and control1011 * registers (all 12).1012 */1013#ifndef NO_CS46121014#define IOTAC_SA_MASK 0x0000FFFF1015#define IOTAC_MSK_MASK 0x000F00001016#define IOTAC_IODC_MASK 0x060000001017#define IOTAC_IODC_16_BIT 0x000000001018#define IOTAC_IODC_10_BIT 0x020000001019#define IOTAC_IODC_12_BIT 0x040000001020#define IOTAC_WSPI 0x080000001021#define IOTAC_RSPI 0x100000001022#define IOTAC_WSE 0x200000001023#define IOTAC_WE 0x400000001024#define IOTAC_RE 0x800000001025#define IOTAC_SA_SHIFT 01026#define IOTAC_MSK_SHIFT 161027#endif1028 1029/*1030 * The following defines are for the flags in the I/O trap fast read registers1031 * (all 8).1032 */1033#ifndef NO_CS46121034#define IOTFR_D_MASK 0x0000FFFF1035#define IOTFR_A_MASK 0x000F00001036#define IOTFR_R_MASK 0x0F0000001037#define IOTFR_ALL 0x400000001038#define IOTFR_VL 0x800000001039#define IOTFR_D_SHIFT 01040#define IOTFR_A_SHIFT 161041#define IOTFR_R_SHIFT 241042#endif1043 1044/*1045 * The following defines are for the flags in the I/O trap FIFO register.1046 */1047#ifndef NO_CS46121048#define IOTFIFO_BA_MASK 0x00003FFF1049#define IOTFIFO_S_MASK 0x00FF00001050#define IOTFIFO_OF 0x400000001051#define IOTFIFO_SPIOF 0x800000001052#define IOTFIFO_BA_SHIFT 01053#define IOTFIFO_S_SHIFT 161054#endif1055 1056/*1057 * The following defines are for the flags in the I/O trap retry read data1058 * register.1059 */1060#ifndef NO_CS46121061#define IOTRRD_D_MASK 0x0000FFFF1062#define IOTRRD_RDV 0x800000001063#define IOTRRD_D_SHIFT 01064#endif1065 1066/*1067 * The following defines are for the flags in the I/O trap FIFO pointer1068 * register.1069 */1070#ifndef NO_CS46121071#define IOTFP_CA_MASK 0x00003FFF1072#define IOTFP_PA_MASK 0x3FFF00001073#define IOTFP_CA_SHIFT 01074#define IOTFP_PA_SHIFT 161075#endif1076 1077/*1078 * The following defines are for the flags in the I/O trap control register.1079 */1080#ifndef NO_CS46121081#define IOTCR_ITD 0x000000011082#define IOTCR_HRV 0x000000021083#define IOTCR_SRV 0x000000041084#define IOTCR_DTI 0x000000081085#define IOTCR_DFI 0x000000101086#define IOTCR_DDP 0x000000201087#define IOTCR_JTE 0x000000401088#define IOTCR_PPE 0x000000801089#endif1090 1091/*1092 * The following defines are for the flags in the direct PCI data register.1093 */1094#ifndef NO_CS46121095#define DPCID_D_MASK 0xFFFFFFFF1096#define DPCID_D_SHIFT 01097#endif1098 1099/*1100 * The following defines are for the flags in the direct PCI address register.1101 */1102#ifndef NO_CS46121103#define DPCIA_A_MASK 0xFFFFFFFF1104#define DPCIA_A_SHIFT 01105#endif1106 1107/*1108 * The following defines are for the flags in the direct PCI command register.1109 */1110#ifndef NO_CS46121111#define DPCIC_C_MASK 0x0000000F1112#define DPCIC_C_IOREAD 0x000000021113#define DPCIC_C_IOWRITE 0x000000031114#define DPCIC_BE_MASK 0x000000F01115#endif1116 1117/*1118 * The following defines are for the flags in the PC/PCI request register.1119 */1120#ifndef NO_CS46121121#define PCPCIR_RDC_MASK 0x000000071122#define PCPCIR_C_MASK 0x000070001123#define PCPCIR_REQ 0x000080001124#define PCPCIR_RDC_SHIFT 01125#define PCPCIR_C_SHIFT 121126#endif1127 1128/*1129 * The following defines are for the flags in the PC/PCI grant register.1130 */ 1131#ifndef NO_CS46121132#define PCPCIG_GDC_MASK 0x000000071133#define PCPCIG_VL 0x000080001134#define PCPCIG_GDC_SHIFT 01135#endif1136 1137/*1138 * The following defines are for the flags in the PC/PCI master enable1139 * register.1140 */1141#ifndef NO_CS46121142#define PCPCIEN_EN 0x000000011143#endif1144 1145/*1146 * The following defines are for the flags in the extended PCI power1147 * management control register.1148 */1149#ifndef NO_CS46121150#define EPCIPMC_GWU 0x000000011151#define EPCIPMC_FSPC 0x000000021152#endif 1153 1154/*1155 * The following defines are for the flags in the SP control register.1156 */1157#define SPCR_RUN 0x000000011158#define SPCR_STPFR 0x000000021159#define SPCR_RUNFR 0x000000041160#define SPCR_TICK 0x000000081161#define SPCR_DRQEN 0x000000201162#define SPCR_RSTSP 0x000000401163#define SPCR_OREN 0x000000801164#ifndef NO_CS46121165#define SPCR_PCIINT 0x000001001166#define SPCR_OINTD 0x000002001167#define SPCR_CRE 0x000080001168#endif1169 1170/*1171 * The following defines are for the flags in the debug index register.1172 */1173#define DREG_REGID_MASK 0x0000007F1174#define DREG_DEBUG 0x000000801175#define DREG_RGBK_MASK 0x000007001176#define DREG_TRAP 0x000008001177#if !defined(NO_CS4612)1178#if !defined(NO_CS4615)1179#define DREG_TRAPX 0x000010001180#endif1181#endif1182#define DREG_REGID_SHIFT 01183#define DREG_RGBK_SHIFT 81184#define DREG_RGBK_REGID_MASK 0x0000077F1185#define DREG_REGID_R0 0x000000101186#define DREG_REGID_R1 0x000000111187#define DREG_REGID_R2 0x000000121188#define DREG_REGID_R3 0x000000131189#define DREG_REGID_R4 0x000000141190#define DREG_REGID_R5 0x000000151191#define DREG_REGID_R6 0x000000161192#define DREG_REGID_R7 0x000000171193#define DREG_REGID_R8 0x000000181194#define DREG_REGID_R9 0x000000191195#define DREG_REGID_RA 0x0000001A1196#define DREG_REGID_RB 0x0000001B1197#define DREG_REGID_RC 0x0000001C1198#define DREG_REGID_RD 0x0000001D1199#define DREG_REGID_RE 0x0000001E1200#define DREG_REGID_RF 0x0000001F1201#define DREG_REGID_RA_BUS_LOW 0x000000201202#define DREG_REGID_RA_BUS_HIGH 0x000000381203#define DREG_REGID_YBUS_LOW 0x000000501204#define DREG_REGID_YBUS_HIGH 0x000000581205#define DREG_REGID_TRAP_0 0x000001001206#define DREG_REGID_TRAP_1 0x000001011207#define DREG_REGID_TRAP_2 0x000001021208#define DREG_REGID_TRAP_3 0x000001031209#define DREG_REGID_TRAP_4 0x000001041210#define DREG_REGID_TRAP_5 0x000001051211#define DREG_REGID_TRAP_6 0x000001061212#define DREG_REGID_TRAP_7 0x000001071213#define DREG_REGID_INDIRECT_ADDRESS 0x0000010E1214#define DREG_REGID_TOP_OF_STACK 0x0000010F1215#if !defined(NO_CS4612)1216#if !defined(NO_CS4615)1217#define DREG_REGID_TRAP_8 0x000001101218#define DREG_REGID_TRAP_9 0x000001111219#define DREG_REGID_TRAP_10 0x000001121220#define DREG_REGID_TRAP_11 0x000001131221#define DREG_REGID_TRAP_12 0x000001141222#define DREG_REGID_TRAP_13 0x000001151223#define DREG_REGID_TRAP_14 0x000001161224#define DREG_REGID_TRAP_15 0x000001171225#define DREG_REGID_TRAP_16 0x000001181226#define DREG_REGID_TRAP_17 0x000001191227#define DREG_REGID_TRAP_18 0x0000011A1228#define DREG_REGID_TRAP_19 0x0000011B1229#define DREG_REGID_TRAP_20 0x0000011C1230#define DREG_REGID_TRAP_21 0x0000011D1231#define DREG_REGID_TRAP_22 0x0000011E1232#define DREG_REGID_TRAP_23 0x0000011F1233#endif1234#endif1235#define DREG_REGID_RSA0_LOW 0x000002001236#define DREG_REGID_RSA0_HIGH 0x000002011237#define DREG_REGID_RSA1_LOW 0x000002021238#define DREG_REGID_RSA1_HIGH 0x000002031239#define DREG_REGID_RSA2 0x000002041240#define DREG_REGID_RSA3 0x000002051241#define DREG_REGID_RSI0_LOW 0x000002061242#define DREG_REGID_RSI0_HIGH 0x000002071243#define DREG_REGID_RSI1 0x000002081244#define DREG_REGID_RSI2 0x000002091245#define DREG_REGID_SAGUSTATUS 0x0000020A1246#define DREG_REGID_RSCONFIG01_LOW 0x0000020B1247#define DREG_REGID_RSCONFIG01_HIGH 0x0000020C1248#define DREG_REGID_RSCONFIG23_LOW 0x0000020D1249#define DREG_REGID_RSCONFIG23_HIGH 0x0000020E1250#define DREG_REGID_RSDMA01E 0x0000020F1251#define DREG_REGID_RSDMA23E 0x000002101252#define DREG_REGID_RSD0_LOW 0x000002111253#define DREG_REGID_RSD0_HIGH 0x000002121254#define DREG_REGID_RSD1_LOW 0x000002131255#define DREG_REGID_RSD1_HIGH 0x000002141256#define DREG_REGID_RSD2_LOW 0x000002151257#define DREG_REGID_RSD2_HIGH 0x000002161258#define DREG_REGID_RSD3_LOW 0x000002171259#define DREG_REGID_RSD3_HIGH 0x000002181260#define DREG_REGID_SRAR_HIGH 0x0000021A1261#define DREG_REGID_SRAR_LOW 0x0000021B1262#define DREG_REGID_DMA_STATE 0x0000021C1263#define DREG_REGID_CURRENT_DMA_STREAM 0x0000021D1264#define DREG_REGID_NEXT_DMA_STREAM 0x0000021E1265#define DREG_REGID_CPU_STATUS 0x000003001266#define DREG_REGID_MAC_MODE 0x000003011267#define DREG_REGID_STACK_AND_REPEAT 0x000003021268#define DREG_REGID_INDEX0 0x000003041269#define DREG_REGID_INDEX1 0x000003051270#define DREG_REGID_DMA_STATE_0_3 0x000004001271#define DREG_REGID_DMA_STATE_4_7 0x000004041272#define DREG_REGID_DMA_STATE_8_11 0x000004081273#define DREG_REGID_DMA_STATE_12_15 0x0000040C1274#define DREG_REGID_DMA_STATE_16_19 0x000004101275#define DREG_REGID_DMA_STATE_20_23 0x000004141276#define DREG_REGID_DMA_STATE_24_27 0x000004181277#define DREG_REGID_DMA_STATE_28_31 0x0000041C1278#define DREG_REGID_DMA_STATE_32_35 0x000004201279#define DREG_REGID_DMA_STATE_36_39 0x000004241280#define DREG_REGID_DMA_STATE_40_43 0x000004281281#define DREG_REGID_DMA_STATE_44_47 0x0000042C1282#define DREG_REGID_DMA_STATE_48_51 0x000004301283#define DREG_REGID_DMA_STATE_52_55 0x000004341284#define DREG_REGID_DMA_STATE_56_59 0x000004381285#define DREG_REGID_DMA_STATE_60_63 0x0000043C1286#define DREG_REGID_DMA_STATE_64_67 0x000004401287#define DREG_REGID_DMA_STATE_68_71 0x000004441288#define DREG_REGID_DMA_STATE_72_75 0x000004481289#define DREG_REGID_DMA_STATE_76_79 0x0000044C1290#define DREG_REGID_DMA_STATE_80_83 0x000004501291#define DREG_REGID_DMA_STATE_84_87 0x000004541292#define DREG_REGID_DMA_STATE_88_91 0x000004581293#define DREG_REGID_DMA_STATE_92_95 0x0000045C1294#define DREG_REGID_TRAP_SELECT 0x000005001295#define DREG_REGID_TRAP_WRITE_0 0x000005001296#define DREG_REGID_TRAP_WRITE_1 0x000005011297#define DREG_REGID_TRAP_WRITE_2 0x000005021298#define DREG_REGID_TRAP_WRITE_3 0x000005031299#define DREG_REGID_TRAP_WRITE_4 0x000005041300#define DREG_REGID_TRAP_WRITE_5 0x000005051301#define DREG_REGID_TRAP_WRITE_6 0x000005061302#define DREG_REGID_TRAP_WRITE_7 0x000005071303#if !defined(NO_CS4612)1304#if !defined(NO_CS4615)1305#define DREG_REGID_TRAP_WRITE_8 0x000005101306#define DREG_REGID_TRAP_WRITE_9 0x000005111307#define DREG_REGID_TRAP_WRITE_10 0x000005121308#define DREG_REGID_TRAP_WRITE_11 0x000005131309#define DREG_REGID_TRAP_WRITE_12 0x000005141310#define DREG_REGID_TRAP_WRITE_13 0x000005151311#define DREG_REGID_TRAP_WRITE_14 0x000005161312#define DREG_REGID_TRAP_WRITE_15 0x000005171313#define DREG_REGID_TRAP_WRITE_16 0x000005181314#define DREG_REGID_TRAP_WRITE_17 0x000005191315#define DREG_REGID_TRAP_WRITE_18 0x0000051A1316#define DREG_REGID_TRAP_WRITE_19 0x0000051B1317#define DREG_REGID_TRAP_WRITE_20 0x0000051C1318#define DREG_REGID_TRAP_WRITE_21 0x0000051D1319#define DREG_REGID_TRAP_WRITE_22 0x0000051E1320#define DREG_REGID_TRAP_WRITE_23 0x0000051F1321#endif1322#endif1323#define DREG_REGID_MAC0_ACC0_LOW 0x000006001324#define DREG_REGID_MAC0_ACC1_LOW 0x000006011325#define DREG_REGID_MAC0_ACC2_LOW 0x000006021326#define DREG_REGID_MAC0_ACC3_LOW 0x000006031327#define DREG_REGID_MAC1_ACC0_LOW 0x000006041328#define DREG_REGID_MAC1_ACC1_LOW 0x000006051329#define DREG_REGID_MAC1_ACC2_LOW 0x000006061330#define DREG_REGID_MAC1_ACC3_LOW 0x000006071331#define DREG_REGID_MAC0_ACC0_MID 0x000006081332#define DREG_REGID_MAC0_ACC1_MID 0x000006091333#define DREG_REGID_MAC0_ACC2_MID 0x0000060A1334#define DREG_REGID_MAC0_ACC3_MID 0x0000060B1335#define DREG_REGID_MAC1_ACC0_MID 0x0000060C1336#define DREG_REGID_MAC1_ACC1_MID 0x0000060D1337#define DREG_REGID_MAC1_ACC2_MID 0x0000060E1338#define DREG_REGID_MAC1_ACC3_MID 0x0000060F1339#define DREG_REGID_MAC0_ACC0_HIGH 0x000006101340#define DREG_REGID_MAC0_ACC1_HIGH 0x000006111341#define DREG_REGID_MAC0_ACC2_HIGH 0x000006121342#define DREG_REGID_MAC0_ACC3_HIGH 0x000006131343#define DREG_REGID_MAC1_ACC0_HIGH 0x000006141344#define DREG_REGID_MAC1_ACC1_HIGH 0x000006151345#define DREG_REGID_MAC1_ACC2_HIGH 0x000006161346#define DREG_REGID_MAC1_ACC3_HIGH 0x000006171347#define DREG_REGID_RSHOUT_LOW 0x000006201348#define DREG_REGID_RSHOUT_MID 0x000006281349#define DREG_REGID_RSHOUT_HIGH 0x000006301350 1351/*1352 * The following defines are for the flags in the DMA stream requestor write1353 */1354#define DSRWP_DSR_MASK 0x0000000F1355#define DSRWP_DSR_BG_RQ 0x000000011356#define DSRWP_DSR_PRIORITY_MASK 0x000000061357#define DSRWP_DSR_PRIORITY_0 0x000000001358#define DSRWP_DSR_PRIORITY_1 0x000000021359#define DSRWP_DSR_PRIORITY_2 0x000000041360#define DSRWP_DSR_PRIORITY_3 0x000000061361#define DSRWP_DSR_RQ_PENDING 0x000000081362 1363/*1364 * The following defines are for the flags in the trap write port register.1365 */1366#define TWPR_TW_MASK 0x0000FFFF1367#define TWPR_TW_SHIFT 01368 1369/*1370 * The following defines are for the flags in the stack pointer write1371 * register.1372 */1373#define SPWR_STKP_MASK 0x0000000F1374#define SPWR_STKP_SHIFT 01375 1376/*1377 * The following defines are for the flags in the SP interrupt register.1378 */1379#define SPIR_FRI 0x000000011380#define SPIR_DOI 0x000000021381#define SPIR_GPI2 0x000000041382#define SPIR_GPI3 0x000000081383#define SPIR_IP0 0x000000101384#define SPIR_IP1 0x000000201385#define SPIR_IP2 0x000000401386#define SPIR_IP3 0x000000801387 1388/*1389 * The following defines are for the flags in the functional group 1 register.1390 */1391#define FGR1_F1S_MASK 0x0000FFFF1392#define FGR1_F1S_SHIFT 01393 1394/*1395 * The following defines are for the flags in the SP clock status register.1396 */1397#define SPCS_FRI 0x000000011398#define SPCS_DOI 0x000000021399#define SPCS_GPI2 0x000000041400#define SPCS_GPI3 0x000000081401#define SPCS_IP0 0x000000101402#define SPCS_IP1 0x000000201403#define SPCS_IP2 0x000000401404#define SPCS_IP3 0x000000801405#define SPCS_SPRUN 0x000001001406#define SPCS_SLEEP 0x000002001407#define SPCS_FG 0x000004001408#define SPCS_ORUN 0x000008001409#define SPCS_IRQ 0x000010001410#define SPCS_FGN_MASK 0x0000E0001411#define SPCS_FGN_SHIFT 131412 1413/*1414 * The following defines are for the flags in the SP DMA requestor status1415 * register.1416 */1417#define SDSR_DCS_MASK 0x000000FF1418#define SDSR_DCS_SHIFT 01419#define SDSR_DCS_NONE 0x000000071420 1421/*1422 * The following defines are for the flags in the frame timer register.1423 */1424#define FRMT_FTV_MASK 0x0000FFFF1425#define FRMT_FTV_SHIFT 01426 1427/*1428 * The following defines are for the flags in the frame timer current count1429 * register.1430 */1431#define FRCC_FCC_MASK 0x0000FFFF1432#define FRCC_FCC_SHIFT 01433 1434/*1435 * The following defines are for the flags in the frame timer save count1436 * register.1437 */1438#define FRSC_FCS_MASK 0x0000FFFF1439#define FRSC_FCS_SHIFT 01440 1441/*1442 * The following define the various flags stored in the scatter/gather1443 * descriptors.1444 */1445#define DMA_SG_NEXT_ENTRY_MASK 0x00000FF81446#define DMA_SG_SAMPLE_END_MASK 0x0FFF00001447#define DMA_SG_SAMPLE_END_FLAG 0x100000001448#define DMA_SG_LOOP_END_FLAG 0x200000001449#define DMA_SG_SIGNAL_END_FLAG 0x400000001450#define DMA_SG_SIGNAL_PAGE_FLAG 0x800000001451#define DMA_SG_NEXT_ENTRY_SHIFT 31452#define DMA_SG_SAMPLE_END_SHIFT 161453 1454/*1455 * The following define the offsets of the fields within the on-chip generic1456 * DMA requestor.1457 */1458#define DMA_RQ_CONTROL1 0x000000001459#define DMA_RQ_CONTROL2 0x000000041460#define DMA_RQ_SOURCE_ADDR 0x000000081461#define DMA_RQ_DESTINATION_ADDR 0x0000000C1462#define DMA_RQ_NEXT_PAGE_ADDR 0x000000101463#define DMA_RQ_NEXT_PAGE_SGDESC 0x000000141464#define DMA_RQ_LOOP_START_ADDR 0x000000181465#define DMA_RQ_POST_LOOP_ADDR 0x0000001C1466#define DMA_RQ_PAGE_MAP_ADDR 0x000000201467 1468/*1469 * The following defines are for the flags in the first control word of the1470 * on-chip generic DMA requestor.1471 */1472#define DMA_RQ_C1_COUNT_MASK 0x000003FF1473#define DMA_RQ_C1_DESTINATION_SCATTER 0x000010001474#define DMA_RQ_C1_SOURCE_GATHER 0x000020001475#define DMA_RQ_C1_DONE_FLAG 0x000040001476#define DMA_RQ_C1_OPTIMIZE_STATE 0x000080001477#define DMA_RQ_C1_SAMPLE_END_STATE_MASK 0x000300001478#define DMA_RQ_C1_FULL_PAGE 0x000000001479#define DMA_RQ_C1_BEFORE_SAMPLE_END 0x000100001480#define DMA_RQ_C1_PAGE_MAP_ERROR 0x000200001481#define DMA_RQ_C1_AT_SAMPLE_END 0x000300001482#define DMA_RQ_C1_LOOP_END_STATE_MASK 0x000C00001483#define DMA_RQ_C1_NOT_LOOP_END 0x000000001484#define DMA_RQ_C1_BEFORE_LOOP_END 0x000400001485#define DMA_RQ_C1_2PAGE_LOOP_BEGIN 0x000800001486#define DMA_RQ_C1_LOOP_BEGIN 0x000C00001487#define DMA_RQ_C1_PAGE_MAP_MASK 0x003000001488#define DMA_RQ_C1_PM_NONE_PENDING 0x000000001489#define DMA_RQ_C1_PM_NEXT_PENDING 0x001000001490#define DMA_RQ_C1_PM_RESERVED 0x002000001491#define DMA_RQ_C1_PM_LOOP_NEXT_PENDING 0x003000001492#define DMA_RQ_C1_WRITEBACK_DEST_FLAG 0x004000001493#define DMA_RQ_C1_WRITEBACK_SRC_FLAG 0x008000001494#define DMA_RQ_C1_DEST_SIZE_MASK 0x070000001495#define DMA_RQ_C1_DEST_LINEAR 0x000000001496#define DMA_RQ_C1_DEST_MOD16 0x010000001497#define DMA_RQ_C1_DEST_MOD32 0x020000001498#define DMA_RQ_C1_DEST_MOD64 0x030000001499#define DMA_RQ_C1_DEST_MOD128 0x040000001500#define DMA_RQ_C1_DEST_MOD256 0x050000001501#define DMA_RQ_C1_DEST_MOD512 0x060000001502#define DMA_RQ_C1_DEST_MOD1024 0x070000001503#define DMA_RQ_C1_DEST_ON_HOST 0x080000001504#define DMA_RQ_C1_SOURCE_SIZE_MASK 0x700000001505#define DMA_RQ_C1_SOURCE_LINEAR 0x000000001506#define DMA_RQ_C1_SOURCE_MOD16 0x100000001507#define DMA_RQ_C1_SOURCE_MOD32 0x200000001508#define DMA_RQ_C1_SOURCE_MOD64 0x300000001509#define DMA_RQ_C1_SOURCE_MOD128 0x400000001510#define DMA_RQ_C1_SOURCE_MOD256 0x500000001511#define DMA_RQ_C1_SOURCE_MOD512 0x600000001512#define DMA_RQ_C1_SOURCE_MOD1024 0x700000001513#define DMA_RQ_C1_SOURCE_ON_HOST 0x800000001514#define DMA_RQ_C1_COUNT_SHIFT 01515 1516/*1517 * The following defines are for the flags in the second control word of the1518 * on-chip generic DMA requestor.1519 */1520#define DMA_RQ_C2_VIRTUAL_CHANNEL_MASK 0x0000003F1521#define DMA_RQ_C2_VIRTUAL_SIGNAL_MASK 0x000003001522#define DMA_RQ_C2_NO_VIRTUAL_SIGNAL 0x000000001523#define DMA_RQ_C2_SIGNAL_EVERY_DMA 0x000001001524#define DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG 0x000002001525#define DMA_RQ_C2_SIGNAL_DEST_PINGPONG 0x000003001526#define DMA_RQ_C2_AUDIO_CONVERT_MASK 0x0000F0001527#define DMA_RQ_C2_AC_NONE 0x000000001528#define DMA_RQ_C2_AC_8_TO_16_BIT 0x000010001529#define DMA_RQ_C2_AC_MONO_TO_STEREO 0x000020001530#define DMA_RQ_C2_AC_ENDIAN_CONVERT 0x000040001531#define DMA_RQ_C2_AC_SIGNED_CONVERT 0x000080001532#define DMA_RQ_C2_LOOP_END_MASK 0x0FFF00001533#define DMA_RQ_C2_LOOP_MASK 0x300000001534#define DMA_RQ_C2_NO_LOOP 0x000000001535#define DMA_RQ_C2_ONE_PAGE_LOOP 0x100000001536#define DMA_RQ_C2_TWO_PAGE_LOOP 0x200000001537#define DMA_RQ_C2_MULTI_PAGE_LOOP 0x300000001538#define DMA_RQ_C2_SIGNAL_LOOP_BACK 0x400000001539#define DMA_RQ_C2_SIGNAL_POST_BEGIN_PAGE 0x800000001540#define DMA_RQ_C2_VIRTUAL_CHANNEL_SHIFT 01541#define DMA_RQ_C2_LOOP_END_SHIFT 161542 1543/*1544 * The following defines are for the flags in the source and destination words1545 * of the on-chip generic DMA requestor.1546 */1547#define DMA_RQ_SD_ADDRESS_MASK 0x0000FFFF1548#define DMA_RQ_SD_MEMORY_ID_MASK 0x000F00001549#define DMA_RQ_SD_SP_PARAM_ADDR 0x000000001550#define DMA_RQ_SD_SP_SAMPLE_ADDR 0x000100001551#define DMA_RQ_SD_SP_PROGRAM_ADDR 0x000200001552#define DMA_RQ_SD_SP_DEBUG_ADDR 0x000300001553#define DMA_RQ_SD_OMNIMEM_ADDR 0x000E00001554#define DMA_RQ_SD_END_FLAG 0x400000001555#define DMA_RQ_SD_ERROR_FLAG 0x800000001556#define DMA_RQ_SD_ADDRESS_SHIFT 01557 1558/*1559 * The following defines are for the flags in the page map address word of the1560 * on-chip generic DMA requestor.1561 */1562#define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_MASK 0x00000FF81563#define DMA_RQ_PMA_PAGE_TABLE_MASK 0xFFFFF0001564#define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_SHIFT 31565#define DMA_RQ_PMA_PAGE_TABLE_SHIFT 121566 1567#define BA1_VARIDEC_BUF_1 0x0001568 1569#define BA1_PDTC 0x0c0 /* BA1_PLAY_DMA_TRANSACTION_COUNT_REG */1570#define BA1_PFIE 0x0c4 /* BA1_PLAY_FORMAT_&_INTERRUPT_ENABLE_REG */1571#define BA1_PBA 0x0c8 /* BA1_PLAY_BUFFER_ADDRESS */1572#define BA1_PVOL 0x0f8 /* BA1_PLAY_VOLUME_REG */1573#define BA1_PSRC 0x288 /* BA1_PLAY_SAMPLE_RATE_CORRECTION_REG */1574#define BA1_PCTL 0x2a4 /* BA1_PLAY_CONTROL_REG */1575#define BA1_PPI 0x2b4 /* BA1_PLAY_PHASE_INCREMENT_REG */1576 1577#define BA1_CCTL 0x064 /* BA1_CAPTURE_CONTROL_REG */1578#define BA1_CIE 0x104 /* BA1_CAPTURE_INTERRUPT_ENABLE_REG */1579#define BA1_CBA 0x10c /* BA1_CAPTURE_BUFFER_ADDRESS */1580#define BA1_CSRC 0x2c8 /* BA1_CAPTURE_SAMPLE_RATE_CORRECTION_REG */1581#define BA1_CCI 0x2d8 /* BA1_CAPTURE_COEFFICIENT_INCREMENT_REG */1582#define BA1_CD 0x2e0 /* BA1_CAPTURE_DELAY_REG */1583#define BA1_CPI 0x2f4 /* BA1_CAPTURE_PHASE_INCREMENT_REG */1584#define BA1_CVOL 0x2f8 /* BA1_CAPTURE_VOLUME_REG */1585 1586#define BA1_CFG1 0x134 /* BA1_CAPTURE_FRAME_GROUP_1_REG */1587#define BA1_CFG2 0x138 /* BA1_CAPTURE_FRAME_GROUP_2_REG */1588#define BA1_CCST 0x13c /* BA1_CAPTURE_CONSTANT_REG */1589#define BA1_CSPB 0x340 /* BA1_CAPTURE_SPB_ADDRESS */1590 1591/*1592 *1593 */1594 1595#define CS46XX_MODE_OUTPUT (1<<0) /* MIDI UART - output */ 1596#define CS46XX_MODE_INPUT (1<<1) /* MIDI UART - input */1597 1598/*1599 *1600 */1601 1602#define SAVE_REG_MAX 0x101603#define POWER_DOWN_ALL 0x7f0f1604 1605/* maxinum number of AC97 codecs connected, AC97 2.0 defined 4 */1606#define MAX_NR_AC97 41607#define CS46XX_PRIMARY_CODEC_INDEX 01608#define CS46XX_SECONDARY_CODEC_INDEX 11609#define CS46XX_SECONDARY_CODEC_OFFSET 0x801610#define CS46XX_DSP_CAPTURE_CHANNEL 11611 1612/* capture */1613#define CS46XX_DSP_CAPTURE_CHANNEL 11614 1615/* mixer */1616#define CS46XX_MIXER_SPDIF_INPUT_ELEMENT 11617#define CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT 21618 1619 1620struct snd_cs46xx_pcm {1621 struct snd_dma_buffer hw_buf;1622 1623 unsigned int ctl;1624 unsigned int shift; /* Shift count to trasform frames in bytes */1625 struct snd_pcm_indirect pcm_rec;1626 struct snd_pcm_substream *substream;1627 1628 struct dsp_pcm_channel_descriptor * pcm_channel;1629 1630 int pcm_channel_id; /* Fron Rear, Center Lfe ... */1631};1632 1633struct snd_cs46xx_region {1634 char name[24];1635 unsigned long base;1636 void __iomem *remap_addr;1637 unsigned long size;1638};1639 1640struct snd_cs46xx {1641 int irq;1642 unsigned long ba0_addr;1643 unsigned long ba1_addr;1644 union {1645 struct {1646 struct snd_cs46xx_region ba0;1647 struct snd_cs46xx_region data0;1648 struct snd_cs46xx_region data1;1649 struct snd_cs46xx_region pmem;1650 struct snd_cs46xx_region reg;1651 } name;1652 struct snd_cs46xx_region idx[5];1653 } region;1654 1655 unsigned int mode;1656 1657 struct {1658 struct snd_dma_buffer hw_buf;1659 1660 unsigned int ctl;1661 unsigned int shift; /* Shift count to trasform frames in bytes */1662 struct snd_pcm_indirect pcm_rec;1663 struct snd_pcm_substream *substream;1664 } capt;1665 1666 1667 int nr_ac97_codecs;1668 struct snd_ac97_bus *ac97_bus;1669 struct snd_ac97 *ac97[MAX_NR_AC97];1670 1671 struct pci_dev *pci;1672 struct snd_card *card;1673 struct snd_pcm *pcm;1674 1675 struct snd_rawmidi *rmidi;1676 struct snd_rawmidi_substream *midi_input;1677 struct snd_rawmidi_substream *midi_output;1678 1679 spinlock_t reg_lock;1680 unsigned int midcr;1681 unsigned int uartm;1682 1683 int amplifier;1684 void (*amplifier_ctrl)(struct snd_cs46xx *, int);1685 void (*active_ctrl)(struct snd_cs46xx *, int);1686 void (*mixer_init)(struct snd_cs46xx *);1687 1688 int acpi_port;1689 struct snd_kcontrol *eapd_switch; /* for amplifier hack */1690 int accept_valid; /* accept mmap valid (for OSS) */1691 int in_suspend;1692 1693 struct gameport *gameport;1694 1695#ifdef CONFIG_SND_CS46XX_NEW_DSP1696 struct mutex spos_mutex;1697 1698 struct dsp_spos_instance * dsp_spos_instance;1699 1700 struct snd_pcm *pcm_rear;1701 struct snd_pcm *pcm_center_lfe;1702 struct snd_pcm *pcm_iec958;1703 1704#define CS46XX_DSP_MODULES 51705 struct dsp_module_desc *modules[CS46XX_DSP_MODULES];1706#else /* for compatibility */1707 struct snd_cs46xx_pcm *playback_pcm;1708 unsigned int play_ctl;1709 1710 struct ba1_struct *ba1;1711#endif1712 1713#ifdef CONFIG_PM_SLEEP1714 u32 *saved_regs;1715#endif1716};1717 1718int snd_cs46xx_create(struct snd_card *card,1719 struct pci_dev *pci,1720 int external_amp, int thinkpad);1721extern const struct dev_pm_ops snd_cs46xx_pm;1722 1723int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device);1724int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device);1725int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device);1726int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device);1727int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device);1728int snd_cs46xx_midi(struct snd_cs46xx *chip, int device);1729int snd_cs46xx_start_dsp(struct snd_cs46xx *chip);1730int snd_cs46xx_gameport(struct snd_cs46xx *chip);1731 1732#endif /* __SOUND_CS46XX_H */1733