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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * HD audio interface patch for Creative CA0132 chip.4 * CA0132 registers defines.5 *6 * Copyright (c) 2011, Creative Technology Ltd.7 */8 9#ifndef __CA0132_REGS_H10#define __CA0132_REGS_H11 12#define DSP_CHIP_OFFSET 0x10000013#define DSP_DBGCNTL_MODULE_OFFSET 0xE3014#define DSP_DBGCNTL_INST_OFFSET \15 (DSP_CHIP_OFFSET + DSP_DBGCNTL_MODULE_OFFSET)16 17#define DSP_DBGCNTL_EXEC_LOBIT 0x018#define DSP_DBGCNTL_EXEC_HIBIT 0x319#define DSP_DBGCNTL_EXEC_MASK 0xF20 21#define DSP_DBGCNTL_SS_LOBIT 0x422#define DSP_DBGCNTL_SS_HIBIT 0x723#define DSP_DBGCNTL_SS_MASK 0xF024 25#define DSP_DBGCNTL_STATE_LOBIT 0xA26#define DSP_DBGCNTL_STATE_HIBIT 0xD27#define DSP_DBGCNTL_STATE_MASK 0x3C0028 29#define XRAM_CHIP_OFFSET 0x030#define XRAM_XRAM_CHANNEL_COUNT 0xE00031#define XRAM_XRAM_MODULE_OFFSET 0x032#define XRAM_XRAM_CHAN_INCR 433#define XRAM_XRAM_INST_OFFSET(_chan) \34 (XRAM_CHIP_OFFSET + XRAM_XRAM_MODULE_OFFSET + \35 (_chan * XRAM_XRAM_CHAN_INCR))36 37#define YRAM_CHIP_OFFSET 0x4000038#define YRAM_YRAM_CHANNEL_COUNT 0x800039#define YRAM_YRAM_MODULE_OFFSET 0x040#define YRAM_YRAM_CHAN_INCR 441#define YRAM_YRAM_INST_OFFSET(_chan) \42 (YRAM_CHIP_OFFSET + YRAM_YRAM_MODULE_OFFSET + \43 (_chan * YRAM_YRAM_CHAN_INCR))44 45#define UC_CHIP_OFFSET 0x8000046#define UC_UC_CHANNEL_COUNT 0x1000047#define UC_UC_MODULE_OFFSET 0x048#define UC_UC_CHAN_INCR 449#define UC_UC_INST_OFFSET(_chan) \50 (UC_CHIP_OFFSET + UC_UC_MODULE_OFFSET + \51 (_chan * UC_UC_CHAN_INCR))52 53#define AXRAM_CHIP_OFFSET 0x3C00054#define AXRAM_AXRAM_CHANNEL_COUNT 0x100055#define AXRAM_AXRAM_MODULE_OFFSET 0x056#define AXRAM_AXRAM_CHAN_INCR 457#define AXRAM_AXRAM_INST_OFFSET(_chan) \58 (AXRAM_CHIP_OFFSET + AXRAM_AXRAM_MODULE_OFFSET + \59 (_chan * AXRAM_AXRAM_CHAN_INCR))60 61#define AYRAM_CHIP_OFFSET 0x7800062#define AYRAM_AYRAM_CHANNEL_COUNT 0x100063#define AYRAM_AYRAM_MODULE_OFFSET 0x064#define AYRAM_AYRAM_CHAN_INCR 465#define AYRAM_AYRAM_INST_OFFSET(_chan) \66 (AYRAM_CHIP_OFFSET + AYRAM_AYRAM_MODULE_OFFSET + \67 (_chan * AYRAM_AYRAM_CHAN_INCR))68 69#define DSPDMAC_CHIP_OFFSET 0x11000070#define DSPDMAC_DMA_CFG_CHANNEL_COUNT 1271#define DSPDMAC_DMACFG_MODULE_OFFSET 0xF0072#define DSPDMAC_DMACFG_CHAN_INCR 0x1073#define DSPDMAC_DMACFG_INST_OFFSET(_chan) \74 (DSPDMAC_CHIP_OFFSET + DSPDMAC_DMACFG_MODULE_OFFSET + \75 (_chan * DSPDMAC_DMACFG_CHAN_INCR))76 77#define DSPDMAC_DMACFG_DBADR_LOBIT 0x078#define DSPDMAC_DMACFG_DBADR_HIBIT 0x1079#define DSPDMAC_DMACFG_DBADR_MASK 0x1FFFF80#define DSPDMAC_DMACFG_LP_LOBIT 0x1181#define DSPDMAC_DMACFG_LP_HIBIT 0x1182#define DSPDMAC_DMACFG_LP_MASK 0x2000083 84#define DSPDMAC_DMACFG_AINCR_LOBIT 0x1285#define DSPDMAC_DMACFG_AINCR_HIBIT 0x1286#define DSPDMAC_DMACFG_AINCR_MASK 0x4000087 88#define DSPDMAC_DMACFG_DWR_LOBIT 0x1389#define DSPDMAC_DMACFG_DWR_HIBIT 0x1390#define DSPDMAC_DMACFG_DWR_MASK 0x8000091 92#define DSPDMAC_DMACFG_AJUMP_LOBIT 0x1493#define DSPDMAC_DMACFG_AJUMP_HIBIT 0x1794#define DSPDMAC_DMACFG_AJUMP_MASK 0xF0000095 96#define DSPDMAC_DMACFG_AMODE_LOBIT 0x1897#define DSPDMAC_DMACFG_AMODE_HIBIT 0x1998#define DSPDMAC_DMACFG_AMODE_MASK 0x300000099 100#define DSPDMAC_DMACFG_LK_LOBIT 0x1A101#define DSPDMAC_DMACFG_LK_HIBIT 0x1A102#define DSPDMAC_DMACFG_LK_MASK 0x4000000103 104#define DSPDMAC_DMACFG_AICS_LOBIT 0x1B105#define DSPDMAC_DMACFG_AICS_HIBIT 0x1F106#define DSPDMAC_DMACFG_AICS_MASK 0xF8000000107 108#define DSPDMAC_DMACFG_LP_SINGLE 0109#define DSPDMAC_DMACFG_LP_LOOPING 1110 111#define DSPDMAC_DMACFG_AINCR_XANDY 0112#define DSPDMAC_DMACFG_AINCR_XORY 1113 114#define DSPDMAC_DMACFG_DWR_DMA_RD 0115#define DSPDMAC_DMACFG_DWR_DMA_WR 1116 117#define DSPDMAC_DMACFG_AMODE_LINEAR 0118#define DSPDMAC_DMACFG_AMODE_RSV1 1119#define DSPDMAC_DMACFG_AMODE_WINTLV 2120#define DSPDMAC_DMACFG_AMODE_GINTLV 3121 122#define DSPDMAC_DSP_ADR_OFS_CHANNEL_COUNT 12123#define DSPDMAC_DSPADROFS_MODULE_OFFSET 0xF04124#define DSPDMAC_DSPADROFS_CHAN_INCR 0x10125#define DSPDMAC_DSPADROFS_INST_OFFSET(_chan) \126 (DSPDMAC_CHIP_OFFSET + DSPDMAC_DSPADROFS_MODULE_OFFSET + \127 (_chan * DSPDMAC_DSPADROFS_CHAN_INCR))128 129#define DSPDMAC_DSPADROFS_COFS_LOBIT 0x0130#define DSPDMAC_DSPADROFS_COFS_HIBIT 0xF131#define DSPDMAC_DSPADROFS_COFS_MASK 0xFFFF132 133#define DSPDMAC_DSPADROFS_BOFS_LOBIT 0x10134#define DSPDMAC_DSPADROFS_BOFS_HIBIT 0x1F135#define DSPDMAC_DSPADROFS_BOFS_MASK 0xFFFF0000136 137#define DSPDMAC_DSP_ADR_WOFS_CHANNEL_COUNT 12138#define DSPDMAC_DSPADRWOFS_MODULE_OFFSET 0xF04139#define DSPDMAC_DSPADRWOFS_CHAN_INCR 0x10140 141#define DSPDMAC_DSPADRWOFS_INST_OFFSET(_chan) \142 (DSPDMAC_CHIP_OFFSET + DSPDMAC_DSPADRWOFS_MODULE_OFFSET + \143 (_chan * DSPDMAC_DSPADRWOFS_CHAN_INCR))144 145#define DSPDMAC_DSPADRWOFS_WCOFS_LOBIT 0x0146#define DSPDMAC_DSPADRWOFS_WCOFS_HIBIT 0xA147#define DSPDMAC_DSPADRWOFS_WCOFS_MASK 0x7FF148 149#define DSPDMAC_DSPADRWOFS_WCBFR_LOBIT 0xB150#define DSPDMAC_DSPADRWOFS_WCBFR_HIBIT 0xF151#define DSPDMAC_DSPADRWOFS_WCBFR_MASK 0xF800152 153#define DSPDMAC_DSPADRWOFS_WBOFS_LOBIT 0x10154#define DSPDMAC_DSPADRWOFS_WBOFS_HIBIT 0x1A155#define DSPDMAC_DSPADRWOFS_WBOFS_MASK 0x7FF0000156 157#define DSPDMAC_DSPADRWOFS_WBBFR_LOBIT 0x1B158#define DSPDMAC_DSPADRWOFS_WBBFR_HIBIT 0x1F159#define DSPDMAC_DSPADRWOFS_WBBFR_MASK 0xF8000000160 161#define DSPDMAC_DSP_ADR_GOFS_CHANNEL_COUNT 12162#define DSPDMAC_DSPADRGOFS_MODULE_OFFSET 0xF04163#define DSPDMAC_DSPADRGOFS_CHAN_INCR 0x10164#define DSPDMAC_DSPADRGOFS_INST_OFFSET(_chan) \165 (DSPDMAC_CHIP_OFFSET + DSPDMAC_DSPADRGOFS_MODULE_OFFSET + \166 (_chan * DSPDMAC_DSPADRGOFS_CHAN_INCR))167 168#define DSPDMAC_DSPADRGOFS_GCOFS_LOBIT 0x0169#define DSPDMAC_DSPADRGOFS_GCOFS_HIBIT 0x9170#define DSPDMAC_DSPADRGOFS_GCOFS_MASK 0x3FF171 172#define DSPDMAC_DSPADRGOFS_GCS_LOBIT 0xA173#define DSPDMAC_DSPADRGOFS_GCS_HIBIT 0xC174#define DSPDMAC_DSPADRGOFS_GCS_MASK 0x1C00175 176#define DSPDMAC_DSPADRGOFS_GCBFR_LOBIT 0xD177#define DSPDMAC_DSPADRGOFS_GCBFR_HIBIT 0xF178#define DSPDMAC_DSPADRGOFS_GCBFR_MASK 0xE000179 180#define DSPDMAC_DSPADRGOFS_GBOFS_LOBIT 0x10181#define DSPDMAC_DSPADRGOFS_GBOFS_HIBIT 0x19182#define DSPDMAC_DSPADRGOFS_GBOFS_MASK 0x3FF0000183 184#define DSPDMAC_DSPADRGOFS_GBS_LOBIT 0x1A185#define DSPDMAC_DSPADRGOFS_GBS_HIBIT 0x1C186#define DSPDMAC_DSPADRGOFS_GBS_MASK 0x1C000000187 188#define DSPDMAC_DSPADRGOFS_GBBFR_LOBIT 0x1D189#define DSPDMAC_DSPADRGOFS_GBBFR_HIBIT 0x1F190#define DSPDMAC_DSPADRGOFS_GBBFR_MASK 0xE0000000191 192#define DSPDMAC_XFR_CNT_CHANNEL_COUNT 12193#define DSPDMAC_XFRCNT_MODULE_OFFSET 0xF08194#define DSPDMAC_XFRCNT_CHAN_INCR 0x10195 196#define DSPDMAC_XFRCNT_INST_OFFSET(_chan) \197 (DSPDMAC_CHIP_OFFSET + DSPDMAC_XFRCNT_MODULE_OFFSET + \198 (_chan * DSPDMAC_XFRCNT_CHAN_INCR))199 200#define DSPDMAC_XFRCNT_CCNT_LOBIT 0x0201#define DSPDMAC_XFRCNT_CCNT_HIBIT 0xF202#define DSPDMAC_XFRCNT_CCNT_MASK 0xFFFF203 204#define DSPDMAC_XFRCNT_BCNT_LOBIT 0x10205#define DSPDMAC_XFRCNT_BCNT_HIBIT 0x1F206#define DSPDMAC_XFRCNT_BCNT_MASK 0xFFFF0000207 208#define DSPDMAC_IRQ_CNT_CHANNEL_COUNT 12209#define DSPDMAC_IRQCNT_MODULE_OFFSET 0xF0C210#define DSPDMAC_IRQCNT_CHAN_INCR 0x10211#define DSPDMAC_IRQCNT_INST_OFFSET(_chan) \212 (DSPDMAC_CHIP_OFFSET + DSPDMAC_IRQCNT_MODULE_OFFSET + \213 (_chan * DSPDMAC_IRQCNT_CHAN_INCR))214 215#define DSPDMAC_IRQCNT_CICNT_LOBIT 0x0216#define DSPDMAC_IRQCNT_CICNT_HIBIT 0xF217#define DSPDMAC_IRQCNT_CICNT_MASK 0xFFFF218 219#define DSPDMAC_IRQCNT_BICNT_LOBIT 0x10220#define DSPDMAC_IRQCNT_BICNT_HIBIT 0x1F221#define DSPDMAC_IRQCNT_BICNT_MASK 0xFFFF0000222 223#define DSPDMAC_AUD_CHSEL_CHANNEL_COUNT 12224#define DSPDMAC_AUDCHSEL_MODULE_OFFSET 0xFC0225#define DSPDMAC_AUDCHSEL_CHAN_INCR 0x4226#define DSPDMAC_AUDCHSEL_INST_OFFSET(_chan) \227 (DSPDMAC_CHIP_OFFSET + DSPDMAC_AUDCHSEL_MODULE_OFFSET + \228 (_chan * DSPDMAC_AUDCHSEL_CHAN_INCR))229 230#define DSPDMAC_AUDCHSEL_ACS_LOBIT 0x0231#define DSPDMAC_AUDCHSEL_ACS_HIBIT 0x1F232#define DSPDMAC_AUDCHSEL_ACS_MASK 0xFFFFFFFF233 234#define DSPDMAC_CHNLSTART_MODULE_OFFSET 0xFF0235#define DSPDMAC_CHNLSTART_INST_OFFSET \236 (DSPDMAC_CHIP_OFFSET + DSPDMAC_CHNLSTART_MODULE_OFFSET)237 238#define DSPDMAC_CHNLSTART_EN_LOBIT 0x0239#define DSPDMAC_CHNLSTART_EN_HIBIT 0xB240#define DSPDMAC_CHNLSTART_EN_MASK 0xFFF241 242#define DSPDMAC_CHNLSTART_VAI1_LOBIT 0xC243#define DSPDMAC_CHNLSTART_VAI1_HIBIT 0xF244#define DSPDMAC_CHNLSTART_VAI1_MASK 0xF000245 246#define DSPDMAC_CHNLSTART_DIS_LOBIT 0x10247#define DSPDMAC_CHNLSTART_DIS_HIBIT 0x1B248#define DSPDMAC_CHNLSTART_DIS_MASK 0xFFF0000249 250#define DSPDMAC_CHNLSTART_VAI2_LOBIT 0x1C251#define DSPDMAC_CHNLSTART_VAI2_HIBIT 0x1F252#define DSPDMAC_CHNLSTART_VAI2_MASK 0xF0000000253 254#define DSPDMAC_CHNLSTATUS_MODULE_OFFSET 0xFF4255#define DSPDMAC_CHNLSTATUS_INST_OFFSET \256 (DSPDMAC_CHIP_OFFSET + DSPDMAC_CHNLSTATUS_MODULE_OFFSET)257 258#define DSPDMAC_CHNLSTATUS_ISC_LOBIT 0x0259#define DSPDMAC_CHNLSTATUS_ISC_HIBIT 0xB260#define DSPDMAC_CHNLSTATUS_ISC_MASK 0xFFF261 262#define DSPDMAC_CHNLSTATUS_AOO_LOBIT 0xC263#define DSPDMAC_CHNLSTATUS_AOO_HIBIT 0xC264#define DSPDMAC_CHNLSTATUS_AOO_MASK 0x1000265 266#define DSPDMAC_CHNLSTATUS_AOU_LOBIT 0xD267#define DSPDMAC_CHNLSTATUS_AOU_HIBIT 0xD268#define DSPDMAC_CHNLSTATUS_AOU_MASK 0x2000269 270#define DSPDMAC_CHNLSTATUS_AIO_LOBIT 0xE271#define DSPDMAC_CHNLSTATUS_AIO_HIBIT 0xE272#define DSPDMAC_CHNLSTATUS_AIO_MASK 0x4000273 274#define DSPDMAC_CHNLSTATUS_AIU_LOBIT 0xF275#define DSPDMAC_CHNLSTATUS_AIU_HIBIT 0xF276#define DSPDMAC_CHNLSTATUS_AIU_MASK 0x8000277 278#define DSPDMAC_CHNLSTATUS_IEN_LOBIT 0x10279#define DSPDMAC_CHNLSTATUS_IEN_HIBIT 0x1B280#define DSPDMAC_CHNLSTATUS_IEN_MASK 0xFFF0000281 282#define DSPDMAC_CHNLSTATUS_VAI0_LOBIT 0x1C283#define DSPDMAC_CHNLSTATUS_VAI0_HIBIT 0x1F284#define DSPDMAC_CHNLSTATUS_VAI0_MASK 0xF0000000285 286#define DSPDMAC_CHNLPROP_MODULE_OFFSET 0xFF8287#define DSPDMAC_CHNLPROP_INST_OFFSET \288 (DSPDMAC_CHIP_OFFSET + DSPDMAC_CHNLPROP_MODULE_OFFSET)289 290#define DSPDMAC_CHNLPROP_DCON_LOBIT 0x0291#define DSPDMAC_CHNLPROP_DCON_HIBIT 0xB292#define DSPDMAC_CHNLPROP_DCON_MASK 0xFFF293 294#define DSPDMAC_CHNLPROP_FFS_LOBIT 0xC295#define DSPDMAC_CHNLPROP_FFS_HIBIT 0xC296#define DSPDMAC_CHNLPROP_FFS_MASK 0x1000297 298#define DSPDMAC_CHNLPROP_NAJ_LOBIT 0xD299#define DSPDMAC_CHNLPROP_NAJ_HIBIT 0xD300#define DSPDMAC_CHNLPROP_NAJ_MASK 0x2000301 302#define DSPDMAC_CHNLPROP_ENH_LOBIT 0xE303#define DSPDMAC_CHNLPROP_ENH_HIBIT 0xE304#define DSPDMAC_CHNLPROP_ENH_MASK 0x4000305 306#define DSPDMAC_CHNLPROP_MSPCE_LOBIT 0x10307#define DSPDMAC_CHNLPROP_MSPCE_HIBIT 0x1B308#define DSPDMAC_CHNLPROP_MSPCE_MASK 0xFFF0000309 310#define DSPDMAC_CHNLPROP_AC_LOBIT 0x1C311#define DSPDMAC_CHNLPROP_AC_HIBIT 0x1F312#define DSPDMAC_CHNLPROP_AC_MASK 0xF0000000313 314#define DSPDMAC_ACTIVE_MODULE_OFFSET 0xFFC315#define DSPDMAC_ACTIVE_INST_OFFSET \316 (DSPDMAC_CHIP_OFFSET + DSPDMAC_ACTIVE_MODULE_OFFSET)317 318#define DSPDMAC_ACTIVE_AAR_LOBIT 0x0319#define DSPDMAC_ACTIVE_AAR_HIBIT 0xB320#define DSPDMAC_ACTIVE_AAR_MASK 0xFFF321 322#define DSPDMAC_ACTIVE_WFR_LOBIT 0xC323#define DSPDMAC_ACTIVE_WFR_HIBIT 0x17324#define DSPDMAC_ACTIVE_WFR_MASK 0xFFF000325 326#define DSP_AUX_MEM_BASE 0xE000327#define INVALID_CHIP_ADDRESS (~0U)328 329#define X_SIZE (XRAM_XRAM_CHANNEL_COUNT * XRAM_XRAM_CHAN_INCR)330#define Y_SIZE (YRAM_YRAM_CHANNEL_COUNT * YRAM_YRAM_CHAN_INCR)331#define AX_SIZE (AXRAM_AXRAM_CHANNEL_COUNT * AXRAM_AXRAM_CHAN_INCR)332#define AY_SIZE (AYRAM_AYRAM_CHANNEL_COUNT * AYRAM_AYRAM_CHAN_INCR)333#define UC_SIZE (UC_UC_CHANNEL_COUNT * UC_UC_CHAN_INCR)334 335#define XEXT_SIZE (X_SIZE + AX_SIZE)336#define YEXT_SIZE (Y_SIZE + AY_SIZE)337 338#define U64K 0x10000UL339 340#define X_END (XRAM_CHIP_OFFSET + X_SIZE)341#define X_EXT (XRAM_CHIP_OFFSET + XEXT_SIZE)342#define AX_END (XRAM_CHIP_OFFSET + U64K*4)343 344#define Y_END (YRAM_CHIP_OFFSET + Y_SIZE)345#define Y_EXT (YRAM_CHIP_OFFSET + YEXT_SIZE)346#define AY_END (YRAM_CHIP_OFFSET + U64K*4)347 348#define UC_END (UC_CHIP_OFFSET + UC_SIZE)349 350#define X_RANGE_MAIN(a, s) \351 (((a)+((s)-1)*XRAM_XRAM_CHAN_INCR < X_END))352#define X_RANGE_AUX(a, s) \353 (((a) >= X_END) && ((a)+((s)-1)*XRAM_XRAM_CHAN_INCR < AX_END))354#define X_RANGE_EXT(a, s) \355 (((a)+((s)-1)*XRAM_XRAM_CHAN_INCR < X_EXT))356#define X_RANGE_ALL(a, s) \357 (((a)+((s)-1)*XRAM_XRAM_CHAN_INCR < AX_END))358 359#define Y_RANGE_MAIN(a, s) \360 (((a) >= YRAM_CHIP_OFFSET) && \361 ((a)+((s)-1)*YRAM_YRAM_CHAN_INCR < Y_END))362#define Y_RANGE_AUX(a, s) \363 (((a) >= Y_END) && \364 ((a)+((s)-1)*YRAM_YRAM_CHAN_INCR < AY_END))365#define Y_RANGE_EXT(a, s) \366 (((a) >= YRAM_CHIP_OFFSET) && \367 ((a)+((s)-1)*YRAM_YRAM_CHAN_INCR < Y_EXT))368#define Y_RANGE_ALL(a, s) \369 (((a) >= YRAM_CHIP_OFFSET) && \370 ((a)+((s)-1)*YRAM_YRAM_CHAN_INCR < AY_END))371 372#define UC_RANGE(a, s) \373 (((a) >= UC_CHIP_OFFSET) && \374 ((a)+((s)-1)*UC_UC_CHAN_INCR < UC_END))375 376#define X_OFF(a) \377 (((a) - XRAM_CHIP_OFFSET) / XRAM_XRAM_CHAN_INCR)378#define AX_OFF(a) \379 (((a) % (AXRAM_AXRAM_CHANNEL_COUNT * \380 AXRAM_AXRAM_CHAN_INCR)) / AXRAM_AXRAM_CHAN_INCR)381 382#define Y_OFF(a) \383 (((a) - YRAM_CHIP_OFFSET) / YRAM_YRAM_CHAN_INCR)384#define AY_OFF(a) \385 (((a) % (AYRAM_AYRAM_CHANNEL_COUNT * \386 AYRAM_AYRAM_CHAN_INCR)) / AYRAM_AYRAM_CHAN_INCR)387 388#define UC_OFF(a) (((a) - UC_CHIP_OFFSET) / UC_UC_CHAN_INCR)389 390#define X_EXT_MAIN_SIZE(a) (XRAM_XRAM_CHANNEL_COUNT - X_OFF(a))391#define X_EXT_AUX_SIZE(a, s) ((s) - X_EXT_MAIN_SIZE(a))392 393#define Y_EXT_MAIN_SIZE(a) (YRAM_YRAM_CHANNEL_COUNT - Y_OFF(a))394#define Y_EXT_AUX_SIZE(a, s) ((s) - Y_EXT_MAIN_SIZE(a))395 396#endif397