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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 *4 *  hda_intel.c - Implementation of primary alsa driver code base5 *                for Intel HD Audio.6 *7 *  Copyright(c) 2004 Intel Corporation8 *9 *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>10 *                     PeiSen Hou <pshou@realtek.com.tw>11 *12 *  CONTACTS:13 *14 *  Matt Jared		matt.jared@intel.com15 *  Andy Kopp		andy.kopp@intel.com16 *  Dan Kogan		dan.d.kogan@intel.com17 *18 *  CHANGES:19 *20 *  2004.12.01	Major rewrite by tiwai, merged the work of pshou21 */22 23#include <linux/delay.h>24#include <linux/interrupt.h>25#include <linux/kernel.h>26#include <linux/module.h>27#include <linux/dma-mapping.h>28#include <linux/moduleparam.h>29#include <linux/init.h>30#include <linux/slab.h>31#include <linux/pci.h>32#include <linux/mutex.h>33#include <linux/io.h>34#include <linux/pm_runtime.h>35#include <linux/clocksource.h>36#include <linux/time.h>37#include <linux/completion.h>38#include <linux/acpi.h>39#include <linux/pgtable.h>40 41#ifdef CONFIG_X8642/* for snoop control */43#include <asm/set_memory.h>44#include <asm/cpufeature.h>45#endif46#include <sound/core.h>47#include <sound/initval.h>48#include <sound/hdaudio.h>49#include <sound/hda_i915.h>50#include <sound/intel-dsp-config.h>51#include <linux/vgaarb.h>52#include <linux/vga_switcheroo.h>53#include <linux/apple-gmux.h>54#include <linux/firmware.h>55#include <sound/hda_codec.h>56#include "hda_controller.h"57#include "hda_intel.h"58 59#define CREATE_TRACE_POINTS60#include "hda_intel_trace.h"61 62/* position fix mode */63enum {64	POS_FIX_AUTO,65	POS_FIX_LPIB,66	POS_FIX_POSBUF,67	POS_FIX_VIACOMBO,68	POS_FIX_COMBO,69	POS_FIX_SKL,70	POS_FIX_FIFO,71};72 73/* Defines for ATI HD Audio support in SB450 south bridge */74#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x4275#define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x0276 77/* Defines for Nvidia HDA support */78#define NVIDIA_HDA_TRANSREG_ADDR      0x4e79#define NVIDIA_HDA_ENABLE_COHBITS     0x0f80#define NVIDIA_HDA_ISTRM_COH          0x4d81#define NVIDIA_HDA_OSTRM_COH          0x4c82#define NVIDIA_HDA_ENABLE_COHBIT      0x0183 84/* Defines for Intel SCH HDA snoop control */85#define INTEL_HDA_CGCTL	 0x4886#define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)87#define INTEL_SCH_HDA_DEVC      0x7888#define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)89 90/* max number of SDs */91/* ICH, ATI and VIA have 4 playback and 4 capture */92#define ICH6_NUM_CAPTURE	493#define ICH6_NUM_PLAYBACK	494 95/* ULI has 6 playback and 5 capture */96#define ULI_NUM_CAPTURE		597#define ULI_NUM_PLAYBACK	698 99/* ATI HDMI may have up to 8 playbacks and 0 capture */100#define ATIHDMI_NUM_CAPTURE	0101#define ATIHDMI_NUM_PLAYBACK	8102 103 104static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;105static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;106static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;107static char *model[SNDRV_CARDS];108static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};109static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};110static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};111static int probe_only[SNDRV_CARDS];112static int jackpoll_ms[SNDRV_CARDS];113static int single_cmd = -1;114static int enable_msi = -1;115#ifdef CONFIG_SND_HDA_PATCH_LOADER116static char *patch[SNDRV_CARDS];117#endif118#ifdef CONFIG_SND_HDA_INPUT_BEEP119static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =120					CONFIG_SND_HDA_INPUT_BEEP_MODE};121#endif122static bool dmic_detect = 1;123static bool ctl_dev_id = IS_ENABLED(CONFIG_SND_HDA_CTL_DEV_ID) ? 1 : 0;124 125module_param_array(index, int, NULL, 0444);126MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");127module_param_array(id, charp, NULL, 0444);128MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");129module_param_array(enable, bool, NULL, 0444);130MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");131module_param_array(model, charp, NULL, 0444);132MODULE_PARM_DESC(model, "Use the given board model.");133module_param_array(position_fix, int, NULL, 0444);134MODULE_PARM_DESC(position_fix, "DMA pointer read method."135		 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");136module_param_array(bdl_pos_adj, int, NULL, 0644);137MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");138module_param_array(probe_mask, int, NULL, 0444);139MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");140module_param_array(probe_only, int, NULL, 0444);141MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");142module_param_array(jackpoll_ms, int, NULL, 0444);143MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");144module_param(single_cmd, bint, 0444);145MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "146		 "(for debugging only).");147module_param(enable_msi, bint, 0444);148MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");149#ifdef CONFIG_SND_HDA_PATCH_LOADER150module_param_array(patch, charp, NULL, 0444);151MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");152#endif153#ifdef CONFIG_SND_HDA_INPUT_BEEP154module_param_array(beep_mode, bool, NULL, 0444);155MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "156			    "(0=off, 1=on) (default=1).");157#endif158module_param(dmic_detect, bool, 0444);159MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "160			     "(0=off, 1=on) (default=1); "161		 "deprecated, use snd-intel-dspcfg.dsp_driver option instead");162module_param(ctl_dev_id, bool, 0444);163MODULE_PARM_DESC(ctl_dev_id, "Use control device identifier (based on codec address).");164 165#ifdef CONFIG_PM166static int param_set_xint(const char *val, const struct kernel_param *kp);167static const struct kernel_param_ops param_ops_xint = {168	.set = param_set_xint,169	.get = param_get_int,170};171#define param_check_xint param_check_int172 173static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;174module_param(power_save, xint, 0644);175MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "176		 "(in second, 0 = disable).");177 178static int pm_blacklist = -1;179module_param(pm_blacklist, bint, 0644);180MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");181 182/* reset the HD-audio controller in power save mode.183 * this may give more power-saving, but will take longer time to184 * wake up.185 */186static bool power_save_controller = 1;187module_param(power_save_controller, bool, 0644);188MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");189#else /* CONFIG_PM */190#define power_save	0191#define pm_blacklist	0192#define power_save_controller	false193#endif /* CONFIG_PM */194 195static int align_buffer_size = -1;196module_param(align_buffer_size, bint, 0644);197MODULE_PARM_DESC(align_buffer_size,198		"Force buffer and period sizes to be multiple of 128 bytes.");199 200#ifdef CONFIG_X86201static int hda_snoop = -1;202module_param_named(snoop, hda_snoop, bint, 0444);203MODULE_PARM_DESC(snoop, "Enable/disable snooping");204#else205#define hda_snoop		true206#endif207 208 209MODULE_LICENSE("GPL");210MODULE_DESCRIPTION("Intel HDA driver");211 212#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)213#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)214#define SUPPORT_VGA_SWITCHEROO215#endif216#endif217 218 219/*220 */221 222/* driver types */223enum {224	AZX_DRIVER_ICH,225	AZX_DRIVER_PCH,226	AZX_DRIVER_SCH,227	AZX_DRIVER_SKL,228	AZX_DRIVER_HDMI,229	AZX_DRIVER_ATI,230	AZX_DRIVER_ATIHDMI,231	AZX_DRIVER_ATIHDMI_NS,232	AZX_DRIVER_GFHDMI,233	AZX_DRIVER_VIA,234	AZX_DRIVER_SIS,235	AZX_DRIVER_ULI,236	AZX_DRIVER_NVIDIA,237	AZX_DRIVER_TERA,238	AZX_DRIVER_CTX,239	AZX_DRIVER_CTHDA,240	AZX_DRIVER_CMEDIA,241	AZX_DRIVER_ZHAOXIN,242	AZX_DRIVER_LOONGSON,243	AZX_DRIVER_GENERIC,244	AZX_NUM_DRIVERS, /* keep this as last entry */245};246 247#define azx_get_snoop_type(chip) \248	(((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)249#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)250 251/* quirks for old Intel chipsets */252#define AZX_DCAPS_INTEL_ICH \253	(AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)254 255/* quirks for Intel PCH */256#define AZX_DCAPS_INTEL_PCH_BASE \257	(AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\258	 AZX_DCAPS_SNOOP_TYPE(SCH))259 260/* PCH up to IVB; no runtime PM; bind with i915 gfx */261#define AZX_DCAPS_INTEL_PCH_NOPM \262	(AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)263 264/* PCH for HSW/BDW; with runtime PM */265/* no i915 binding for this as HSW/BDW has another controller for HDMI */266#define AZX_DCAPS_INTEL_PCH \267	(AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)268 269/* HSW HDMI */270#define AZX_DCAPS_INTEL_HASWELL \271	(/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\272	 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\273	 AZX_DCAPS_SNOOP_TYPE(SCH))274 275/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */276#define AZX_DCAPS_INTEL_BROADWELL \277	(/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\278	 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\279	 AZX_DCAPS_SNOOP_TYPE(SCH))280 281#define AZX_DCAPS_INTEL_BAYTRAIL \282	(AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)283 284#define AZX_DCAPS_INTEL_BRASWELL \285	(AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\286	 AZX_DCAPS_I915_COMPONENT)287 288#define AZX_DCAPS_INTEL_SKYLAKE \289	(AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\290	 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)291 292#define AZX_DCAPS_INTEL_BROXTON		AZX_DCAPS_INTEL_SKYLAKE293 294#define AZX_DCAPS_INTEL_LNL \295	(AZX_DCAPS_INTEL_SKYLAKE | AZX_DCAPS_PIO_COMMANDS)296 297/* quirks for ATI SB / AMD Hudson */298#define AZX_DCAPS_PRESET_ATI_SB \299	(AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\300	 AZX_DCAPS_SNOOP_TYPE(ATI))301 302/* quirks for ATI/AMD HDMI */303#define AZX_DCAPS_PRESET_ATI_HDMI \304	(AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\305	 AZX_DCAPS_NO_MSI64)306 307/* quirks for ATI HDMI with snoop off */308#define AZX_DCAPS_PRESET_ATI_HDMI_NS \309	(AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)310 311/* quirks for AMD SB */312#define AZX_DCAPS_PRESET_AMD_SB \313	(AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\314	 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\315	 AZX_DCAPS_RETRY_PROBE)316 317/* quirks for Nvidia */318#define AZX_DCAPS_PRESET_NVIDIA \319	(AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\320	 AZX_DCAPS_SNOOP_TYPE(NVIDIA))321 322#define AZX_DCAPS_PRESET_CTHDA \323	(AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\324	 AZX_DCAPS_NO_64BIT |\325	 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)326 327/*328 * vga_switcheroo support329 */330#ifdef SUPPORT_VGA_SWITCHEROO331#define use_vga_switcheroo(chip)	((chip)->use_vga_switcheroo)332#define needs_eld_notify_link(chip)	((chip)->bus.keep_power)333#else334#define use_vga_switcheroo(chip)	0335#define needs_eld_notify_link(chip)	false336#endif337 338static const char * const driver_short_names[] = {339	[AZX_DRIVER_ICH] = "HDA Intel",340	[AZX_DRIVER_PCH] = "HDA Intel PCH",341	[AZX_DRIVER_SCH] = "HDA Intel MID",342	[AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */343	[AZX_DRIVER_HDMI] = "HDA Intel HDMI",344	[AZX_DRIVER_ATI] = "HDA ATI SB",345	[AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",346	[AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",347	[AZX_DRIVER_GFHDMI] = "HDA GF HDMI",348	[AZX_DRIVER_VIA] = "HDA VIA VT82xx",349	[AZX_DRIVER_SIS] = "HDA SIS966",350	[AZX_DRIVER_ULI] = "HDA ULI M5461",351	[AZX_DRIVER_NVIDIA] = "HDA NVidia",352	[AZX_DRIVER_TERA] = "HDA Teradici", 353	[AZX_DRIVER_CTX] = "HDA Creative", 354	[AZX_DRIVER_CTHDA] = "HDA Creative",355	[AZX_DRIVER_CMEDIA] = "HDA C-Media",356	[AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",357	[AZX_DRIVER_LOONGSON] = "HDA Loongson",358	[AZX_DRIVER_GENERIC] = "HD-Audio Generic",359};360 361static int azx_acquire_irq(struct azx *chip, int do_disconnect);362static void set_default_power_save(struct azx *chip);363 364/*365 * initialize the PCI registers366 */367/* update bits in a PCI register byte */368static void update_pci_byte(struct pci_dev *pci, unsigned int reg,369			    unsigned char mask, unsigned char val)370{371	unsigned char data;372 373	pci_read_config_byte(pci, reg, &data);374	data &= ~mask;375	data |= (val & mask);376	pci_write_config_byte(pci, reg, data);377}378 379static void azx_init_pci(struct azx *chip)380{381	int snoop_type = azx_get_snoop_type(chip);382 383	/* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)384	 * TCSEL == Traffic Class Select Register, which sets PCI express QOS385	 * Ensuring these bits are 0 clears playback static on some HD Audio386	 * codecs.387	 * The PCI register TCSEL is defined in the Intel manuals.388	 */389	if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {390		dev_dbg(chip->card->dev, "Clearing TCSEL\n");391		update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);392	}393 394	/* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,395	 * we need to enable snoop.396	 */397	if (snoop_type == AZX_SNOOP_TYPE_ATI) {398		dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",399			azx_snoop(chip));400		update_pci_byte(chip->pci,401				ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,402				azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);403	}404 405	/* For NVIDIA HDA, enable snoop */406	if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {407		dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",408			azx_snoop(chip));409		update_pci_byte(chip->pci,410				NVIDIA_HDA_TRANSREG_ADDR,411				0x0f, NVIDIA_HDA_ENABLE_COHBITS);412		update_pci_byte(chip->pci,413				NVIDIA_HDA_ISTRM_COH,414				0x01, NVIDIA_HDA_ENABLE_COHBIT);415		update_pci_byte(chip->pci,416				NVIDIA_HDA_OSTRM_COH,417				0x01, NVIDIA_HDA_ENABLE_COHBIT);418	}419 420	/* Enable SCH/PCH snoop if needed */421	if (snoop_type == AZX_SNOOP_TYPE_SCH) {422		unsigned short snoop;423		pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);424		if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||425		    (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {426			snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;427			if (!azx_snoop(chip))428				snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;429			pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);430			pci_read_config_word(chip->pci,431				INTEL_SCH_HDA_DEVC, &snoop);432		}433		dev_dbg(chip->card->dev, "SCH snoop: %s\n",434			(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?435			"Disabled" : "Enabled");436        }437}438 439/*440 * In BXT-P A0, HD-Audio DMA requests is later than expected,441 * and makes an audio stream sensitive to system latencies when442 * 24/32 bits are playing.443 * Adjusting threshold of DMA fifo to force the DMA request444 * sooner to improve latency tolerance at the expense of power.445 */446static void bxt_reduce_dma_latency(struct azx *chip)447{448	u32 val;449 450	val = azx_readl(chip, VS_EM4L);451	val &= (0x3 << 20);452	azx_writel(chip, VS_EM4L, val);453}454 455/*456 * ML_LCAP bits:457 *  bit 0: 6 MHz Supported458 *  bit 1: 12 MHz Supported459 *  bit 2: 24 MHz Supported460 *  bit 3: 48 MHz Supported461 *  bit 4: 96 MHz Supported462 *  bit 5: 192 MHz Supported463 */464static int intel_get_lctl_scf(struct azx *chip)465{466	struct hdac_bus *bus = azx_bus(chip);467	static const int preferred_bits[] = { 2, 3, 1, 4, 5 };468	u32 val, t;469	int i;470 471	val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);472 473	for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {474		t = preferred_bits[i];475		if (val & (1 << t))476			return t;477	}478 479	dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");480	return 0;481}482 483static int intel_ml_lctl_set_power(struct azx *chip, int state)484{485	struct hdac_bus *bus = azx_bus(chip);486	u32 val;487	int timeout;488 489	/*490	 * Changes to LCTL.SCF are only needed for the first multi-link dealing491	 * with external codecs492	 */493	val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);494	val &= ~AZX_ML_LCTL_SPA;495	val |= state << AZX_ML_LCTL_SPA_SHIFT;496	writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);497	/* wait for CPA */498	timeout = 50;499	while (timeout) {500		if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &501		    AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT))502			return 0;503		timeout--;504		udelay(10);505	}506 507	return -1;508}509 510static void intel_init_lctl(struct azx *chip)511{512	struct hdac_bus *bus = azx_bus(chip);513	u32 val;514	int ret;515 516	/* 0. check lctl register value is correct or not */517	val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);518	/* only perform additional configurations if the SCF is initially based on 6MHz */519	if ((val & AZX_ML_LCTL_SCF) != 0)520		return;521 522	/*523	 * Before operating on SPA, CPA must match SPA.524	 * Any deviation may result in undefined behavior.525	 */526	if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) !=527		((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT))528		return;529 530	/* 1. turn link down: set SPA to 0 and wait CPA to 0 */531	ret = intel_ml_lctl_set_power(chip, 0);532	udelay(100);533	if (ret)534		goto set_spa;535 536	/* 2. update SCF to select an audio clock different from 6MHz */537	val &= ~AZX_ML_LCTL_SCF;538	val |= intel_get_lctl_scf(chip);539	writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);540 541set_spa:542	/* 4. turn link up: set SPA to 1 and wait CPA to 1 */543	intel_ml_lctl_set_power(chip, 1);544	udelay(100);545}546 547static void hda_intel_init_chip(struct azx *chip, bool full_reset)548{549	struct hdac_bus *bus = azx_bus(chip);550	struct pci_dev *pci = chip->pci;551	u32 val;552 553	snd_hdac_set_codec_wakeup(bus, true);554	if (chip->driver_type == AZX_DRIVER_SKL) {555		pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);556		val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;557		pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);558	}559	azx_init_chip(chip, full_reset);560	if (chip->driver_type == AZX_DRIVER_SKL) {561		pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);562		val = val | INTEL_HDA_CGCTL_MISCBDCGE;563		pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);564	}565 566	snd_hdac_set_codec_wakeup(bus, false);567 568	/* reduce dma latency to avoid noise */569	if (HDA_CONTROLLER_IS_APL(pci))570		bxt_reduce_dma_latency(chip);571 572	if (bus->mlcap != NULL)573		intel_init_lctl(chip);574}575 576/* calculate runtime delay from LPIB */577static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,578				   unsigned int pos)579{580	struct snd_pcm_substream *substream = azx_dev->core.substream;581	int stream = substream->stream;582	unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);583	int delay;584 585	if (stream == SNDRV_PCM_STREAM_PLAYBACK)586		delay = pos - lpib_pos;587	else588		delay = lpib_pos - pos;589	if (delay < 0) {590		if (delay >= azx_dev->core.delay_negative_threshold)591			delay = 0;592		else593			delay += azx_dev->core.bufsize;594	}595 596	if (delay >= azx_dev->core.period_bytes) {597		dev_info(chip->card->dev,598			 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",599			 delay, azx_dev->core.period_bytes);600		delay = 0;601		chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;602		chip->get_delay[stream] = NULL;603	}604 605	return bytes_to_frames(substream->runtime, delay);606}607 608static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);609 610/* called from IRQ */611static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)612{613	struct hda_intel *hda = container_of(chip, struct hda_intel, chip);614	int ok;615 616	ok = azx_position_ok(chip, azx_dev);617	if (ok == 1) {618		azx_dev->irq_pending = 0;619		return ok;620	} else if (ok == 0) {621		/* bogus IRQ, process it later */622		azx_dev->irq_pending = 1;623		schedule_work(&hda->irq_pending_work);624	}625	return 0;626}627 628#define display_power(chip, enable) \629	snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)630 631/*632 * Check whether the current DMA position is acceptable for updating633 * periods.  Returns non-zero if it's OK.634 *635 * Many HD-audio controllers appear pretty inaccurate about636 * the update-IRQ timing.  The IRQ is issued before actually the637 * data is processed.  So, we need to process it afterwords in a638 * workqueue.639 *640 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update641 */642static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)643{644	struct snd_pcm_substream *substream = azx_dev->core.substream;645	struct snd_pcm_runtime *runtime = substream->runtime;646	int stream = substream->stream;647	u32 wallclk;648	unsigned int pos;649	snd_pcm_uframes_t hwptr, target;650 651	/*652	 * The value of the WALLCLK register is always 0653	 * on the Loongson controller, so we return directly.654	 */655	if (chip->driver_type == AZX_DRIVER_LOONGSON)656		return 1;657 658	wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;659	if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)660		return -1;	/* bogus (too early) interrupt */661 662	if (chip->get_position[stream])663		pos = chip->get_position[stream](chip, azx_dev);664	else { /* use the position buffer as default */665		pos = azx_get_pos_posbuf(chip, azx_dev);666		if (!pos || pos == (u32)-1) {667			dev_info(chip->card->dev,668				 "Invalid position buffer, using LPIB read method instead.\n");669			chip->get_position[stream] = azx_get_pos_lpib;670			if (chip->get_position[0] == azx_get_pos_lpib &&671			    chip->get_position[1] == azx_get_pos_lpib)672				azx_bus(chip)->use_posbuf = false;673			pos = azx_get_pos_lpib(chip, azx_dev);674			chip->get_delay[stream] = NULL;675		} else {676			chip->get_position[stream] = azx_get_pos_posbuf;677			if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)678				chip->get_delay[stream] = azx_get_delay_from_lpib;679		}680	}681 682	if (pos >= azx_dev->core.bufsize)683		pos = 0;684 685	if (WARN_ONCE(!azx_dev->core.period_bytes,686		      "hda-intel: zero azx_dev->period_bytes"))687		return -1; /* this shouldn't happen! */688	if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&689	    pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)690		/* NG - it's below the first next period boundary */691		return chip->bdl_pos_adj ? 0 : -1;692	azx_dev->core.start_wallclk += wallclk;693 694	if (azx_dev->core.no_period_wakeup)695		return 1; /* OK, no need to check period boundary */696 697	if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt)698		return 1; /* OK, already in hwptr updating process */699 700	/* check whether the period gets really elapsed */701	pos = bytes_to_frames(runtime, pos);702	hwptr = runtime->hw_ptr_base + pos;703	if (hwptr < runtime->status->hw_ptr)704		hwptr += runtime->buffer_size;705	target = runtime->hw_ptr_interrupt + runtime->period_size;706	if (hwptr < target) {707		/* too early wakeup, process it later */708		return chip->bdl_pos_adj ? 0 : -1;709	}710 711	return 1; /* OK, it's fine */712}713 714/*715 * The work for pending PCM period updates.716 */717static void azx_irq_pending_work(struct work_struct *work)718{719	struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);720	struct azx *chip = &hda->chip;721	struct hdac_bus *bus = azx_bus(chip);722	struct hdac_stream *s;723	int pending, ok;724 725	if (!hda->irq_pending_warned) {726		dev_info(chip->card->dev,727			 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",728			 chip->card->number);729		hda->irq_pending_warned = 1;730	}731 732	for (;;) {733		pending = 0;734		spin_lock_irq(&bus->reg_lock);735		list_for_each_entry(s, &bus->stream_list, list) {736			struct azx_dev *azx_dev = stream_to_azx_dev(s);737			if (!azx_dev->irq_pending ||738			    !s->substream ||739			    !s->running)740				continue;741			ok = azx_position_ok(chip, azx_dev);742			if (ok > 0) {743				azx_dev->irq_pending = 0;744				spin_unlock(&bus->reg_lock);745				snd_pcm_period_elapsed(s->substream);746				spin_lock(&bus->reg_lock);747			} else if (ok < 0) {748				pending = 0;	/* too early */749			} else750				pending++;751		}752		spin_unlock_irq(&bus->reg_lock);753		if (!pending)754			return;755		msleep(1);756	}757}758 759/* clear irq_pending flags and assure no on-going workq */760static void azx_clear_irq_pending(struct azx *chip)761{762	struct hdac_bus *bus = azx_bus(chip);763	struct hdac_stream *s;764 765	spin_lock_irq(&bus->reg_lock);766	list_for_each_entry(s, &bus->stream_list, list) {767		struct azx_dev *azx_dev = stream_to_azx_dev(s);768		azx_dev->irq_pending = 0;769	}770	spin_unlock_irq(&bus->reg_lock);771}772 773static int azx_acquire_irq(struct azx *chip, int do_disconnect)774{775	struct hdac_bus *bus = azx_bus(chip);776 777	if (request_irq(chip->pci->irq, azx_interrupt,778			chip->msi ? 0 : IRQF_SHARED,779			chip->card->irq_descr, chip)) {780		dev_err(chip->card->dev,781			"unable to grab IRQ %d, disabling device\n",782			chip->pci->irq);783		if (do_disconnect)784			snd_card_disconnect(chip->card);785		return -1;786	}787	bus->irq = chip->pci->irq;788	chip->card->sync_irq = bus->irq;789	pci_intx(chip->pci, !chip->msi);790	return 0;791}792 793/* get the current DMA position with correction on VIA chips */794static unsigned int azx_via_get_position(struct azx *chip,795					 struct azx_dev *azx_dev)796{797	unsigned int link_pos, mini_pos, bound_pos;798	unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;799	unsigned int fifo_size;800 801	link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));802	if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {803		/* Playback, no problem using link position */804		return link_pos;805	}806 807	/* Capture */808	/* For new chipset,809	 * use mod to get the DMA position just like old chipset810	 */811	mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);812	mod_dma_pos %= azx_dev->core.period_bytes;813 814	fifo_size = azx_stream(azx_dev)->fifo_size;815 816	if (azx_dev->insufficient) {817		/* Link position never gather than FIFO size */818		if (link_pos <= fifo_size)819			return 0;820 821		azx_dev->insufficient = 0;822	}823 824	if (link_pos <= fifo_size)825		mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;826	else827		mini_pos = link_pos - fifo_size;828 829	/* Find nearest previous boudary */830	mod_mini_pos = mini_pos % azx_dev->core.period_bytes;831	mod_link_pos = link_pos % azx_dev->core.period_bytes;832	if (mod_link_pos >= fifo_size)833		bound_pos = link_pos - mod_link_pos;834	else if (mod_dma_pos >= mod_mini_pos)835		bound_pos = mini_pos - mod_mini_pos;836	else {837		bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;838		if (bound_pos >= azx_dev->core.bufsize)839			bound_pos = 0;840	}841 842	/* Calculate real DMA position we want */843	return bound_pos + mod_dma_pos;844}845 846#define AMD_FIFO_SIZE	32847 848/* get the current DMA position with FIFO size correction */849static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)850{851	struct snd_pcm_substream *substream = azx_dev->core.substream;852	struct snd_pcm_runtime *runtime = substream->runtime;853	unsigned int pos, delay;854 855	pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));856	if (!runtime)857		return pos;858 859	runtime->delay = AMD_FIFO_SIZE;860	delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);861	if (azx_dev->insufficient) {862		if (pos < delay) {863			delay = pos;864			runtime->delay = bytes_to_frames(runtime, pos);865		} else {866			azx_dev->insufficient = 0;867		}868	}869 870	/* correct the DMA position for capture stream */871	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {872		if (pos < delay)873			pos += azx_dev->core.bufsize;874		pos -= delay;875	}876 877	return pos;878}879 880static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,881				   unsigned int pos)882{883	struct snd_pcm_substream *substream = azx_dev->core.substream;884 885	/* just read back the calculated value in the above */886	return substream->runtime->delay;887}888 889static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset)890{891	azx_stop_chip(chip);892	if (!skip_link_reset)893		azx_enter_link_reset(chip);894	azx_clear_irq_pending(chip);895	display_power(chip, false);896}897 898static DEFINE_MUTEX(card_list_lock);899static LIST_HEAD(card_list);900 901static void azx_shutdown_chip(struct azx *chip)902{903	__azx_shutdown_chip(chip, false);904}905 906static void azx_add_card_list(struct azx *chip)907{908	struct hda_intel *hda = container_of(chip, struct hda_intel, chip);909	mutex_lock(&card_list_lock);910	list_add(&hda->list, &card_list);911	mutex_unlock(&card_list_lock);912}913 914static void azx_del_card_list(struct azx *chip)915{916	struct hda_intel *hda = container_of(chip, struct hda_intel, chip);917	mutex_lock(&card_list_lock);918	list_del_init(&hda->list);919	mutex_unlock(&card_list_lock);920}921 922/* trigger power-save check at writing parameter */923static int __maybe_unused param_set_xint(const char *val, const struct kernel_param *kp)924{925	struct hda_intel *hda;926	struct azx *chip;927	int prev = power_save;928	int ret = param_set_int(val, kp);929 930	if (ret || prev == power_save)931		return ret;932 933	if (pm_blacklist > 0)934		return 0;935 936	mutex_lock(&card_list_lock);937	list_for_each_entry(hda, &card_list, list) {938		chip = &hda->chip;939		if (!hda->probe_continued || chip->disabled ||940		    hda->runtime_pm_disabled)941			continue;942		snd_hda_set_power_save(&chip->bus, power_save * 1000);943	}944	mutex_unlock(&card_list_lock);945	return 0;946}947 948/*949 * power management950 */951static bool azx_is_pm_ready(struct snd_card *card)952{953	struct azx *chip;954	struct hda_intel *hda;955 956	if (!card)957		return false;958	chip = card->private_data;959	hda = container_of(chip, struct hda_intel, chip);960	if (chip->disabled || hda->init_failed || !chip->running)961		return false;962	return true;963}964 965static void __azx_runtime_resume(struct azx *chip)966{967	struct hda_intel *hda = container_of(chip, struct hda_intel, chip);968	struct hdac_bus *bus = azx_bus(chip);969	struct hda_codec *codec;970	int status;971 972	display_power(chip, true);973	if (hda->need_i915_power)974		snd_hdac_i915_set_bclk(bus);975 976	/* Read STATESTS before controller reset */977	status = azx_readw(chip, STATESTS);978 979	azx_init_pci(chip);980	hda_intel_init_chip(chip, true);981 982	/* Avoid codec resume if runtime resume is for system suspend */983	if (!chip->pm_prepared) {984		list_for_each_codec(codec, &chip->bus) {985			if (codec->relaxed_resume)986				continue;987 988			if (codec->forced_resume || (status & (1 << codec->addr)))989				pm_request_resume(hda_codec_dev(codec));990		}991	}992 993	/* power down again for link-controlled chips */994	if (!hda->need_i915_power)995		display_power(chip, false);996}997 998static int azx_prepare(struct device *dev)999{1000	struct snd_card *card = dev_get_drvdata(dev);1001	struct azx *chip;1002 1003	if (!azx_is_pm_ready(card))1004		return 0;1005 1006	chip = card->private_data;1007	chip->pm_prepared = 1;1008	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);1009 1010	flush_work(&azx_bus(chip)->unsol_work);1011 1012	/* HDA controller always requires different WAKEEN for runtime suspend1013	 * and system suspend, so don't use direct-complete here.1014	 */1015	return 0;1016}1017 1018static void azx_complete(struct device *dev)1019{1020	struct snd_card *card = dev_get_drvdata(dev);1021	struct azx *chip;1022 1023	if (!azx_is_pm_ready(card))1024		return;1025 1026	chip = card->private_data;1027	snd_power_change_state(card, SNDRV_CTL_POWER_D0);1028	chip->pm_prepared = 0;1029}1030 1031static int azx_suspend(struct device *dev)1032{1033	struct snd_card *card = dev_get_drvdata(dev);1034	struct azx *chip;1035	struct hdac_bus *bus;1036 1037	if (!azx_is_pm_ready(card))1038		return 0;1039 1040	chip = card->private_data;1041	bus = azx_bus(chip);1042	azx_shutdown_chip(chip);1043	if (bus->irq >= 0) {1044		free_irq(bus->irq, chip);1045		bus->irq = -1;1046		chip->card->sync_irq = -1;1047	}1048 1049	if (chip->msi)1050		pci_disable_msi(chip->pci);1051 1052	trace_azx_suspend(chip);1053	return 0;1054}1055 1056static int __maybe_unused azx_resume(struct device *dev)1057{1058	struct snd_card *card = dev_get_drvdata(dev);1059	struct azx *chip;1060 1061	if (!azx_is_pm_ready(card))1062		return 0;1063 1064	chip = card->private_data;1065	if (chip->msi)1066		if (pci_enable_msi(chip->pci) < 0)1067			chip->msi = 0;1068	if (azx_acquire_irq(chip, 1) < 0)1069		return -EIO;1070 1071	__azx_runtime_resume(chip);1072 1073	trace_azx_resume(chip);1074	return 0;1075}1076 1077/* put codec down to D3 at hibernation for Intel SKL+;1078 * otherwise BIOS may still access the codec and screw up the driver1079 */1080static int azx_freeze_noirq(struct device *dev)1081{1082	struct snd_card *card = dev_get_drvdata(dev);1083	struct azx *chip = card->private_data;1084	struct pci_dev *pci = to_pci_dev(dev);1085 1086	if (!azx_is_pm_ready(card))1087		return 0;1088	if (chip->driver_type == AZX_DRIVER_SKL)1089		pci_set_power_state(pci, PCI_D3hot);1090 1091	return 0;1092}1093 1094static int azx_thaw_noirq(struct device *dev)1095{1096	struct snd_card *card = dev_get_drvdata(dev);1097	struct azx *chip = card->private_data;1098	struct pci_dev *pci = to_pci_dev(dev);1099 1100	if (!azx_is_pm_ready(card))1101		return 0;1102	if (chip->driver_type == AZX_DRIVER_SKL)1103		pci_set_power_state(pci, PCI_D0);1104 1105	return 0;1106}1107 1108static int __maybe_unused azx_runtime_suspend(struct device *dev)1109{1110	struct snd_card *card = dev_get_drvdata(dev);1111	struct azx *chip;1112 1113	if (!azx_is_pm_ready(card))1114		return 0;1115	chip = card->private_data;1116 1117	/* enable controller wake up event */1118	azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);1119 1120	azx_shutdown_chip(chip);1121	trace_azx_runtime_suspend(chip);1122	return 0;1123}1124 1125static int __maybe_unused azx_runtime_resume(struct device *dev)1126{1127	struct snd_card *card = dev_get_drvdata(dev);1128	struct azx *chip;1129 1130	if (!azx_is_pm_ready(card))1131		return 0;1132	chip = card->private_data;1133	__azx_runtime_resume(chip);1134 1135	/* disable controller Wake Up event*/1136	azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);1137 1138	trace_azx_runtime_resume(chip);1139	return 0;1140}1141 1142static int __maybe_unused azx_runtime_idle(struct device *dev)1143{1144	struct snd_card *card = dev_get_drvdata(dev);1145	struct azx *chip;1146	struct hda_intel *hda;1147 1148	if (!card)1149		return 0;1150 1151	chip = card->private_data;1152	hda = container_of(chip, struct hda_intel, chip);1153	if (chip->disabled || hda->init_failed)1154		return 0;1155 1156	if (!power_save_controller || !azx_has_pm_runtime(chip) ||1157	    azx_bus(chip)->codec_powered || !chip->running)1158		return -EBUSY;1159 1160	/* ELD notification gets broken when HD-audio bus is off */1161	if (needs_eld_notify_link(chip))1162		return -EBUSY;1163 1164	return 0;1165}1166 1167static const struct dev_pm_ops azx_pm = {1168	SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)1169	.prepare = pm_sleep_ptr(azx_prepare),1170	.complete = pm_sleep_ptr(azx_complete),1171	.freeze_noirq = pm_sleep_ptr(azx_freeze_noirq),1172	.thaw_noirq = pm_sleep_ptr(azx_thaw_noirq),1173	SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)1174};1175 1176 1177static int azx_probe_continue(struct azx *chip);1178 1179#ifdef SUPPORT_VGA_SWITCHEROO1180static struct pci_dev *get_bound_vga(struct pci_dev *pci);1181 1182static void azx_vs_set_state(struct pci_dev *pci,1183			     enum vga_switcheroo_state state)1184{1185	struct snd_card *card = pci_get_drvdata(pci);1186	struct azx *chip = card->private_data;1187	struct hda_intel *hda = container_of(chip, struct hda_intel, chip);1188	struct hda_codec *codec;1189	bool disabled;1190 1191	wait_for_completion(&hda->probe_wait);1192	if (hda->init_failed)1193		return;1194 1195	disabled = (state == VGA_SWITCHEROO_OFF);1196	if (chip->disabled == disabled)1197		return;1198 1199	if (!hda->probe_continued) {1200		chip->disabled = disabled;1201		if (!disabled) {1202			dev_info(chip->card->dev,1203				 "Start delayed initialization\n");1204			if (azx_probe_continue(chip) < 0)1205				dev_err(chip->card->dev, "initialization error\n");1206		}1207	} else {1208		dev_info(chip->card->dev, "%s via vga_switcheroo\n",1209			 disabled ? "Disabling" : "Enabling");1210		if (disabled) {1211			list_for_each_codec(codec, &chip->bus) {1212				pm_runtime_suspend(hda_codec_dev(codec));1213				pm_runtime_disable(hda_codec_dev(codec));1214			}1215			pm_runtime_suspend(card->dev);1216			pm_runtime_disable(card->dev);1217			/* when we get suspended by vga_switcheroo we end up in D3cold,1218			 * however we have no ACPI handle, so pci/acpi can't put us there,1219			 * put ourselves there */1220			pci->current_state = PCI_D3cold;1221			chip->disabled = true;1222			if (snd_hda_lock_devices(&chip->bus))1223				dev_warn(chip->card->dev,1224					 "Cannot lock devices!\n");1225		} else {1226			snd_hda_unlock_devices(&chip->bus);1227			chip->disabled = false;1228			pm_runtime_enable(card->dev);1229			list_for_each_codec(codec, &chip->bus) {1230				pm_runtime_enable(hda_codec_dev(codec));1231				pm_runtime_resume(hda_codec_dev(codec));1232			}1233		}1234	}1235}1236 1237static bool azx_vs_can_switch(struct pci_dev *pci)1238{1239	struct snd_card *card = pci_get_drvdata(pci);1240	struct azx *chip = card->private_data;1241	struct hda_intel *hda = container_of(chip, struct hda_intel, chip);1242 1243	wait_for_completion(&hda->probe_wait);1244	if (hda->init_failed)1245		return false;1246	if (chip->disabled || !hda->probe_continued)1247		return true;1248	if (snd_hda_lock_devices(&chip->bus))1249		return false;1250	snd_hda_unlock_devices(&chip->bus);1251	return true;1252}1253 1254/*1255 * The discrete GPU cannot power down unless the HDA controller runtime1256 * suspends, so activate runtime PM on codecs even if power_save == 0.1257 */1258static void setup_vga_switcheroo_runtime_pm(struct azx *chip)1259{1260	struct hda_intel *hda = container_of(chip, struct hda_intel, chip);1261	struct hda_codec *codec;1262 1263	if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {1264		list_for_each_codec(codec, &chip->bus)1265			codec->auto_runtime_pm = 1;1266		/* reset the power save setup */1267		if (chip->running)1268			set_default_power_save(chip);1269	}1270}1271 1272static void azx_vs_gpu_bound(struct pci_dev *pci,1273			     enum vga_switcheroo_client_id client_id)1274{1275	struct snd_card *card = pci_get_drvdata(pci);1276	struct azx *chip = card->private_data;1277 1278	if (client_id == VGA_SWITCHEROO_DIS)1279		chip->bus.keep_power = 0;1280	setup_vga_switcheroo_runtime_pm(chip);1281}1282 1283static void init_vga_switcheroo(struct azx *chip)1284{1285	struct hda_intel *hda = container_of(chip, struct hda_intel, chip);1286	struct pci_dev *p = get_bound_vga(chip->pci);1287	struct pci_dev *parent;1288	if (p) {1289		dev_info(chip->card->dev,1290			 "Handle vga_switcheroo audio client\n");1291		hda->use_vga_switcheroo = 1;1292 1293		/* cleared in either gpu_bound op or codec probe, or when its1294		 * upstream port has _PR3 (i.e. dGPU).1295		 */1296		parent = pci_upstream_bridge(p);1297		chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;1298		chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;1299		pci_dev_put(p);1300	}1301}1302 1303static const struct vga_switcheroo_client_ops azx_vs_ops = {1304	.set_gpu_state = azx_vs_set_state,1305	.can_switch = azx_vs_can_switch,1306	.gpu_bound = azx_vs_gpu_bound,1307};1308 1309static int register_vga_switcheroo(struct azx *chip)1310{1311	struct hda_intel *hda = container_of(chip, struct hda_intel, chip);1312	struct pci_dev *p;1313	int err;1314 1315	if (!hda->use_vga_switcheroo)1316		return 0;1317 1318	p = get_bound_vga(chip->pci);1319	err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);1320	pci_dev_put(p);1321 1322	if (err < 0)1323		return err;1324	hda->vga_switcheroo_registered = 1;1325 1326	return 0;1327}1328#else1329#define init_vga_switcheroo(chip)		/* NOP */1330#define register_vga_switcheroo(chip)		01331#define check_hdmi_disabled(pci)	false1332#define setup_vga_switcheroo_runtime_pm(chip)	/* NOP */1333#endif /* SUPPORT_VGA_SWITCHER */1334 1335/*1336 * destructor1337 */1338static void azx_free(struct azx *chip)1339{1340	struct pci_dev *pci = chip->pci;1341	struct hda_intel *hda = container_of(chip, struct hda_intel, chip);1342	struct hdac_bus *bus = azx_bus(chip);1343 1344	if (hda->freed)1345		return;1346 1347	if (azx_has_pm_runtime(chip) && chip->running) {1348		pm_runtime_get_noresume(&pci->dev);1349		pm_runtime_forbid(&pci->dev);1350		pm_runtime_dont_use_autosuspend(&pci->dev);1351	}1352 1353	chip->running = 0;1354 1355	azx_del_card_list(chip);1356 1357	hda->init_failed = 1; /* to be sure */1358	complete_all(&hda->probe_wait);1359 1360	if (use_vga_switcheroo(hda)) {1361		if (chip->disabled && hda->probe_continued)1362			snd_hda_unlock_devices(&chip->bus);1363		if (hda->vga_switcheroo_registered)1364			vga_switcheroo_unregister_client(chip->pci);1365	}1366 1367	if (bus->chip_init) {1368		azx_clear_irq_pending(chip);1369		azx_stop_all_streams(chip);1370		azx_stop_chip(chip);1371	}1372 1373	if (bus->irq >= 0)1374		free_irq(bus->irq, (void*)chip);1375 1376	azx_free_stream_pages(chip);1377	azx_free_streams(chip);1378	snd_hdac_bus_exit(bus);1379 1380#ifdef CONFIG_SND_HDA_PATCH_LOADER1381	release_firmware(chip->fw);1382#endif1383	display_power(chip, false);1384 1385	if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)1386		snd_hdac_i915_exit(bus);1387 1388	hda->freed = 1;1389}1390 1391static int azx_dev_disconnect(struct snd_device *device)1392{1393	struct azx *chip = device->device_data;1394	struct hdac_bus *bus = azx_bus(chip);1395 1396	chip->bus.shutdown = 1;1397	cancel_work_sync(&bus->unsol_work);1398 1399	return 0;1400}1401 1402static int azx_dev_free(struct snd_device *device)1403{1404	azx_free(device->device_data);1405	return 0;1406}1407 1408#ifdef SUPPORT_VGA_SWITCHEROO1409#ifdef CONFIG_ACPI1410/* ATPX is in the integrated GPU's namespace */1411static bool atpx_present(void)1412{1413	struct pci_dev *pdev = NULL;1414	acpi_handle dhandle, atpx_handle;1415	acpi_status status;1416 1417	while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) {1418		if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) &&1419		    (pdev->class != PCI_CLASS_DISPLAY_OTHER << 8))1420			continue;1421 1422		dhandle = ACPI_HANDLE(&pdev->dev);1423		if (dhandle) {1424			status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);1425			if (ACPI_SUCCESS(status)) {1426				pci_dev_put(pdev);1427				return true;1428			}1429		}1430	}1431	return false;1432}1433#else1434static bool atpx_present(void)1435{1436	return false;1437}1438#endif1439 1440/*1441 * Check of disabled HDMI controller by vga_switcheroo1442 */1443static struct pci_dev *get_bound_vga(struct pci_dev *pci)1444{1445	struct pci_dev *p;1446 1447	/* check only discrete GPU */1448	switch (pci->vendor) {1449	case PCI_VENDOR_ID_ATI:1450	case PCI_VENDOR_ID_AMD:1451		if (pci->devfn == 1) {1452			p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),1453							pci->bus->number, 0);1454			if (p) {1455				/* ATPX is in the integrated GPU's ACPI namespace1456				 * rather than the dGPU's namespace. However,1457				 * the dGPU is the one who is involved in1458				 * vgaswitcheroo.1459				 */1460				if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&1461				    (atpx_present() || apple_gmux_detect(NULL, NULL)))1462					return p;1463				pci_dev_put(p);1464			}1465		}1466		break;1467	case PCI_VENDOR_ID_NVIDIA:1468		if (pci->devfn == 1) {1469			p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),1470							pci->bus->number, 0);1471			if (p) {1472				if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)1473					return p;1474				pci_dev_put(p);1475			}1476		}1477		break;1478	}1479	return NULL;1480}1481 1482static bool check_hdmi_disabled(struct pci_dev *pci)1483{1484	bool vga_inactive = false;1485	struct pci_dev *p = get_bound_vga(pci);1486 1487	if (p) {1488		if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)1489			vga_inactive = true;1490		pci_dev_put(p);1491	}1492	return vga_inactive;1493}1494#endif /* SUPPORT_VGA_SWITCHEROO */1495 1496/*1497 * allow/deny-listing for position_fix1498 */1499static const struct snd_pci_quirk position_fix_list[] = {1500	SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),1501	SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),1502	SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),1503	SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),1504	SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),1505	SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),1506	SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),1507	SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),1508	SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),1509	SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),1510	SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),1511	SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),1512	SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),1513	SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),1514	{}1515};1516 1517static int check_position_fix(struct azx *chip, int fix)1518{1519	const struct snd_pci_quirk *q;1520 1521	switch (fix) {1522	case POS_FIX_AUTO:1523	case POS_FIX_LPIB:1524	case POS_FIX_POSBUF:1525	case POS_FIX_VIACOMBO:1526	case POS_FIX_COMBO:1527	case POS_FIX_SKL:1528	case POS_FIX_FIFO:1529		return fix;1530	}1531 1532	q = snd_pci_quirk_lookup(chip->pci, position_fix_list);1533	if (q) {1534		dev_info(chip->card->dev,1535			 "position_fix set to %d for device %04x:%04x\n",1536			 q->value, q->subvendor, q->subdevice);1537		return q->value;1538	}1539 1540	/* Check VIA/ATI HD Audio Controller exist */1541	if (chip->driver_type == AZX_DRIVER_VIA) {1542		dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");1543		return POS_FIX_VIACOMBO;1544	}1545	if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {1546		dev_dbg(chip->card->dev, "Using FIFO position fix\n");1547		return POS_FIX_FIFO;1548	}1549	if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {1550		dev_dbg(chip->card->dev, "Using LPIB position fix\n");1551		return POS_FIX_LPIB;1552	}1553	if (chip->driver_type == AZX_DRIVER_SKL) {1554		dev_dbg(chip->card->dev, "Using SKL position fix\n");1555		return POS_FIX_SKL;1556	}1557	return POS_FIX_AUTO;1558}1559 1560static void assign_position_fix(struct azx *chip, int fix)1561{1562	static const azx_get_pos_callback_t callbacks[] = {1563		[POS_FIX_AUTO] = NULL,1564		[POS_FIX_LPIB] = azx_get_pos_lpib,1565		[POS_FIX_POSBUF] = azx_get_pos_posbuf,1566		[POS_FIX_VIACOMBO] = azx_via_get_position,1567		[POS_FIX_COMBO] = azx_get_pos_lpib,1568		[POS_FIX_SKL] = azx_get_pos_posbuf,1569		[POS_FIX_FIFO] = azx_get_pos_fifo,1570	};1571 1572	chip->get_position[0] = chip->get_position[1] = callbacks[fix];1573 1574	/* combo mode uses LPIB only for playback */1575	if (fix == POS_FIX_COMBO)1576		chip->get_position[1] = NULL;1577 1578	if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&1579	    (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {1580		chip->get_delay[0] = chip->get_delay[1] =1581			azx_get_delay_from_lpib;1582	}1583 1584	if (fix == POS_FIX_FIFO)1585		chip->get_delay[0] = chip->get_delay[1] =1586			azx_get_delay_from_fifo;1587}1588 1589/*1590 * deny-lists for probe_mask1591 */1592static const struct snd_pci_quirk probe_mask_list[] = {1593	/* Thinkpad often breaks the controller communication when accessing1594	 * to the non-working (or non-existing) modem codec slot.1595	 */1596	SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),1597	SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),1598	SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),1599	/* broken BIOS */1600	SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),1601	/* including bogus ALC268 in slot#2 that conflicts with ALC888 */1602	SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),1603	/* forced codec slots */1604	SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),1605	SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),1606	SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105),1607	/* WinFast VP200 H (Teradici) user reported broken communication */1608	SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),1609	{}1610};1611 1612#define AZX_FORCE_CODEC_MASK	0x1001613 1614static void check_probe_mask(struct azx *chip, int dev)1615{1616	const struct snd_pci_quirk *q;1617 1618	chip->codec_probe_mask = probe_mask[dev];1619	if (chip->codec_probe_mask == -1) {1620		q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);1621		if (q) {1622			dev_info(chip->card->dev,1623				 "probe_mask set to 0x%x for device %04x:%04x\n",1624				 q->value, q->subvendor, q->subdevice);1625			chip->codec_probe_mask = q->value;1626		}1627	}1628 1629	/* check forced option */1630	if (chip->codec_probe_mask != -1 &&1631	    (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {1632		azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;1633		dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",1634			 (int)azx_bus(chip)->codec_mask);1635	}1636}1637 1638/*1639 * allow/deny-list for enable_msi1640 */1641static const struct snd_pci_quirk msi_deny_list[] = {1642	SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */1643	SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */1644	SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */1645	SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */1646	SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */1647	SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */1648	SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */1649	SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */1650	SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */1651	SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */1652	{}1653};1654 1655static void check_msi(struct azx *chip)1656{1657	const struct snd_pci_quirk *q;1658 1659	if (enable_msi >= 0) {1660		chip->msi = !!enable_msi;1661		return;1662	}1663	chip->msi = 1;	/* enable MSI as default */1664	q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);1665	if (q) {1666		dev_info(chip->card->dev,1667			 "msi for device %04x:%04x set to %d\n",1668			 q->subvendor, q->subdevice, q->value);1669		chip->msi = q->value;1670		return;1671	}1672 1673	/* NVidia chipsets seem to cause troubles with MSI */1674	if (chip->driver_caps & AZX_DCAPS_NO_MSI) {1675		dev_info(chip->card->dev, "Disabling MSI\n");1676		chip->msi = 0;1677	}1678}1679 1680/* check the snoop mode availability */1681static void azx_check_snoop_available(struct azx *chip)1682{1683	int snoop = hda_snoop;1684 1685	if (snoop >= 0) {1686		dev_info(chip->card->dev, "Force to %s mode by module option\n",1687			 snoop ? "snoop" : "non-snoop");1688		chip->snoop = snoop;1689		chip->uc_buffer = !snoop;1690		return;1691	}1692 1693	snoop = true;1694	if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&1695	    chip->driver_type == AZX_DRIVER_VIA) {1696		/* force to non-snoop mode for a new VIA controller1697		 * when BIOS is set1698		 */1699		u8 val;1700		pci_read_config_byte(chip->pci, 0x42, &val);1701		if (!(val & 0x80) && (chip->pci->revision == 0x30 ||1702				      chip->pci->revision == 0x20))1703			snoop = false;1704	}1705 1706	if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)1707		snoop = false;1708 1709	chip->snoop = snoop;1710	if (!snoop) {1711		dev_info(chip->card->dev, "Force to non-snoop mode\n");1712		/* C-Media requires non-cached pages only for CORB/RIRB */1713		if (chip->driver_type != AZX_DRIVER_CMEDIA)1714			chip->uc_buffer = true;1715	}1716}1717 1718static void azx_probe_work(struct work_struct *work)1719{1720	struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work);1721	azx_probe_continue(&hda->chip);1722}1723 1724static int default_bdl_pos_adj(struct azx *chip)1725{1726	/* some exceptions: Atoms seem problematic with value 1 */1727	if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {1728		switch (chip->pci->device) {1729		case PCI_DEVICE_ID_INTEL_HDA_BYT:1730		case PCI_DEVICE_ID_INTEL_HDA_BSW:1731			return 32;1732		case PCI_DEVICE_ID_INTEL_HDA_APL:1733			return 64;1734		}1735	}1736 1737	switch (chip->driver_type) {1738	/*1739	 * increase the bdl size for Glenfly Gpus for hardware1740	 * limitation on hdac interrupt interval1741	 */1742	case AZX_DRIVER_GFHDMI:1743		return 128;1744	case AZX_DRIVER_ICH:1745	case AZX_DRIVER_PCH:1746		return 1;1747	default:1748		return 32;1749	}1750}1751 1752/*1753 * constructor1754 */1755static const struct hda_controller_ops pci_hda_ops;1756 1757static int azx_create(struct snd_card *card, struct pci_dev *pci,1758		      int dev, unsigned int driver_caps,1759		      struct azx **rchip)1760{1761	static const struct snd_device_ops ops = {1762		.dev_disconnect = azx_dev_disconnect,1763		.dev_free = azx_dev_free,1764	};1765	struct hda_intel *hda;1766	struct azx *chip;1767	int err;1768 1769	*rchip = NULL;1770 1771	err = pcim_enable_device(pci);1772	if (err < 0)1773		return err;1774 1775	hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);1776	if (!hda)1777		return -ENOMEM;1778 1779	chip = &hda->chip;1780	mutex_init(&chip->open_mutex);1781	chip->card = card;1782	chip->pci = pci;1783	chip->ops = &pci_hda_ops;1784	chip->driver_caps = driver_caps;1785	chip->driver_type = driver_caps & 0xff;1786	check_msi(chip);1787	chip->dev_index = dev;1788	if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)1789		chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);1790	INIT_LIST_HEAD(&chip->pcm_list);1791	INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);1792	INIT_LIST_HEAD(&hda->list);1793	init_vga_switcheroo(chip);1794	init_completion(&hda->probe_wait);1795 1796	assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));1797 1798	if (single_cmd < 0) /* allow fallback to single_cmd at errors */1799		chip->fallback_to_single_cmd = 1;1800	else /* explicitly set to single_cmd or not */1801		chip->single_cmd = single_cmd;1802 1803	azx_check_snoop_available(chip);1804 1805	if (bdl_pos_adj[dev] < 0)1806		chip->bdl_pos_adj = default_bdl_pos_adj(chip);1807	else1808		chip->bdl_pos_adj = bdl_pos_adj[dev];1809 1810	err = azx_bus_init(chip, model[dev]);1811	if (err < 0)1812		return err;1813 1814	/* use the non-cached pages in non-snoop mode */1815	if (!azx_snoop(chip))1816		azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC;1817 1818	if (chip->driver_type == AZX_DRIVER_NVIDIA) {1819		dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");1820		chip->bus.core.needs_damn_long_delay = 1;1821	}1822 1823	check_probe_mask(chip, dev);1824 1825	err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);1826	if (err < 0) {1827		dev_err(card->dev, "Error creating device [card]!\n");1828		azx_free(chip);1829		return err;1830	}1831 1832	/* continue probing in work context as may trigger request module */1833	INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work);1834 1835	*rchip = chip;1836 1837	return 0;1838}1839 1840static int azx_first_init(struct azx *chip)1841{1842	int dev = chip->dev_index;1843	struct pci_dev *pci = chip->pci;1844	struct snd_card *card = chip->card;1845	struct hdac_bus *bus = azx_bus(chip);1846	int err;1847	unsigned short gcap;1848	unsigned int dma_bits = 64;1849 1850#if BITS_PER_LONG != 641851	/* Fix up base address on ULI M5461 */1852	if (chip->driver_type == AZX_DRIVER_ULI) {1853		u16 tmp3;1854		pci_read_config_word(pci, 0x40, &tmp3);1855		pci_write_config_word(pci, 0x40, tmp3 | 0x10);1856		pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);1857	}1858#endif1859	/*1860	 * Fix response write request not synced to memory when handle1861	 * hdac interrupt on Glenfly Gpus1862	 */1863	if (chip->driver_type == AZX_DRIVER_GFHDMI)1864		bus->polling_mode = 1;1865 1866	if (chip->driver_type == AZX_DRIVER_LOONGSON) {1867		bus->polling_mode = 1;1868		bus->not_use_interrupts = 1;1869		bus->access_sdnctl_in_dword = 1;1870	}1871 1872	err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio");1873	if (err < 0)1874		return err;1875 1876	bus->addr = pci_resource_start(pci, 0);1877	bus->remap_addr = pcim_iomap_table(pci)[0];1878 1879	if (chip->driver_type == AZX_DRIVER_SKL)1880		snd_hdac_bus_parse_capabilities(bus);1881 1882	/*1883	 * Some Intel CPUs has always running timer (ART) feature and1884	 * controller may have Global time sync reporting capability, so1885	 * check both of these before declaring synchronized time reporting1886	 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME1887	 */1888	chip->gts_present = false;1889 1890#ifdef CONFIG_X861891	if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))1892		chip->gts_present = true;1893#endif1894 1895	if (chip->msi) {1896		if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {1897			dev_dbg(card->dev, "Disabling 64bit MSI\n");1898			pci->no_64bit_msi = true;1899		}1900		if (pci_enable_msi(pci) < 0)1901			chip->msi = 0;1902	}1903 1904	pci_set_master(pci);1905 1906	gcap = azx_readw(chip, GCAP);1907	dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);1908 1909	/* AMD devices support 40 or 48bit DMA, take the safe one */1910	if (chip->pci->vendor == PCI_VENDOR_ID_AMD)1911		dma_bits = 40;1912 1913	/* disable SB600 64bit support for safety */1914	if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {1915		struct pci_dev *p_smbus;1916		dma_bits = 40;1917		p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,1918					 PCI_DEVICE_ID_ATI_SBX00_SMBUS,1919					 NULL);1920		if (p_smbus) {1921			if (p_smbus->revision < 0x30)1922				gcap &= ~AZX_GCAP_64OK;1923			pci_dev_put(p_smbus);1924		}1925	}1926 1927	/* NVidia hardware normally only supports up to 40 bits of DMA */1928	if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)1929		dma_bits = 40;1930 1931	/* disable 64bit DMA address on some devices */1932	if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {1933		dev_dbg(card->dev, "Disabling 64bit DMA\n");1934		gcap &= ~AZX_GCAP_64OK;1935	}1936 1937	/* disable buffer size rounding to 128-byte multiples if supported */1938	if (align_buffer_size >= 0)1939		chip->align_buffer_size = !!align_buffer_size;1940	else {1941		if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)1942			chip->align_buffer_size = 0;1943		else1944			chip->align_buffer_size = 1;1945	}1946 1947	/* allow 64bit DMA address if supported by H/W */1948	if (!(gcap & AZX_GCAP_64OK))1949		dma_bits = 32;1950	if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))1951		dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));1952	dma_set_max_seg_size(&pci->dev, UINT_MAX);1953 1954	/* read number of streams from GCAP register instead of using1955	 * hardcoded value1956	 */1957	chip->capture_streams = (gcap >> 8) & 0x0f;1958	chip->playback_streams = (gcap >> 12) & 0x0f;1959	if (!chip->playback_streams && !chip->capture_streams) {1960		/* gcap didn't give any info, switching to old method */1961 1962		switch (chip->driver_type) {1963		case AZX_DRIVER_ULI:1964			chip->playback_streams = ULI_NUM_PLAYBACK;1965			chip->capture_streams = ULI_NUM_CAPTURE;1966			break;1967		case AZX_DRIVER_ATIHDMI:1968		case AZX_DRIVER_ATIHDMI_NS:1969			chip->playback_streams = ATIHDMI_NUM_PLAYBACK;1970			chip->capture_streams = ATIHDMI_NUM_CAPTURE;1971			break;1972		case AZX_DRIVER_GFHDMI:1973		case AZX_DRIVER_GENERIC:1974		default:1975			chip->playback_streams = ICH6_NUM_PLAYBACK;1976			chip->capture_streams = ICH6_NUM_CAPTURE;1977			break;1978		}1979	}1980	chip->capture_index_offset = 0;1981	chip->playback_index_offset = chip->capture_streams;1982	chip->num_streams = chip->playback_streams + chip->capture_streams;1983 1984	/* sanity check for the SDxCTL.STRM field overflow */1985	if (chip->num_streams > 15 &&1986	    (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {1987		dev_warn(chip->card->dev, "number of I/O streams is %d, "1988			 "forcing separate stream tags", chip->num_streams);1989		chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;1990	}1991 1992	/* initialize streams */1993	err = azx_init_streams(chip);1994	if (err < 0)1995		return err;1996 1997	err = azx_alloc_stream_pages(chip);1998	if (err < 0)1999		return err;2000 2001	/* initialize chip */2002	azx_init_pci(chip);2003 2004	snd_hdac_i915_set_bclk(bus);2005 2006	hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);2007 2008	/* codec detection */2009	if (!azx_bus(chip)->codec_mask) {2010		dev_err(card->dev, "no codecs found!\n");2011		/* keep running the rest for the runtime PM */2012	}2013 2014	if (azx_acquire_irq(chip, 0) < 0)2015		return -EBUSY;2016 2017	strcpy(card->driver, "HDA-Intel");2018	strscpy(card->shortname, driver_short_names[chip->driver_type],2019		sizeof(card->shortname));2020	snprintf(card->longname, sizeof(card->longname),2021		 "%s at 0x%lx irq %i",2022		 card->shortname, bus->addr, bus->irq);2023 2024	return 0;2025}2026 2027#ifdef CONFIG_SND_HDA_PATCH_LOADER2028/* callback from request_firmware_nowait() */2029static void azx_firmware_cb(const struct firmware *fw, void *context)2030{2031	struct snd_card *card = context;2032	struct azx *chip = card->private_data;2033 2034	if (fw)2035		chip->fw = fw;2036	else2037		dev_err(card->dev, "Cannot load firmware, continue without patching\n");2038	if (!chip->disabled) {2039		/* continue probing */2040		azx_probe_continue(chip);2041	}2042}2043#endif2044 2045static int disable_msi_reset_irq(struct azx *chip)2046{2047	struct hdac_bus *bus = azx_bus(chip);2048	int err;2049 2050	free_irq(bus->irq, chip);2051	bus->irq = -1;2052	chip->card->sync_irq = -1;2053	pci_disable_msi(chip->pci);2054	chip->msi = 0;2055	err = azx_acquire_irq(chip, 1);2056	if (err < 0)2057		return err;2058 2059	return 0;2060}2061 2062/* Denylist for skipping the whole probe:2063 * some HD-audio PCI entries are exposed without any codecs, and such devices2064 * should be ignored from the beginning.2065 */2066static const struct pci_device_id driver_denylist[] = {2067	{ PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */2068	{ PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */2069	{ PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */2070	{ PCI_DEVICE_SUB(0x1022, 0x15e3, 0x1022, 0xd601) }, /* ASRock X670E Taichi */2071	{}2072};2073 2074static const struct hda_controller_ops pci_hda_ops = {2075	.disable_msi_reset_irq = disable_msi_reset_irq,2076	.position_check = azx_position_check,2077};2078 2079static DECLARE_BITMAP(probed_devs, SNDRV_CARDS);2080 2081static int azx_probe(struct pci_dev *pci,2082		     const struct pci_device_id *pci_id)2083{2084	struct snd_card *card;2085	struct hda_intel *hda;2086	struct azx *chip;2087	bool schedule_probe;2088	int dev;2089	int err;2090 2091	if (pci_match_id(driver_denylist, pci)) {2092		dev_info(&pci->dev, "Skipping the device on the denylist\n");2093		return -ENODEV;2094	}2095 2096	dev = find_first_zero_bit(probed_devs, SNDRV_CARDS);2097	if (dev >= SNDRV_CARDS)2098		return -ENODEV;2099	if (!enable[dev]) {2100		set_bit(dev, probed_devs);2101		return -ENOENT;2102	}2103 2104	/*2105	 * stop probe if another Intel's DSP driver should be activated2106	 */2107	if (dmic_detect) {2108		err = snd_intel_dsp_driver_probe(pci);2109		if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {2110			dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");2111			return -ENODEV;2112		}2113	} else {2114		dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");2115	}2116 2117	err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,2118			   0, &card);2119	if (err < 0) {2120		dev_err(&pci->dev, "Error creating card!\n");2121		return err;2122	}2123 2124	err = azx_create(card, pci, dev, pci_id->driver_data, &chip);2125	if (err < 0)2126		goto out_free;2127	card->private_data = chip;2128	hda = container_of(chip, struct hda_intel, chip);2129 2130	pci_set_drvdata(pci, card);2131 2132#ifdef CONFIG_SND_HDA_I9152133	/* bind with i915 if needed */2134	if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {2135		err = snd_hdac_i915_init(azx_bus(chip));2136		if (err < 0) {2137			if (err == -EPROBE_DEFER)2138				goto out_free;2139 2140			/* if the controller is bound only with HDMI/DP2141			 * (for HSW and BDW), we need to abort the probe;2142			 * for other chips, still continue probing as other2143			 * codecs can be on the same link.2144			 */2145			if (HDA_CONTROLLER_IN_GPU(pci)) {2146				dev_err_probe(card->dev, err,2147					     "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");2148 2149				goto out_free;2150			} else {2151				/* don't bother any longer */2152				chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;2153			}2154		}2155 2156		/* HSW/BDW controllers need this power */2157		if (HDA_CONTROLLER_IN_GPU(pci))2158			hda->need_i915_power = true;2159	}2160#else2161	if (HDA_CONTROLLER_IN_GPU(pci))2162		dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");2163#endif2164 2165	err = register_vga_switcheroo(chip);2166	if (err < 0) {2167		dev_err(card->dev, "Error registering vga_switcheroo client\n");2168		goto out_free;2169	}2170 2171	if (check_hdmi_disabled(pci)) {2172		dev_info(card->dev, "VGA controller is disabled\n");2173		dev_info(card->dev, "Delaying initialization\n");2174		chip->disabled = true;2175	}2176 2177	schedule_probe = !chip->disabled;2178 2179#ifdef CONFIG_SND_HDA_PATCH_LOADER2180	if (patch[dev] && *patch[dev]) {2181		dev_info(card->dev, "Applying patch firmware '%s'\n",2182			 patch[dev]);2183		err = request_firmware_nowait(THIS_MODULE, true, patch[dev],2184					      &pci->dev, GFP_KERNEL, card,2185					      azx_firmware_cb);2186		if (err < 0)2187			goto out_free;2188		schedule_probe = false; /* continued in azx_firmware_cb() */2189	}2190#endif /* CONFIG_SND_HDA_PATCH_LOADER */2191 2192	if (schedule_probe)2193		schedule_delayed_work(&hda->probe_work, 0);2194 2195	set_bit(dev, probed_devs);2196	if (chip->disabled)2197		complete_all(&hda->probe_wait);2198	return 0;2199 2200out_free:2201	pci_set_drvdata(pci, NULL);2202	snd_card_free(card);2203	return err;2204}2205 2206/* On some boards setting power_save to a non 0 value leads to clicking /2207 * popping sounds when ever we enter/leave powersaving mode. Ideally we would2208 * figure out how to avoid these sounds, but that is not always feasible.2209 * So we keep a list of devices where we disable powersaving as its known2210 * to causes problems on these devices.2211 */2212static const struct snd_pci_quirk power_save_denylist[] = {2213	/* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */2214	SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),2215	/* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */2216	SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),2217	/* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */2218	SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),2219	/* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */2220	SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),2221	/* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */2222	SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),2223	/* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */2224	/* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */2225	SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),2226	/* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */2227	SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),2228	/* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */2229	SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),2230	/* https://bugs.launchpad.net/bugs/1821663 */2231	SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),2232	/* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */2233	SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),2234	/* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */2235	SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),2236	SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0),2237	/* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */2238	SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),2239	/* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */2240	SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),2241	/* https://bugs.launchpad.net/bugs/1821663 */2242	SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),2243	/* KONTRON SinglePC may cause a stall at runtime resume */2244	SND_PCI_QUIRK(0x1734, 0x1232, "KONTRON SinglePC", 0),2245	{}2246};2247 2248static void set_default_power_save(struct azx *chip)2249{2250	struct hda_intel *hda = container_of(chip, struct hda_intel, chip);2251	int val = power_save;2252 2253	if (pm_blacklist < 0) {2254		const struct snd_pci_quirk *q;2255 2256		q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);2257		if (q && val) {2258			dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",2259				 q->subvendor, q->subdevice);2260			val = 0;2261			hda->runtime_pm_disabled = 1;2262		}2263	} else if (pm_blacklist > 0) {2264		dev_info(chip->card->dev, "Forcing power_save to 0 via option\n");2265		val = 0;2266	}2267	snd_hda_set_power_save(&chip->bus, val * 1000);2268}2269 2270/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */2271static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {2272	[AZX_DRIVER_NVIDIA] = 8,2273	[AZX_DRIVER_TERA] = 1,2274};2275 2276static int azx_probe_continue(struct azx *chip)2277{2278	struct hda_intel *hda = container_of(chip, struct hda_intel, chip);2279	struct hdac_bus *bus = azx_bus(chip);2280	struct pci_dev *pci = chip->pci;2281	int dev = chip->dev_index;2282	int err;2283 2284	if (chip->disabled || hda->init_failed)2285		return -EIO;2286	if (hda->probe_retry)2287		goto probe_retry;2288 2289	to_hda_bus(bus)->bus_probing = 1;2290	hda->probe_continued = 1;2291 2292	/* Request display power well for the HDA controller or codec. For2293	 * Haswell/Broadwell, both the display HDA controller and codec need2294	 * this power. For other platforms, like Baytrail/Braswell, only the2295	 * display codec needs the power and it can be released after probe.2296	 */2297	display_power(chip, true);2298 2299	err = azx_first_init(chip);2300	if (err < 0)2301		goto out_free;2302 2303#ifdef CONFIG_SND_HDA_INPUT_BEEP2304	chip->beep_mode = beep_mode[dev];2305#endif2306 2307	chip->ctl_dev_id = ctl_dev_id;2308 2309	/* create codec instances */2310	if (bus->codec_mask) {2311		err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);2312		if (err < 0)2313			goto out_free;2314	}2315 2316#ifdef CONFIG_SND_HDA_PATCH_LOADER2317	if (chip->fw) {2318		err = snd_hda_load_patch(&chip->bus, chip->fw->size,2319					 chip->fw->data);2320		if (err < 0)2321			goto out_free;2322	}2323#endif2324 2325 probe_retry:2326	if (bus->codec_mask && !(probe_only[dev] & 1)) {2327		err = azx_codec_configure(chip);2328		if (err) {2329			if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) &&2330			    ++hda->probe_retry < 60) {2331				schedule_delayed_work(&hda->probe_work,2332						      msecs_to_jiffies(1000));2333				return 0; /* keep things up */2334			}2335			dev_err(chip->card->dev, "Cannot probe codecs, giving up\n");2336			goto out_free;2337		}2338	}2339 2340	err = snd_card_register(chip->card);2341	if (err < 0)2342		goto out_free;2343 2344	setup_vga_switcheroo_runtime_pm(chip);2345 2346	chip->running = 1;2347	azx_add_card_list(chip);2348 2349	set_default_power_save(chip);2350 2351	if (azx_has_pm_runtime(chip)) {2352		pm_runtime_use_autosuspend(&pci->dev);2353		pm_runtime_allow(&pci->dev);2354		pm_runtime_put_autosuspend(&pci->dev);2355	}2356 2357out_free:2358	if (err < 0) {2359		pci_set_drvdata(pci, NULL);2360		snd_card_free(chip->card);2361		return err;2362	}2363 2364	if (!hda->need_i915_power)2365		display_power(chip, false);2366	complete_all(&hda->probe_wait);2367	to_hda_bus(bus)->bus_probing = 0;2368	hda->probe_retry = 0;2369	return 0;2370}2371 2372static void azx_remove(struct pci_dev *pci)2373{2374	struct snd_card *card = pci_get_drvdata(pci);2375	struct azx *chip;2376	struct hda_intel *hda;2377 2378	if (card) {2379		/* cancel the pending probing work */2380		chip = card->private_data;2381		hda = container_of(chip, struct hda_intel, chip);2382		/* FIXME: below is an ugly workaround.2383		 * Both device_release_driver() and driver_probe_device()2384		 * take *both* the device's and its parent's lock before2385		 * calling the remove() and probe() callbacks.  The codec2386		 * probe takes the locks of both the codec itself and its2387		 * parent, i.e. the PCI controller dev.  Meanwhile, when2388		 * the PCI controller is unbound, it takes its lock, too2389		 * ==> ouch, a deadlock!2390		 * As a workaround, we unlock temporarily here the controller2391		 * device during cancel_work_sync() call.2392		 */2393		device_unlock(&pci->dev);2394		cancel_delayed_work_sync(&hda->probe_work);2395		device_lock(&pci->dev);2396 2397		clear_bit(chip->dev_index, probed_devs);2398		pci_set_drvdata(pci, NULL);2399		snd_card_free(card);2400	}2401}2402 2403static void azx_shutdown(struct pci_dev *pci)2404{2405	struct snd_card *card = pci_get_drvdata(pci);2406	struct azx *chip;2407 2408	if (!card)2409		return;2410	chip = card->private_data;2411	if (chip && chip->running)2412		__azx_shutdown_chip(chip, true);2413}2414 2415/* PCI IDs */2416static const struct pci_device_id azx_ids[] = {2417	/* CPT */2418	{ PCI_DEVICE_DATA(INTEL, HDA_CPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },2419	/* PBG */2420	{ PCI_DEVICE_DATA(INTEL, HDA_PBG, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },2421	/* Panther Point */2422	{ PCI_DEVICE_DATA(INTEL, HDA_PPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },2423	/* Lynx Point */2424	{ PCI_DEVICE_DATA(INTEL, HDA_LPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },2425	/* 9 Series */2426	{ PCI_DEVICE_DATA(INTEL, HDA_9_SERIES, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },2427	/* Wellsburg */2428	{ PCI_DEVICE_DATA(INTEL, HDA_WBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },2429	{ PCI_DEVICE_DATA(INTEL, HDA_WBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },2430	/* Lewisburg */2431	{ PCI_DEVICE_DATA(INTEL, HDA_LBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) },2432	{ PCI_DEVICE_DATA(INTEL, HDA_LBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) },2433	/* Lynx Point-LP */2434	{ PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },2435	/* Lynx Point-LP */2436	{ PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },2437	/* Wildcat Point-LP */2438	{ PCI_DEVICE_DATA(INTEL, HDA_WPT_LP, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },2439	/* Skylake (Sunrise Point) */2440	{ PCI_DEVICE_DATA(INTEL, HDA_SKL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2441	/* Skylake-LP (Sunrise Point-LP) */2442	{ PCI_DEVICE_DATA(INTEL, HDA_SKL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2443	/* Kabylake */2444	{ PCI_DEVICE_DATA(INTEL, HDA_KBL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2445	/* Kabylake-LP */2446	{ PCI_DEVICE_DATA(INTEL, HDA_KBL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2447	/* Kabylake-H */2448	{ PCI_DEVICE_DATA(INTEL, HDA_KBL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2449	/* Coffelake */2450	{ PCI_DEVICE_DATA(INTEL, HDA_CNL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2451	/* Cannonlake */2452	{ PCI_DEVICE_DATA(INTEL, HDA_CNL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2453	/* CometLake-LP */2454	{ PCI_DEVICE_DATA(INTEL, HDA_CML_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2455	/* CometLake-H */2456	{ PCI_DEVICE_DATA(INTEL, HDA_CML_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2457	{ PCI_DEVICE_DATA(INTEL, HDA_RKL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2458	/* CometLake-S */2459	{ PCI_DEVICE_DATA(INTEL, HDA_CML_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2460	/* CometLake-R */2461	{ PCI_DEVICE_DATA(INTEL, HDA_CML_R, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2462	/* Icelake */2463	{ PCI_DEVICE_DATA(INTEL, HDA_ICL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2464	/* Icelake-H */2465	{ PCI_DEVICE_DATA(INTEL, HDA_ICL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2466	/* Jasperlake */2467	{ PCI_DEVICE_DATA(INTEL, HDA_ICL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2468	{ PCI_DEVICE_DATA(INTEL, HDA_JSL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2469	/* Tigerlake */2470	{ PCI_DEVICE_DATA(INTEL, HDA_TGL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2471	/* Tigerlake-H */2472	{ PCI_DEVICE_DATA(INTEL, HDA_TGL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2473	/* DG1 */2474	{ PCI_DEVICE_DATA(INTEL, HDA_DG1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2475	/* DG2 */2476	{ PCI_DEVICE_DATA(INTEL, HDA_DG2_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2477	{ PCI_DEVICE_DATA(INTEL, HDA_DG2_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2478	{ PCI_DEVICE_DATA(INTEL, HDA_DG2_2, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2479	/* Alderlake-S */2480	{ PCI_DEVICE_DATA(INTEL, HDA_ADL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2481	/* Alderlake-P */2482	{ PCI_DEVICE_DATA(INTEL, HDA_ADL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2483	{ PCI_DEVICE_DATA(INTEL, HDA_ADL_PS, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2484	{ PCI_DEVICE_DATA(INTEL, HDA_ADL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2485	/* Alderlake-M */2486	{ PCI_DEVICE_DATA(INTEL, HDA_ADL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2487	/* Alderlake-N */2488	{ PCI_DEVICE_DATA(INTEL, HDA_ADL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2489	/* Elkhart Lake */2490	{ PCI_DEVICE_DATA(INTEL, HDA_EHL_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2491	{ PCI_DEVICE_DATA(INTEL, HDA_EHL_3, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2492	/* Raptor Lake */2493	{ PCI_DEVICE_DATA(INTEL, HDA_RPL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2494	{ PCI_DEVICE_DATA(INTEL, HDA_RPL_P_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2495	{ PCI_DEVICE_DATA(INTEL, HDA_RPL_P_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2496	{ PCI_DEVICE_DATA(INTEL, HDA_RPL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2497	{ PCI_DEVICE_DATA(INTEL, HDA_RPL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2498	{ PCI_DEVICE_DATA(INTEL, HDA_MTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2499	/* Battlemage */2500	{ PCI_DEVICE_DATA(INTEL, HDA_BMG, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2501	/* Lunarlake-P */2502	{ PCI_DEVICE_DATA(INTEL, HDA_LNL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) },2503	/* Arrow Lake-S */2504	{ PCI_DEVICE_DATA(INTEL, HDA_ARL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2505	/* Arrow Lake */2506	{ PCI_DEVICE_DATA(INTEL, HDA_ARL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },2507	/* Panther Lake */2508	{ PCI_DEVICE_DATA(INTEL, HDA_PTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) },2509	/* Apollolake (Broxton-P) */2510	{ PCI_DEVICE_DATA(INTEL, HDA_APL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) },2511	/* Gemini-Lake */2512	{ PCI_DEVICE_DATA(INTEL, HDA_GML, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) },2513	/* Haswell */2514	{ PCI_DEVICE_DATA(INTEL, HDA_HSW_0, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },2515	{ PCI_DEVICE_DATA(INTEL, HDA_HSW_2, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },2516	{ PCI_DEVICE_DATA(INTEL, HDA_HSW_3, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },2517	/* Broadwell */2518	{ PCI_DEVICE_DATA(INTEL, HDA_BDW, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL) },2519	/* 5 Series/3400 */2520	{ PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_0, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) },2521	{ PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_1, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) },2522	/* Poulsbo */2523	{ PCI_DEVICE_DATA(INTEL, HDA_POULSBO, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE |2524	  AZX_DCAPS_POSFIX_LPIB) },2525	/* Oaktrail */2526	{ PCI_DEVICE_DATA(INTEL, HDA_OAKTRAIL, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE) },2527	/* BayTrail */2528	{ PCI_DEVICE_DATA(INTEL, HDA_BYT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL) },2529	/* Braswell */2530	{ PCI_DEVICE_DATA(INTEL, HDA_BSW, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL) },2531	/* ICH6 */2532	{ PCI_DEVICE_DATA(INTEL, HDA_ICH6, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },2533	/* ICH7 */2534	{ PCI_DEVICE_DATA(INTEL, HDA_ICH7, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },2535	/* ESB2 */2536	{ PCI_DEVICE_DATA(INTEL, HDA_ESB2, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },2537	/* ICH8 */2538	{ PCI_DEVICE_DATA(INTEL, HDA_ICH8, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },2539	/* ICH9 */2540	{ PCI_DEVICE_DATA(INTEL, HDA_ICH9_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },2541	/* ICH9 */2542	{ PCI_DEVICE_DATA(INTEL, HDA_ICH9_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },2543	/* ICH10 */2544	{ PCI_DEVICE_DATA(INTEL, HDA_ICH10_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },2545	/* ICH10 */2546	{ PCI_DEVICE_DATA(INTEL, HDA_ICH10_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },2547	/* Generic Intel */2548	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),2549	  .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,2550	  .class_mask = 0xffffff,2551	  .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },2552	/* ATI SB 450/600/700/800/900 */2553	{ PCI_VDEVICE(ATI, 0x437b),2554	  .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },2555	{ PCI_VDEVICE(ATI, 0x4383),2556	  .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },2557	/* AMD Hudson */2558	{ PCI_VDEVICE(AMD, 0x780d),2559	  .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },2560	/* AMD, X370 & co */2561	{ PCI_VDEVICE(AMD, 0x1457),2562	  .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },2563	/* AMD, X570 & co */2564	{ PCI_VDEVICE(AMD, 0x1487),2565	  .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },2566	/* AMD Stoney */2567	{ PCI_VDEVICE(AMD, 0x157a),2568	  .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |2569			 AZX_DCAPS_PM_RUNTIME },2570	/* AMD Raven */2571	{ PCI_VDEVICE(AMD, 0x15e3),2572	  .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },2573	/* ATI HDMI */2574	{ PCI_VDEVICE(ATI, 0x0002),2575	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |2576	  AZX_DCAPS_PM_RUNTIME },2577	{ PCI_VDEVICE(ATI, 0x1308),2578	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },2579	{ PCI_VDEVICE(ATI, 0x157a),2580	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },2581	{ PCI_VDEVICE(ATI, 0x15b3),2582	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },2583	{ PCI_VDEVICE(ATI, 0x793b),2584	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },2585	{ PCI_VDEVICE(ATI, 0x7919),2586	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },2587	{ PCI_VDEVICE(ATI, 0x960f),2588	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },2589	{ PCI_VDEVICE(ATI, 0x970f),2590	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },2591	{ PCI_VDEVICE(ATI, 0x9840),2592	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },2593	{ PCI_VDEVICE(ATI, 0xaa00),2594	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },2595	{ PCI_VDEVICE(ATI, 0xaa08),2596	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },2597	{ PCI_VDEVICE(ATI, 0xaa10),2598	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },2599	{ PCI_VDEVICE(ATI, 0xaa18),2600	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },2601	{ PCI_VDEVICE(ATI, 0xaa20),2602	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },2603	{ PCI_VDEVICE(ATI, 0xaa28),2604	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },2605	{ PCI_VDEVICE(ATI, 0xaa30),2606	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },2607	{ PCI_VDEVICE(ATI, 0xaa38),2608	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },2609	{ PCI_VDEVICE(ATI, 0xaa40),2610	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },2611	{ PCI_VDEVICE(ATI, 0xaa48),2612	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },2613	{ PCI_VDEVICE(ATI, 0xaa50),2614	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },2615	{ PCI_VDEVICE(ATI, 0xaa58),2616	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },2617	{ PCI_VDEVICE(ATI, 0xaa60),2618	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },2619	{ PCI_VDEVICE(ATI, 0xaa68),2620	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },2621	{ PCI_VDEVICE(ATI, 0xaa80),2622	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },2623	{ PCI_VDEVICE(ATI, 0xaa88),2624	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },2625	{ PCI_VDEVICE(ATI, 0xaa90),2626	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },2627	{ PCI_VDEVICE(ATI, 0xaa98),2628	  .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },2629	{ PCI_VDEVICE(ATI, 0x9902),2630	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },2631	{ PCI_VDEVICE(ATI, 0xaaa0),2632	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },2633	{ PCI_VDEVICE(ATI, 0xaaa8),2634	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },2635	{ PCI_VDEVICE(ATI, 0xaab0),2636	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },2637	{ PCI_VDEVICE(ATI, 0xaac0),2638	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |2639	  AZX_DCAPS_PM_RUNTIME },2640	{ PCI_VDEVICE(ATI, 0xaac8),2641	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |2642	  AZX_DCAPS_PM_RUNTIME },2643	{ PCI_VDEVICE(ATI, 0xaad8),2644	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |2645	  AZX_DCAPS_PM_RUNTIME },2646	{ PCI_VDEVICE(ATI, 0xaae0),2647	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |2648	  AZX_DCAPS_PM_RUNTIME },2649	{ PCI_VDEVICE(ATI, 0xaae8),2650	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |2651	  AZX_DCAPS_PM_RUNTIME },2652	{ PCI_VDEVICE(ATI, 0xaaf0),2653	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |2654	  AZX_DCAPS_PM_RUNTIME },2655	{ PCI_VDEVICE(ATI, 0xaaf8),2656	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |2657	  AZX_DCAPS_PM_RUNTIME },2658	{ PCI_VDEVICE(ATI, 0xab00),2659	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |2660	  AZX_DCAPS_PM_RUNTIME },2661	{ PCI_VDEVICE(ATI, 0xab08),2662	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |2663	  AZX_DCAPS_PM_RUNTIME },2664	{ PCI_VDEVICE(ATI, 0xab10),2665	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |2666	  AZX_DCAPS_PM_RUNTIME },2667	{ PCI_VDEVICE(ATI, 0xab18),2668	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |2669	  AZX_DCAPS_PM_RUNTIME },2670	{ PCI_VDEVICE(ATI, 0xab20),2671	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |2672	  AZX_DCAPS_PM_RUNTIME },2673	{ PCI_VDEVICE(ATI, 0xab28),2674	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |2675	  AZX_DCAPS_PM_RUNTIME },2676	{ PCI_VDEVICE(ATI, 0xab30),2677	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |2678	  AZX_DCAPS_PM_RUNTIME },2679	{ PCI_VDEVICE(ATI, 0xab38),2680	  .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |2681	  AZX_DCAPS_PM_RUNTIME },2682	/* GLENFLY */2683	{ PCI_DEVICE(PCI_VENDOR_ID_GLENFLY, PCI_ANY_ID),2684	  .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,2685	  .class_mask = 0xffffff,2686	  .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB |2687	  AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },2688	/* VIA VT8251/VT8237A */2689	{ PCI_VDEVICE(VIA, 0x3288), .driver_data = AZX_DRIVER_VIA },2690	/* VIA GFX VT7122/VX900 */2691	{ PCI_VDEVICE(VIA, 0x9170), .driver_data = AZX_DRIVER_GENERIC },2692	/* VIA GFX VT6122/VX11 */2693	{ PCI_VDEVICE(VIA, 0x9140), .driver_data = AZX_DRIVER_GENERIC },2694	/* SIS966 */2695	{ PCI_VDEVICE(SI, 0x7502), .driver_data = AZX_DRIVER_SIS },2696	/* ULI M5461 */2697	{ PCI_VDEVICE(AL, 0x5461), .driver_data = AZX_DRIVER_ULI },2698	/* NVIDIA MCP */2699	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),2700	  .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,2701	  .class_mask = 0xffffff,2702	  .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },2703	/* Teradici */2704	{ PCI_DEVICE(0x6549, 0x1200),2705	  .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },2706	{ PCI_DEVICE(0x6549, 0x2200),2707	  .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },2708	/* Creative X-Fi (CA0110-IBG) */2709	/* CTHDA chips */2710	{ PCI_VDEVICE(CREATIVE, 0x0010),2711	  .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },2712	{ PCI_VDEVICE(CREATIVE, 0x0012),2713	  .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },2714#if !IS_ENABLED(CONFIG_SND_CTXFI)2715	/* the following entry conflicts with snd-ctxfi driver,2716	 * as ctxfi driver mutates from HD-audio to native mode with2717	 * a special command sequence.2718	 */2719	{ PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),2720	  .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,2721	  .class_mask = 0xffffff,2722	  .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |2723	  AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },2724#else2725	/* this entry seems still valid -- i.e. without emu20kx chip */2726	{ PCI_VDEVICE(CREATIVE, 0x0009),2727	  .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |2728	  AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },2729#endif2730	/* CM8888 */2731	{ PCI_VDEVICE(CMEDIA, 0x5011),2732	  .driver_data = AZX_DRIVER_CMEDIA |2733	  AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },2734	/* Vortex86MX */2735	{ PCI_VDEVICE(RDC, 0x3010), .driver_data = AZX_DRIVER_GENERIC },2736	/* VMware HDAudio */2737	{ PCI_VDEVICE(VMWARE, 0x1977), .driver_data = AZX_DRIVER_GENERIC },2738	/* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */2739	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),2740	  .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,2741	  .class_mask = 0xffffff,2742	  .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },2743	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),2744	  .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,2745	  .class_mask = 0xffffff,2746	  .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },2747	/* Zhaoxin */2748	{ PCI_VDEVICE(ZHAOXIN, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },2749	/* Loongson HDAudio*/2750	{ PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDA),2751	  .driver_data = AZX_DRIVER_LOONGSON },2752	{ PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDMI),2753	  .driver_data = AZX_DRIVER_LOONGSON },2754	{ 0, }2755};2756MODULE_DEVICE_TABLE(pci, azx_ids);2757 2758/* pci_driver definition */2759static struct pci_driver azx_driver = {2760	.name = KBUILD_MODNAME,2761	.id_table = azx_ids,2762	.probe = azx_probe,2763	.remove = azx_remove,2764	.shutdown = azx_shutdown,2765	.driver = {2766		.pm = &azx_pm,2767	},2768};2769 2770module_pci_driver(azx_driver);2771