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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * ALSA driver for ICEnsemble VT1724 (Envy24HT)4 *5 * Lowlevel functions for Infrasonic Quartet6 *7 * Copyright (c) 2009 Pavel Hofman <pavel.hofman@ivitera.com>8 */9 10#include <linux/delay.h>11#include <linux/interrupt.h>12#include <linux/init.h>13#include <linux/slab.h>14#include <linux/string.h>15#include <sound/core.h>16#include <sound/tlv.h>17#include <sound/info.h>18 19#include "ice1712.h"20#include "envy24ht.h"21#include <sound/ak4113.h>22#include "quartet.h"23 24struct qtet_spec {25 struct ak4113 *ak4113;26 unsigned int scr; /* system control register */27 unsigned int mcr; /* monitoring control register */28 unsigned int cpld; /* cpld register */29};30 31struct qtet_kcontrol_private {32 unsigned int bit;33 void (*set_register)(struct snd_ice1712 *ice, unsigned int val);34 unsigned int (*get_register)(struct snd_ice1712 *ice);35 const char * const texts[2];36};37 38enum {39 IN12_SEL = 0,40 IN34_SEL,41 AIN34_SEL,42 COAX_OUT,43 IN12_MON12,44 IN12_MON34,45 IN34_MON12,46 IN34_MON34,47 OUT12_MON34,48 OUT34_MON12,49};50 51static const char * const ext_clock_names[3] = {"IEC958 In", "Word Clock 1xFS",52 "Word Clock 256xFS"};53 54/* chip address on I2C bus */55#define AK4113_ADDR 0x26 /* S/PDIF receiver */56 57/* chip address on SPI bus */58#define AK4620_ADDR 0x02 /* ADC/DAC */59 60 61/*62 * GPIO pins63 */64 65/* GPIO0 - O - DATA0, def. 0 */66#define GPIO_D0 (1<<0)67/* GPIO1 - I/O - DATA1, Jack Detect Input0 (0:present, 1:missing), def. 1 */68#define GPIO_D1_JACKDTC0 (1<<1)69/* GPIO2 - I/O - DATA2, Jack Detect Input1 (0:present, 1:missing), def. 1 */70#define GPIO_D2_JACKDTC1 (1<<2)71/* GPIO3 - I/O - DATA3, def. 1 */72#define GPIO_D3 (1<<3)73/* GPIO4 - I/O - DATA4, SPI CDTO, def. 1 */74#define GPIO_D4_SPI_CDTO (1<<4)75/* GPIO5 - I/O - DATA5, SPI CCLK, def. 1 */76#define GPIO_D5_SPI_CCLK (1<<5)77/* GPIO6 - I/O - DATA6, Cable Detect Input (0:detected, 1:not detected */78#define GPIO_D6_CD (1<<6)79/* GPIO7 - I/O - DATA7, Device Detect Input (0:detected, 1:not detected */80#define GPIO_D7_DD (1<<7)81/* GPIO8 - O - CPLD Chip Select, def. 1 */82#define GPIO_CPLD_CSN (1<<8)83/* GPIO9 - O - CPLD register read/write (0:write, 1:read), def. 0 */84#define GPIO_CPLD_RW (1<<9)85/* GPIO10 - O - SPI Chip Select for CODEC#0, def. 1 */86#define GPIO_SPI_CSN0 (1<<10)87/* GPIO11 - O - SPI Chip Select for CODEC#1, def. 1 */88#define GPIO_SPI_CSN1 (1<<11)89/* GPIO12 - O - Ex. Register Output Enable (0:enable, 1:disable), def. 1,90 * init 0 */91#define GPIO_EX_GPIOE (1<<12)92/* GPIO13 - O - Ex. Register0 Chip Select for System Control Register,93 * def. 1 */94#define GPIO_SCR (1<<13)95/* GPIO14 - O - Ex. Register1 Chip Select for Monitor Control Register,96 * def. 1 */97#define GPIO_MCR (1<<14)98 99#define GPIO_SPI_ALL (GPIO_D4_SPI_CDTO | GPIO_D5_SPI_CCLK |\100 GPIO_SPI_CSN0 | GPIO_SPI_CSN1)101 102#define GPIO_DATA_MASK (GPIO_D0 | GPIO_D1_JACKDTC0 | \103 GPIO_D2_JACKDTC1 | GPIO_D3 | \104 GPIO_D4_SPI_CDTO | GPIO_D5_SPI_CCLK | \105 GPIO_D6_CD | GPIO_D7_DD)106 107/* System Control Register GPIO_SCR data bits */108/* Mic/Line select relay (0:line, 1:mic) */109#define SCR_RELAY GPIO_D0110/* Phantom power drive control (0:5V, 1:48V) */111#define SCR_PHP_V GPIO_D1_JACKDTC0112/* H/W mute control (0:Normal, 1:Mute) */113#define SCR_MUTE GPIO_D2_JACKDTC1114/* Phantom power control (0:Phantom on, 1:off) */115#define SCR_PHP GPIO_D3116/* Analog input 1/2 Source Select */117#define SCR_AIN12_SEL0 GPIO_D4_SPI_CDTO118#define SCR_AIN12_SEL1 GPIO_D5_SPI_CCLK119/* Analog input 3/4 Source Select (0:line, 1:hi-z) */120#define SCR_AIN34_SEL GPIO_D6_CD121/* Codec Power Down (0:power down, 1:normal) */122#define SCR_CODEC_PDN GPIO_D7_DD123 124#define SCR_AIN12_LINE (0)125#define SCR_AIN12_MIC (SCR_AIN12_SEL0)126#define SCR_AIN12_LOWCUT (SCR_AIN12_SEL1 | SCR_AIN12_SEL0)127 128/* Monitor Control Register GPIO_MCR data bits */129/* Input 1/2 to Monitor 1/2 (0:off, 1:on) */130#define MCR_IN12_MON12 GPIO_D0131/* Input 1/2 to Monitor 3/4 (0:off, 1:on) */132#define MCR_IN12_MON34 GPIO_D1_JACKDTC0133/* Input 3/4 to Monitor 1/2 (0:off, 1:on) */134#define MCR_IN34_MON12 GPIO_D2_JACKDTC1135/* Input 3/4 to Monitor 3/4 (0:off, 1:on) */136#define MCR_IN34_MON34 GPIO_D3137/* Output to Monitor 1/2 (0:off, 1:on) */138#define MCR_OUT34_MON12 GPIO_D4_SPI_CDTO139/* Output to Monitor 3/4 (0:off, 1:on) */140#define MCR_OUT12_MON34 GPIO_D5_SPI_CCLK141 142/* CPLD Register DATA bits */143/* Clock Rate Select */144#define CPLD_CKS0 GPIO_D0145#define CPLD_CKS1 GPIO_D1_JACKDTC0146#define CPLD_CKS2 GPIO_D2_JACKDTC1147/* Sync Source Select (0:Internal, 1:External) */148#define CPLD_SYNC_SEL GPIO_D3149/* Word Clock FS Select (0:FS, 1:256FS) */150#define CPLD_WORD_SEL GPIO_D4_SPI_CDTO151/* Coaxial Output Source (IS-Link) (0:SPDIF, 1:I2S) */152#define CPLD_COAX_OUT GPIO_D5_SPI_CCLK153/* Input 1/2 Source Select (0:Analog12, 1:An34) */154#define CPLD_IN12_SEL GPIO_D6_CD155/* Input 3/4 Source Select (0:Analog34, 1:Digital In) */156#define CPLD_IN34_SEL GPIO_D7_DD157 158/* internal clock (CPLD_SYNC_SEL = 0) options */159#define CPLD_CKS_44100HZ (0)160#define CPLD_CKS_48000HZ (CPLD_CKS0)161#define CPLD_CKS_88200HZ (CPLD_CKS1)162#define CPLD_CKS_96000HZ (CPLD_CKS1 | CPLD_CKS0)163#define CPLD_CKS_176400HZ (CPLD_CKS2)164#define CPLD_CKS_192000HZ (CPLD_CKS2 | CPLD_CKS0)165 166#define CPLD_CKS_MASK (CPLD_CKS0 | CPLD_CKS1 | CPLD_CKS2)167 168/* external clock (CPLD_SYNC_SEL = 1) options */169/* external clock - SPDIF */170#define CPLD_EXT_SPDIF (0 | CPLD_SYNC_SEL)171/* external clock - WordClock 1xfs */172#define CPLD_EXT_WORDCLOCK_1FS (CPLD_CKS1 | CPLD_SYNC_SEL)173/* external clock - WordClock 256xfs */174#define CPLD_EXT_WORDCLOCK_256FS (CPLD_CKS1 | CPLD_WORD_SEL |\175 CPLD_SYNC_SEL)176 177#define EXT_SPDIF_TYPE 0178#define EXT_WORDCLOCK_1FS_TYPE 1179#define EXT_WORDCLOCK_256FS_TYPE 2180 181#define AK4620_DFS0 (1<<0)182#define AK4620_DFS1 (1<<1)183#define AK4620_CKS0 (1<<2)184#define AK4620_CKS1 (1<<3)185/* Clock and Format Control register */186#define AK4620_DFS_REG 0x02187 188/* Deem and Volume Control register */189#define AK4620_DEEMVOL_REG 0x03190#define AK4620_SMUTE (1<<7)191 192/*193 * Conversion from int value to its binary form. Used for debugging.194 * The output buffer must be allocated prior to calling the function.195 */196static char *get_binary(char *buffer, int value)197{198 int i, j, pos;199 pos = 0;200 for (i = 0; i < 4; ++i) {201 for (j = 0; j < 8; ++j) {202 if (value & (1 << (31-(i*8 + j))))203 buffer[pos] = '1';204 else205 buffer[pos] = '0';206 pos++;207 }208 if (i < 3) {209 buffer[pos] = ' ';210 pos++;211 }212 }213 buffer[pos] = '\0';214 return buffer;215}216 217/*218 * Initial setup of the conversion array GPIO <-> rate219 */220static const unsigned int qtet_rates[] = {221 44100, 48000, 88200,222 96000, 176400, 192000,223};224 225static const unsigned int cks_vals[] = {226 CPLD_CKS_44100HZ, CPLD_CKS_48000HZ, CPLD_CKS_88200HZ,227 CPLD_CKS_96000HZ, CPLD_CKS_176400HZ, CPLD_CKS_192000HZ,228};229 230static const struct snd_pcm_hw_constraint_list qtet_rates_info = {231 .count = ARRAY_SIZE(qtet_rates),232 .list = qtet_rates,233 .mask = 0,234};235 236static void qtet_ak4113_write(void *private_data, unsigned char reg,237 unsigned char val)238{239 snd_vt1724_write_i2c((struct snd_ice1712 *)private_data, AK4113_ADDR,240 reg, val);241}242 243static unsigned char qtet_ak4113_read(void *private_data, unsigned char reg)244{245 return snd_vt1724_read_i2c((struct snd_ice1712 *)private_data,246 AK4113_ADDR, reg);247}248 249 250/*251 * AK4620 section252 */253 254/*255 * Write data to addr register of ak4620256 */257static void qtet_akm_write(struct snd_akm4xxx *ak, int chip,258 unsigned char addr, unsigned char data)259{260 unsigned int tmp, orig_dir;261 int idx;262 unsigned int addrdata;263 struct snd_ice1712 *ice = ak->private_data[0];264 265 if (snd_BUG_ON(chip < 0 || chip >= 4))266 return;267 /*dev_dbg(ice->card->dev, "Writing to AK4620: chip=%d, addr=0x%x,268 data=0x%x\n", chip, addr, data);*/269 orig_dir = ice->gpio.get_dir(ice);270 ice->gpio.set_dir(ice, orig_dir | GPIO_SPI_ALL);271 /* set mask - only SPI bits */272 ice->gpio.set_mask(ice, ~GPIO_SPI_ALL);273 274 tmp = ice->gpio.get_data(ice);275 /* high all */276 tmp |= GPIO_SPI_ALL;277 ice->gpio.set_data(ice, tmp);278 udelay(100);279 /* drop chip select */280 if (chip)281 /* CODEC 1 */282 tmp &= ~GPIO_SPI_CSN1;283 else284 tmp &= ~GPIO_SPI_CSN0;285 ice->gpio.set_data(ice, tmp);286 udelay(100);287 288 /* build I2C address + data byte */289 addrdata = (AK4620_ADDR << 6) | 0x20 | (addr & 0x1f);290 addrdata = (addrdata << 8) | data;291 for (idx = 15; idx >= 0; idx--) {292 /* drop clock */293 tmp &= ~GPIO_D5_SPI_CCLK;294 ice->gpio.set_data(ice, tmp);295 udelay(100);296 /* set data */297 if (addrdata & (1 << idx))298 tmp |= GPIO_D4_SPI_CDTO;299 else300 tmp &= ~GPIO_D4_SPI_CDTO;301 ice->gpio.set_data(ice, tmp);302 udelay(100);303 /* raise clock */304 tmp |= GPIO_D5_SPI_CCLK;305 ice->gpio.set_data(ice, tmp);306 udelay(100);307 }308 /* all back to 1 */309 tmp |= GPIO_SPI_ALL;310 ice->gpio.set_data(ice, tmp);311 udelay(100);312 313 /* return all gpios to non-writable */314 ice->gpio.set_mask(ice, 0xffffff);315 /* restore GPIOs direction */316 ice->gpio.set_dir(ice, orig_dir);317}318 319static void qtet_akm_set_regs(struct snd_akm4xxx *ak, unsigned char addr,320 unsigned char mask, unsigned char value)321{322 unsigned char tmp;323 int chip;324 for (chip = 0; chip < ak->num_chips; chip++) {325 tmp = snd_akm4xxx_get(ak, chip, addr);326 /* clear the bits */327 tmp &= ~mask;328 /* set the new bits */329 tmp |= value;330 snd_akm4xxx_write(ak, chip, addr, tmp);331 }332}333 334/*335 * change the rate of AK4620336 */337static void qtet_akm_set_rate_val(struct snd_akm4xxx *ak, unsigned int rate)338{339 unsigned char ak4620_dfs;340 341 if (rate == 0) /* no hint - S/PDIF input is master or the new spdif342 input rate undetected, simply return */343 return;344 345 /* adjust DFS on codecs - see datasheet */346 if (rate > 108000)347 ak4620_dfs = AK4620_DFS1 | AK4620_CKS1;348 else if (rate > 54000)349 ak4620_dfs = AK4620_DFS0 | AK4620_CKS0;350 else351 ak4620_dfs = 0;352 353 /* set new value */354 qtet_akm_set_regs(ak, AK4620_DFS_REG, AK4620_DFS0 | AK4620_DFS1 |355 AK4620_CKS0 | AK4620_CKS1, ak4620_dfs);356}357 358#define AK_CONTROL(xname, xch) { .name = xname, .num_channels = xch }359 360#define PCM_12_PLAYBACK_VOLUME "PCM 1/2 Playback Volume"361#define PCM_34_PLAYBACK_VOLUME "PCM 3/4 Playback Volume"362#define PCM_12_CAPTURE_VOLUME "PCM 1/2 Capture Volume"363#define PCM_34_CAPTURE_VOLUME "PCM 3/4 Capture Volume"364 365static const struct snd_akm4xxx_dac_channel qtet_dac[] = {366 AK_CONTROL(PCM_12_PLAYBACK_VOLUME, 2),367 AK_CONTROL(PCM_34_PLAYBACK_VOLUME, 2),368};369 370static const struct snd_akm4xxx_adc_channel qtet_adc[] = {371 AK_CONTROL(PCM_12_CAPTURE_VOLUME, 2),372 AK_CONTROL(PCM_34_CAPTURE_VOLUME, 2),373};374 375static const struct snd_akm4xxx akm_qtet_dac = {376 .type = SND_AK4620,377 .num_dacs = 4, /* DAC1 - Output 12378 */379 .num_adcs = 4, /* ADC1 - Input 12380 */381 .ops = {382 .write = qtet_akm_write,383 .set_rate_val = qtet_akm_set_rate_val,384 },385 .dac_info = qtet_dac,386 .adc_info = qtet_adc,387};388 389/* Communication routines with the CPLD */390 391 392/* Writes data to external register reg, both reg and data are393 * GPIO representations */394static void reg_write(struct snd_ice1712 *ice, unsigned int reg,395 unsigned int data)396{397 unsigned int tmp;398 399 mutex_lock(&ice->gpio_mutex);400 /* set direction of used GPIOs*/401 /* all outputs */402 tmp = 0x00ffff;403 ice->gpio.set_dir(ice, tmp);404 /* mask - writable bits */405 ice->gpio.set_mask(ice, ~(tmp));406 /* write the data */407 tmp = ice->gpio.get_data(ice);408 tmp &= ~GPIO_DATA_MASK;409 tmp |= data;410 ice->gpio.set_data(ice, tmp);411 udelay(100);412 /* drop output enable */413 tmp &= ~GPIO_EX_GPIOE;414 ice->gpio.set_data(ice, tmp);415 udelay(100);416 /* drop the register gpio */417 tmp &= ~reg;418 ice->gpio.set_data(ice, tmp);419 udelay(100);420 /* raise the register GPIO */421 tmp |= reg;422 ice->gpio.set_data(ice, tmp);423 udelay(100);424 425 /* raise all data gpios */426 tmp |= GPIO_DATA_MASK;427 ice->gpio.set_data(ice, tmp);428 /* mask - immutable bits */429 ice->gpio.set_mask(ice, 0xffffff);430 /* outputs only 8-15 */431 ice->gpio.set_dir(ice, 0x00ff00);432 mutex_unlock(&ice->gpio_mutex);433}434 435static unsigned int get_scr(struct snd_ice1712 *ice)436{437 struct qtet_spec *spec = ice->spec;438 return spec->scr;439}440 441static unsigned int get_mcr(struct snd_ice1712 *ice)442{443 struct qtet_spec *spec = ice->spec;444 return spec->mcr;445}446 447static unsigned int get_cpld(struct snd_ice1712 *ice)448{449 struct qtet_spec *spec = ice->spec;450 return spec->cpld;451}452 453static void set_scr(struct snd_ice1712 *ice, unsigned int val)454{455 struct qtet_spec *spec = ice->spec;456 reg_write(ice, GPIO_SCR, val);457 spec->scr = val;458}459 460static void set_mcr(struct snd_ice1712 *ice, unsigned int val)461{462 struct qtet_spec *spec = ice->spec;463 reg_write(ice, GPIO_MCR, val);464 spec->mcr = val;465}466 467static void set_cpld(struct snd_ice1712 *ice, unsigned int val)468{469 struct qtet_spec *spec = ice->spec;470 reg_write(ice, GPIO_CPLD_CSN, val);471 spec->cpld = val;472}473 474static void proc_regs_read(struct snd_info_entry *entry,475 struct snd_info_buffer *buffer)476{477 struct snd_ice1712 *ice = entry->private_data;478 char bin_buffer[36];479 480 snd_iprintf(buffer, "SCR: %s\n", get_binary(bin_buffer,481 get_scr(ice)));482 snd_iprintf(buffer, "MCR: %s\n", get_binary(bin_buffer,483 get_mcr(ice)));484 snd_iprintf(buffer, "CPLD: %s\n", get_binary(bin_buffer,485 get_cpld(ice)));486}487 488static void proc_init(struct snd_ice1712 *ice)489{490 snd_card_ro_proc_new(ice->card, "quartet", ice, proc_regs_read);491}492 493static int qtet_mute_get(struct snd_kcontrol *kcontrol,494 struct snd_ctl_elem_value *ucontrol)495{496 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);497 unsigned int val;498 val = get_scr(ice) & SCR_MUTE;499 ucontrol->value.integer.value[0] = (val) ? 0 : 1;500 return 0;501}502 503static int qtet_mute_put(struct snd_kcontrol *kcontrol,504 struct snd_ctl_elem_value *ucontrol)505{506 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);507 unsigned int old, new, smute;508 old = get_scr(ice) & SCR_MUTE;509 if (ucontrol->value.integer.value[0]) {510 /* unmute */511 new = 0;512 /* un-smuting DAC */513 smute = 0;514 } else {515 /* mute */516 new = SCR_MUTE;517 /* smuting DAC */518 smute = AK4620_SMUTE;519 }520 if (old != new) {521 struct snd_akm4xxx *ak = ice->akm;522 set_scr(ice, (get_scr(ice) & ~SCR_MUTE) | new);523 /* set smute */524 qtet_akm_set_regs(ak, AK4620_DEEMVOL_REG, AK4620_SMUTE, smute);525 return 1;526 }527 /* no change */528 return 0;529}530 531static int qtet_ain12_enum_info(struct snd_kcontrol *kcontrol,532 struct snd_ctl_elem_info *uinfo)533{534 static const char * const texts[3] =535 {"Line In 1/2", "Mic", "Mic + Low-cut"};536 return snd_ctl_enum_info(uinfo, 1, ARRAY_SIZE(texts), texts);537}538 539static int qtet_ain12_sw_get(struct snd_kcontrol *kcontrol,540 struct snd_ctl_elem_value *ucontrol)541{542 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);543 unsigned int val, result;544 val = get_scr(ice) & (SCR_AIN12_SEL1 | SCR_AIN12_SEL0);545 switch (val) {546 case SCR_AIN12_LINE:547 result = 0;548 break;549 case SCR_AIN12_MIC:550 result = 1;551 break;552 case SCR_AIN12_LOWCUT:553 result = 2;554 break;555 default:556 /* BUG - no other combinations allowed */557 snd_BUG();558 result = 0;559 }560 ucontrol->value.integer.value[0] = result;561 return 0;562}563 564static int qtet_ain12_sw_put(struct snd_kcontrol *kcontrol,565 struct snd_ctl_elem_value *ucontrol)566{567 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);568 unsigned int old, new, tmp, masked_old;569 old = get_scr(ice);570 masked_old = old & (SCR_AIN12_SEL1 | SCR_AIN12_SEL0);571 tmp = ucontrol->value.integer.value[0];572 if (tmp == 2)573 tmp = 3; /* binary 10 is not supported */574 tmp <<= 4; /* shifting to SCR_AIN12_SEL0 */575 if (tmp != masked_old) {576 /* change requested */577 switch (tmp) {578 case SCR_AIN12_LINE:579 new = old & ~(SCR_AIN12_SEL1 | SCR_AIN12_SEL0);580 set_scr(ice, new);581 /* turn off relay */582 new &= ~SCR_RELAY;583 set_scr(ice, new);584 break;585 case SCR_AIN12_MIC:586 /* turn on relay */587 new = old | SCR_RELAY;588 set_scr(ice, new);589 new = (new & ~SCR_AIN12_SEL1) | SCR_AIN12_SEL0;590 set_scr(ice, new);591 break;592 case SCR_AIN12_LOWCUT:593 /* turn on relay */594 new = old | SCR_RELAY;595 set_scr(ice, new);596 new |= SCR_AIN12_SEL1 | SCR_AIN12_SEL0;597 set_scr(ice, new);598 break;599 default:600 snd_BUG();601 }602 return 1;603 }604 /* no change */605 return 0;606}607 608static int qtet_php_get(struct snd_kcontrol *kcontrol,609 struct snd_ctl_elem_value *ucontrol)610{611 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);612 unsigned int val;613 /* if phantom voltage =48V, phantom on */614 val = get_scr(ice) & SCR_PHP_V;615 ucontrol->value.integer.value[0] = val ? 1 : 0;616 return 0;617}618 619static int qtet_php_put(struct snd_kcontrol *kcontrol,620 struct snd_ctl_elem_value *ucontrol)621{622 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);623 unsigned int old, new;624 old = new = get_scr(ice);625 if (ucontrol->value.integer.value[0] /* phantom on requested */626 && (~old & SCR_PHP_V)) /* 0 = voltage 5V */ {627 /* is off, turn on */628 /* turn voltage on first, = 1 */629 new = old | SCR_PHP_V;630 set_scr(ice, new);631 /* turn phantom on, = 0 */632 new &= ~SCR_PHP;633 set_scr(ice, new);634 } else if (!ucontrol->value.integer.value[0] && (old & SCR_PHP_V)) {635 /* phantom off requested and 1 = voltage 48V */636 /* is on, turn off */637 /* turn voltage off first, = 0 */638 new = old & ~SCR_PHP_V;639 set_scr(ice, new);640 /* turn phantom off, = 1 */641 new |= SCR_PHP;642 set_scr(ice, new);643 }644 if (old != new)645 return 1;646 /* no change */647 return 0;648}649 650#define PRIV_SW(xid, xbit, xreg) [xid] = {.bit = xbit,\651 .set_register = set_##xreg,\652 .get_register = get_##xreg, }653 654 655#define PRIV_ENUM2(xid, xbit, xreg, xtext1, xtext2) [xid] = {.bit = xbit,\656 .set_register = set_##xreg,\657 .get_register = get_##xreg,\658 .texts = {xtext1, xtext2} }659 660static const struct qtet_kcontrol_private qtet_privates[] = {661 PRIV_ENUM2(IN12_SEL, CPLD_IN12_SEL, cpld, "An In 1/2", "An In 3/4"),662 PRIV_ENUM2(IN34_SEL, CPLD_IN34_SEL, cpld, "An In 3/4", "IEC958 In"),663 PRIV_ENUM2(AIN34_SEL, SCR_AIN34_SEL, scr, "Line In 3/4", "Hi-Z"),664 PRIV_ENUM2(COAX_OUT, CPLD_COAX_OUT, cpld, "IEC958", "I2S"),665 PRIV_SW(IN12_MON12, MCR_IN12_MON12, mcr),666 PRIV_SW(IN12_MON34, MCR_IN12_MON34, mcr),667 PRIV_SW(IN34_MON12, MCR_IN34_MON12, mcr),668 PRIV_SW(IN34_MON34, MCR_IN34_MON34, mcr),669 PRIV_SW(OUT12_MON34, MCR_OUT12_MON34, mcr),670 PRIV_SW(OUT34_MON12, MCR_OUT34_MON12, mcr),671};672 673static int qtet_enum_info(struct snd_kcontrol *kcontrol,674 struct snd_ctl_elem_info *uinfo)675{676 struct qtet_kcontrol_private private =677 qtet_privates[kcontrol->private_value];678 return snd_ctl_enum_info(uinfo, 1, ARRAY_SIZE(private.texts),679 private.texts);680}681 682static int qtet_sw_get(struct snd_kcontrol *kcontrol,683 struct snd_ctl_elem_value *ucontrol)684{685 struct qtet_kcontrol_private private =686 qtet_privates[kcontrol->private_value];687 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);688 ucontrol->value.integer.value[0] =689 (private.get_register(ice) & private.bit) ? 1 : 0;690 return 0;691}692 693static int qtet_sw_put(struct snd_kcontrol *kcontrol,694 struct snd_ctl_elem_value *ucontrol)695{696 struct qtet_kcontrol_private private =697 qtet_privates[kcontrol->private_value];698 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);699 unsigned int old, new;700 old = private.get_register(ice);701 if (ucontrol->value.integer.value[0])702 new = old | private.bit;703 else704 new = old & ~private.bit;705 if (old != new) {706 private.set_register(ice, new);707 return 1;708 }709 /* no change */710 return 0;711}712 713#define qtet_sw_info snd_ctl_boolean_mono_info714 715#define QTET_CONTROL(xname, xtype, xpriv) \716 {.iface = SNDRV_CTL_ELEM_IFACE_MIXER,\717 .name = xname,\718 .info = qtet_##xtype##_info,\719 .get = qtet_sw_get,\720 .put = qtet_sw_put,\721 .private_value = xpriv }722 723static const struct snd_kcontrol_new qtet_controls[] = {724 {725 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,726 .name = "Master Playback Switch",727 .info = qtet_sw_info,728 .get = qtet_mute_get,729 .put = qtet_mute_put,730 .private_value = 0731 },732 {733 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,734 .name = "Phantom Power",735 .info = qtet_sw_info,736 .get = qtet_php_get,737 .put = qtet_php_put,738 .private_value = 0739 },740 {741 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,742 .name = "Analog In 1/2 Capture Switch",743 .info = qtet_ain12_enum_info,744 .get = qtet_ain12_sw_get,745 .put = qtet_ain12_sw_put,746 .private_value = 0747 },748 QTET_CONTROL("Analog In 3/4 Capture Switch", enum, AIN34_SEL),749 QTET_CONTROL("PCM In 1/2 Capture Switch", enum, IN12_SEL),750 QTET_CONTROL("PCM In 3/4 Capture Switch", enum, IN34_SEL),751 QTET_CONTROL("Coax Output Source", enum, COAX_OUT),752 QTET_CONTROL("Analog In 1/2 to Monitor 1/2", sw, IN12_MON12),753 QTET_CONTROL("Analog In 1/2 to Monitor 3/4", sw, IN12_MON34),754 QTET_CONTROL("Analog In 3/4 to Monitor 1/2", sw, IN34_MON12),755 QTET_CONTROL("Analog In 3/4 to Monitor 3/4", sw, IN34_MON34),756 QTET_CONTROL("Output 1/2 to Monitor 3/4", sw, OUT12_MON34),757 QTET_CONTROL("Output 3/4 to Monitor 1/2", sw, OUT34_MON12),758};759 760static const char * const follower_vols[] = {761 PCM_12_PLAYBACK_VOLUME,762 PCM_34_PLAYBACK_VOLUME,763 NULL764};765 766static767DECLARE_TLV_DB_SCALE(qtet_master_db_scale, -6350, 50, 1);768 769static int qtet_add_controls(struct snd_ice1712 *ice)770{771 struct qtet_spec *spec = ice->spec;772 int err, i;773 struct snd_kcontrol *vmaster;774 err = snd_ice1712_akm4xxx_build_controls(ice);775 if (err < 0)776 return err;777 for (i = 0; i < ARRAY_SIZE(qtet_controls); i++) {778 err = snd_ctl_add(ice->card,779 snd_ctl_new1(&qtet_controls[i], ice));780 if (err < 0)781 return err;782 }783 784 /* Create virtual master control */785 vmaster = snd_ctl_make_virtual_master("Master Playback Volume",786 qtet_master_db_scale);787 if (!vmaster)788 return -ENOMEM;789 err = snd_ctl_add(ice->card, vmaster);790 if (err < 0)791 return err;792 err = snd_ctl_add_followers(ice->card, vmaster, follower_vols);793 if (err < 0)794 return err;795 /* only capture SPDIF over AK4113 */796 return snd_ak4113_build(spec->ak4113,797 ice->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);798}799 800static inline int qtet_is_spdif_master(struct snd_ice1712 *ice)801{802 /* CPLD_SYNC_SEL: 0 = internal, 1 = external (i.e. spdif master) */803 return (get_cpld(ice) & CPLD_SYNC_SEL) ? 1 : 0;804}805 806static unsigned int qtet_get_rate(struct snd_ice1712 *ice)807{808 int i;809 unsigned char result;810 811 result = get_cpld(ice) & CPLD_CKS_MASK;812 for (i = 0; i < ARRAY_SIZE(cks_vals); i++)813 if (cks_vals[i] == result)814 return qtet_rates[i];815 return 0;816}817 818static int get_cks_val(int rate)819{820 int i;821 for (i = 0; i < ARRAY_SIZE(qtet_rates); i++)822 if (qtet_rates[i] == rate)823 return cks_vals[i];824 return 0;825}826 827/* setting new rate */828static void qtet_set_rate(struct snd_ice1712 *ice, unsigned int rate)829{830 unsigned int new;831 unsigned char val;832 /* switching ice1724 to external clock - supplied by ext. circuits */833 val = inb(ICEMT1724(ice, RATE));834 outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));835 836 new = (get_cpld(ice) & ~CPLD_CKS_MASK) | get_cks_val(rate);837 /* switch to internal clock, drop CPLD_SYNC_SEL */838 new &= ~CPLD_SYNC_SEL;839 /* dev_dbg(ice->card->dev, "QT - set_rate: old %x, new %x\n",840 get_cpld(ice), new); */841 set_cpld(ice, new);842}843 844static inline unsigned char qtet_set_mclk(struct snd_ice1712 *ice,845 unsigned int rate)846{847 /* no change in master clock */848 return 0;849}850 851/* setting clock to external - SPDIF */852static int qtet_set_spdif_clock(struct snd_ice1712 *ice, int type)853{854 unsigned int old, new;855 856 old = new = get_cpld(ice);857 new &= ~(CPLD_CKS_MASK | CPLD_WORD_SEL);858 switch (type) {859 case EXT_SPDIF_TYPE:860 new |= CPLD_EXT_SPDIF;861 break;862 case EXT_WORDCLOCK_1FS_TYPE:863 new |= CPLD_EXT_WORDCLOCK_1FS;864 break;865 case EXT_WORDCLOCK_256FS_TYPE:866 new |= CPLD_EXT_WORDCLOCK_256FS;867 break;868 default:869 snd_BUG();870 }871 if (old != new) {872 set_cpld(ice, new);873 /* changed */874 return 1;875 }876 return 0;877}878 879static int qtet_get_spdif_master_type(struct snd_ice1712 *ice)880{881 unsigned int val;882 int result;883 val = get_cpld(ice);884 /* checking only rate/clock-related bits */885 val &= (CPLD_CKS_MASK | CPLD_WORD_SEL | CPLD_SYNC_SEL);886 if (!(val & CPLD_SYNC_SEL)) {887 /* switched to internal clock, is not any external type */888 result = -1;889 } else {890 switch (val) {891 case (CPLD_EXT_SPDIF):892 result = EXT_SPDIF_TYPE;893 break;894 case (CPLD_EXT_WORDCLOCK_1FS):895 result = EXT_WORDCLOCK_1FS_TYPE;896 break;897 case (CPLD_EXT_WORDCLOCK_256FS):898 result = EXT_WORDCLOCK_256FS_TYPE;899 break;900 default:901 /* undefined combination of external clock setup */902 snd_BUG();903 result = 0;904 }905 }906 return result;907}908 909/* Called when ak4113 detects change in the input SPDIF stream */910static void qtet_ak4113_change(struct ak4113 *ak4113, unsigned char c0,911 unsigned char c1)912{913 struct snd_ice1712 *ice = ak4113->change_callback_private;914 int rate;915 if ((qtet_get_spdif_master_type(ice) == EXT_SPDIF_TYPE) &&916 c1) {917 /* only for SPDIF master mode, rate was changed */918 rate = snd_ak4113_external_rate(ak4113);919 /* dev_dbg(ice->card->dev, "ak4113 - input rate changed to %d\n",920 rate); */921 qtet_akm_set_rate_val(ice->akm, rate);922 }923}924 925/*926 * If clock slaved to SPDIF-IN, setting runtime rate927 * to the detected external rate928 */929static void qtet_spdif_in_open(struct snd_ice1712 *ice,930 struct snd_pcm_substream *substream)931{932 struct qtet_spec *spec = ice->spec;933 struct snd_pcm_runtime *runtime = substream->runtime;934 int rate;935 936 if (qtet_get_spdif_master_type(ice) != EXT_SPDIF_TYPE)937 /* not external SPDIF, no rate limitation */938 return;939 /* only external SPDIF can detect incoming sample rate */940 rate = snd_ak4113_external_rate(spec->ak4113);941 if (rate >= runtime->hw.rate_min && rate <= runtime->hw.rate_max) {942 runtime->hw.rate_min = rate;943 runtime->hw.rate_max = rate;944 }945}946 947/*948 * initialize the chip949 */950static int qtet_init(struct snd_ice1712 *ice)951{952 static const unsigned char ak4113_init_vals[] = {953 /* AK4113_REG_PWRDN */ AK4113_RST | AK4113_PWN |954 AK4113_OCKS0 | AK4113_OCKS1,955 /* AK4113_REQ_FORMAT */ AK4113_DIF_I24I2S | AK4113_VTX |956 AK4113_DEM_OFF | AK4113_DEAU,957 /* AK4113_REG_IO0 */ AK4113_OPS2 | AK4113_TXE |958 AK4113_XTL_24_576M,959 /* AK4113_REG_IO1 */ AK4113_EFH_1024LRCLK | AK4113_IPS(0),960 /* AK4113_REG_INT0_MASK */ 0,961 /* AK4113_REG_INT1_MASK */ 0,962 /* AK4113_REG_DATDTS */ 0,963 };964 int err;965 struct qtet_spec *spec;966 struct snd_akm4xxx *ak;967 unsigned char val;968 969 /* switching ice1724 to external clock - supplied by ext. circuits */970 val = inb(ICEMT1724(ice, RATE));971 outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));972 973 spec = kzalloc(sizeof(*spec), GFP_KERNEL);974 if (!spec)975 return -ENOMEM;976 /* qtet is clocked by Xilinx array */977 ice->hw_rates = &qtet_rates_info;978 ice->is_spdif_master = qtet_is_spdif_master;979 ice->get_rate = qtet_get_rate;980 ice->set_rate = qtet_set_rate;981 ice->set_mclk = qtet_set_mclk;982 ice->set_spdif_clock = qtet_set_spdif_clock;983 ice->get_spdif_master_type = qtet_get_spdif_master_type;984 ice->ext_clock_names = ext_clock_names;985 ice->ext_clock_count = ARRAY_SIZE(ext_clock_names);986 /* since Qtet can detect correct SPDIF-in rate, all streams can be987 * limited to this specific rate */988 ice->spdif.ops.open = ice->pro_open = qtet_spdif_in_open;989 ice->spec = spec;990 991 /* Mute Off */992 /* SCR Initialize*/993 /* keep codec power down first */994 set_scr(ice, SCR_PHP);995 udelay(1);996 /* codec power up */997 set_scr(ice, SCR_PHP | SCR_CODEC_PDN);998 999 /* MCR Initialize */1000 set_mcr(ice, 0);1001 1002 /* CPLD Initialize */1003 set_cpld(ice, 0);1004 1005 1006 ice->num_total_dacs = 2;1007 ice->num_total_adcs = 2;1008 1009 ice->akm = kcalloc(2, sizeof(struct snd_akm4xxx), GFP_KERNEL);1010 ak = ice->akm;1011 if (!ak)1012 return -ENOMEM;1013 /* only one codec with two chips */1014 ice->akm_codecs = 1;1015 err = snd_ice1712_akm4xxx_init(ak, &akm_qtet_dac, NULL, ice);1016 if (err < 0)1017 return err;1018 err = snd_ak4113_create(ice->card,1019 qtet_ak4113_read,1020 qtet_ak4113_write,1021 ak4113_init_vals,1022 ice, &spec->ak4113);1023 if (err < 0)1024 return err;1025 /* callback for codecs rate setting */1026 spec->ak4113->change_callback = qtet_ak4113_change;1027 spec->ak4113->change_callback_private = ice;1028 /* AK41143 in Quartet can detect external rate correctly1029 * (i.e. check_flags = 0) */1030 spec->ak4113->check_flags = 0;1031 1032 proc_init(ice);1033 1034 qtet_set_rate(ice, 44100);1035 return 0;1036}1037 1038static const unsigned char qtet_eeprom[] = {1039 [ICE_EEP2_SYSCONF] = 0x28, /* clock 256(24MHz), mpu401, 1xADC,1040 1xDACs, SPDIF in */1041 [ICE_EEP2_ACLINK] = 0x80, /* I2S */1042 [ICE_EEP2_I2S] = 0x78, /* 96k, 24bit, 192k */1043 [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, in, out-ext */1044 [ICE_EEP2_GPIO_DIR] = 0x00, /* 0-7 inputs, switched to output1045 only during output operations */1046 [ICE_EEP2_GPIO_DIR1] = 0xff, /* 8-15 outputs */1047 [ICE_EEP2_GPIO_DIR2] = 0x00,1048 [ICE_EEP2_GPIO_MASK] = 0xff, /* changed only for OUT operations */1049 [ICE_EEP2_GPIO_MASK1] = 0x00,1050 [ICE_EEP2_GPIO_MASK2] = 0xff,1051 1052 [ICE_EEP2_GPIO_STATE] = 0x00, /* inputs */1053 [ICE_EEP2_GPIO_STATE1] = 0x7d, /* all 1, but GPIO_CPLD_RW1054 and GPIO15 always zero */1055 [ICE_EEP2_GPIO_STATE2] = 0x00, /* inputs */1056};1057 1058/* entry point */1059struct snd_ice1712_card_info snd_vt1724_qtet_cards[] = {1060 {1061 .subvendor = VT1724_SUBDEVICE_QTET,1062 .name = "Infrasonic Quartet",1063 .model = "quartet",1064 .chip_init = qtet_init,1065 .build_controls = qtet_add_controls,1066 .eeprom_size = sizeof(qtet_eeprom),1067 .eeprom_data = qtet_eeprom,1068 },1069 { } /* terminator */1070};1071