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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * ALSA modem driver for Intel ICH (i8x0) chipsets4 *5 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>6 *7 * This is modified (by Sasha Khapyorsky <sashak@alsa-project.org>) version8 * of ALSA ICH sound driver intel8x0.c .9 */ 10 11#include <linux/io.h>12#include <linux/delay.h>13#include <linux/interrupt.h>14#include <linux/init.h>15#include <linux/pci.h>16#include <linux/slab.h>17#include <linux/module.h>18#include <sound/core.h>19#include <sound/pcm.h>20#include <sound/ac97_codec.h>21#include <sound/info.h>22#include <sound/initval.h>23 24MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");25MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; "26 "SiS 7013; NVidia MCP/2/2S/3 modems");27MODULE_LICENSE("GPL");28 29static int index = -2; /* Exclude the first card */30static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */31static int ac97_clock;32 33module_param(index, int, 0444);34MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard.");35module_param(id, charp, 0444);36MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard.");37module_param(ac97_clock, int, 0444);38MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");39 40/* just for backward compatibility */41static bool enable;42module_param(enable, bool, 0444);43 44/*45 * Direct registers46 */47enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };48 49#define ICHREG(x) ICH_REG_##x50 51#define DEFINE_REGSET(name,base) \52enum { \53 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \54 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \55 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \56 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \57 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \58 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \59 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \60}61 62/* busmaster blocks */63DEFINE_REGSET(OFF, 0); /* offset */64 65/* values for each busmaster block */66 67/* LVI */68#define ICH_REG_LVI_MASK 0x1f69 70/* SR */71#define ICH_FIFOE 0x10 /* FIFO error */72#define ICH_BCIS 0x08 /* buffer completion interrupt status */73#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */74#define ICH_CELV 0x02 /* current equals last valid */75#define ICH_DCH 0x01 /* DMA controller halted */76 77/* PIV */78#define ICH_REG_PIV_MASK 0x1f /* mask */79 80/* CR */81#define ICH_IOCE 0x10 /* interrupt on completion enable */82#define ICH_FEIE 0x08 /* fifo error interrupt enable */83#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */84#define ICH_RESETREGS 0x02 /* reset busmaster registers */85#define ICH_STARTBM 0x01 /* start busmaster operation */86 87 88/* global block */89#define ICH_REG_GLOB_CNT 0x3c /* dword - global control */90#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */91#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */92#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */93#define ICH_ACLINK 0x00000008 /* AClink shut off */94#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */95#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */96#define ICH_GIE 0x00000001 /* GPI interrupt enable */97#define ICH_REG_GLOB_STA 0x40 /* dword - global status */98#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */99#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */100#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */101#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */102#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */103#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */104#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */105#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */106#define ICH_MD3 0x00020000 /* modem power down semaphore */107#define ICH_AD3 0x00010000 /* audio power down semaphore */108#define ICH_RCS 0x00008000 /* read completion status */109#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */110#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */111#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */112#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */113#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */114#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */115#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */116#define ICH_MCINT 0x00000080 /* MIC capture interrupt */117#define ICH_POINT 0x00000040 /* playback interrupt */118#define ICH_PIINT 0x00000020 /* capture interrupt */119#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */120#define ICH_MOINT 0x00000004 /* modem playback interrupt */121#define ICH_MIINT 0x00000002 /* modem capture interrupt */122#define ICH_GSCI 0x00000001 /* GPI status change interrupt */123#define ICH_REG_ACC_SEMA 0x44 /* byte - codec write semaphore */124#define ICH_CAS 0x01 /* codec access semaphore */125 126#define ICH_MAX_FRAGS 32 /* max hw frags */127 128 129/*130 * 131 */132 133enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT };134enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT };135 136#define get_ichdev(substream) (substream->runtime->private_data)137 138struct ichdev {139 unsigned int ichd; /* ich device number */140 unsigned long reg_offset; /* offset to bmaddr */141 __le32 *bdbar; /* CPU address (32bit) */142 unsigned int bdbar_addr; /* PCI bus address (32bit) */143 struct snd_pcm_substream *substream;144 unsigned int physbuf; /* physical address (32bit) */145 unsigned int size;146 unsigned int fragsize;147 unsigned int fragsize1;148 unsigned int position;149 int frags;150 int lvi;151 int lvi_frag;152 int civ;153 int ack;154 int ack_reload;155 unsigned int ack_bit;156 unsigned int roff_sr;157 unsigned int roff_picb;158 unsigned int int_sta_mask; /* interrupt status mask */159 unsigned int ali_slot; /* ALI DMA slot */160 struct snd_ac97 *ac97;161};162 163struct intel8x0m {164 unsigned int device_type;165 166 int irq;167 168 void __iomem *addr;169 void __iomem *bmaddr;170 171 struct pci_dev *pci;172 struct snd_card *card;173 174 int pcm_devs;175 struct snd_pcm *pcm[2];176 struct ichdev ichd[2];177 178 unsigned int in_ac97_init: 1;179 180 struct snd_ac97_bus *ac97_bus;181 struct snd_ac97 *ac97;182 183 spinlock_t reg_lock;184 185 struct snd_dma_buffer *bdbars;186 u32 bdbars_count;187 u32 int_sta_reg; /* interrupt status register */188 u32 int_sta_mask; /* interrupt status mask */189 unsigned int pcm_pos_shift;190};191 192static const struct pci_device_id snd_intel8x0m_ids[] = {193 { PCI_VDEVICE(INTEL, 0x2416), DEVICE_INTEL }, /* 82801AA */194 { PCI_VDEVICE(INTEL, 0x2426), DEVICE_INTEL }, /* 82901AB */195 { PCI_VDEVICE(INTEL, 0x2446), DEVICE_INTEL }, /* 82801BA */196 { PCI_VDEVICE(INTEL, 0x2486), DEVICE_INTEL }, /* ICH3 */197 { PCI_VDEVICE(INTEL, 0x24c6), DEVICE_INTEL }, /* ICH4 */198 { PCI_VDEVICE(INTEL, 0x24d6), DEVICE_INTEL }, /* ICH5 */199 { PCI_VDEVICE(INTEL, 0x266d), DEVICE_INTEL }, /* ICH6 */200 { PCI_VDEVICE(INTEL, 0x27dd), DEVICE_INTEL }, /* ICH7 */201 { PCI_VDEVICE(INTEL, 0x7196), DEVICE_INTEL }, /* 440MX */202 { PCI_VDEVICE(AMD, 0x7446), DEVICE_INTEL }, /* AMD768 */203 { PCI_VDEVICE(SI, 0x7013), DEVICE_SIS }, /* SI7013 */204 { PCI_VDEVICE(NVIDIA, 0x01c1), DEVICE_NFORCE }, /* NFORCE */205 { PCI_VDEVICE(NVIDIA, 0x0069), DEVICE_NFORCE }, /* NFORCE2 */206 { PCI_VDEVICE(NVIDIA, 0x0089), DEVICE_NFORCE }, /* NFORCE2s */207 { PCI_VDEVICE(NVIDIA, 0x00d9), DEVICE_NFORCE }, /* NFORCE3 */208 { PCI_VDEVICE(AMD, 0x746e), DEVICE_INTEL }, /* AMD8111 */209#if 0210 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */211#endif212 { 0, }213};214 215MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids);216 217/*218 * Lowlevel I/O - busmaster219 */220 221static inline u8 igetbyte(struct intel8x0m *chip, u32 offset)222{223 return ioread8(chip->bmaddr + offset);224}225 226static inline u16 igetword(struct intel8x0m *chip, u32 offset)227{228 return ioread16(chip->bmaddr + offset);229}230 231static inline u32 igetdword(struct intel8x0m *chip, u32 offset)232{233 return ioread32(chip->bmaddr + offset);234}235 236static inline void iputbyte(struct intel8x0m *chip, u32 offset, u8 val)237{238 iowrite8(val, chip->bmaddr + offset);239}240 241static inline void iputword(struct intel8x0m *chip, u32 offset, u16 val)242{243 iowrite16(val, chip->bmaddr + offset);244}245 246static inline void iputdword(struct intel8x0m *chip, u32 offset, u32 val)247{248 iowrite32(val, chip->bmaddr + offset);249}250 251/*252 * Lowlevel I/O - AC'97 registers253 */254 255static inline u16 iagetword(struct intel8x0m *chip, u32 offset)256{257 return ioread16(chip->addr + offset);258}259 260static inline void iaputword(struct intel8x0m *chip, u32 offset, u16 val)261{262 iowrite16(val, chip->addr + offset);263}264 265/*266 * Basic I/O267 */268 269/*270 * access to AC97 codec via normal i/o (for ICH and SIS7013)271 */272 273/* return the GLOB_STA bit for the corresponding codec */274static unsigned int get_ich_codec_bit(struct intel8x0m *chip, unsigned int codec)275{276 static const unsigned int codec_bit[3] = {277 ICH_PCR, ICH_SCR, ICH_TCR278 };279 if (snd_BUG_ON(codec >= 3))280 return ICH_PCR;281 return codec_bit[codec];282}283 284static int snd_intel8x0m_codec_semaphore(struct intel8x0m *chip, unsigned int codec)285{286 int time;287 288 if (codec > 1)289 return -EIO;290 codec = get_ich_codec_bit(chip, codec);291 292 /* codec ready ? */293 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)294 return -EIO;295 296 /* Anyone holding a semaphore for 1 msec should be shot... */297 time = 100;298 do {299 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))300 return 0;301 udelay(10);302 } while (time--);303 304 /* access to some forbidden (non existent) ac97 registers will not305 * reset the semaphore. So even if you don't get the semaphore, still306 * continue the access. We don't need the semaphore anyway. */307 dev_err(chip->card->dev,308 "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",309 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));310 iagetword(chip, 0); /* clear semaphore flag */311 /* I don't care about the semaphore */312 return -EBUSY;313}314 315static void snd_intel8x0m_codec_write(struct snd_ac97 *ac97,316 unsigned short reg,317 unsigned short val)318{319 struct intel8x0m *chip = ac97->private_data;320 321 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {322 if (! chip->in_ac97_init)323 dev_err(chip->card->dev,324 "codec_write %d: semaphore is not ready for register 0x%x\n",325 ac97->num, reg);326 }327 iaputword(chip, reg + ac97->num * 0x80, val);328}329 330static unsigned short snd_intel8x0m_codec_read(struct snd_ac97 *ac97,331 unsigned short reg)332{333 struct intel8x0m *chip = ac97->private_data;334 unsigned short res;335 unsigned int tmp;336 337 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {338 if (! chip->in_ac97_init)339 dev_err(chip->card->dev,340 "codec_read %d: semaphore is not ready for register 0x%x\n",341 ac97->num, reg);342 res = 0xffff;343 } else {344 res = iagetword(chip, reg + ac97->num * 0x80);345 tmp = igetdword(chip, ICHREG(GLOB_STA));346 if (tmp & ICH_RCS) {347 /* reset RCS and preserve other R/WC bits */348 iputdword(chip, ICHREG(GLOB_STA),349 tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));350 if (! chip->in_ac97_init)351 dev_err(chip->card->dev,352 "codec_read %d: read timeout for register 0x%x\n",353 ac97->num, reg);354 res = 0xffff;355 }356 }357 if (reg == AC97_GPIO_STATUS)358 iagetword(chip, 0); /* clear semaphore */359 return res;360}361 362 363/*364 * DMA I/O365 */366static void snd_intel8x0m_setup_periods(struct intel8x0m *chip, struct ichdev *ichdev)367{368 int idx;369 __le32 *bdbar = ichdev->bdbar;370 unsigned long port = ichdev->reg_offset;371 372 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);373 if (ichdev->size == ichdev->fragsize) {374 ichdev->ack_reload = ichdev->ack = 2;375 ichdev->fragsize1 = ichdev->fragsize >> 1;376 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {377 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);378 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */379 ichdev->fragsize1 >> chip->pcm_pos_shift);380 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));381 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */382 ichdev->fragsize1 >> chip->pcm_pos_shift);383 }384 ichdev->frags = 2;385 } else {386 ichdev->ack_reload = ichdev->ack = 1;387 ichdev->fragsize1 = ichdev->fragsize;388 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {389 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));390 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */391 ichdev->fragsize >> chip->pcm_pos_shift);392 /*393 dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n",394 idx + 0, bdbar[idx + 0], bdbar[idx + 1]);395 */396 }397 ichdev->frags = ichdev->size / ichdev->fragsize;398 }399 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);400 ichdev->civ = 0;401 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);402 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;403 ichdev->position = 0;404#if 0405 dev_dbg(chip->card->dev,406 "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",407 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,408 ichdev->fragsize1);409#endif410 /* clear interrupts */411 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);412}413 414/*415 * Interrupt handler416 */417 418static inline void snd_intel8x0m_update(struct intel8x0m *chip, struct ichdev *ichdev)419{420 unsigned long port = ichdev->reg_offset;421 int civ, i, step;422 int ack = 0;423 424 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);425 if (civ == ichdev->civ) {426 step = 1;427 ichdev->civ++;428 ichdev->civ &= ICH_REG_LVI_MASK;429 } else {430 step = civ - ichdev->civ;431 if (step < 0)432 step += ICH_REG_LVI_MASK + 1;433 ichdev->civ = civ;434 }435 436 ichdev->position += step * ichdev->fragsize1;437 ichdev->position %= ichdev->size;438 ichdev->lvi += step;439 ichdev->lvi &= ICH_REG_LVI_MASK;440 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);441 for (i = 0; i < step; i++) {442 ichdev->lvi_frag++;443 ichdev->lvi_frag %= ichdev->frags;444 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf +445 ichdev->lvi_frag *446 ichdev->fragsize1);447#if 0448 dev_dbg(chip->card->dev,449 "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",450 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],451 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),452 inl(port + 4), inb(port + ICH_REG_OFF_CR));453#endif454 if (--ichdev->ack == 0) {455 ichdev->ack = ichdev->ack_reload;456 ack = 1;457 }458 }459 if (ack && ichdev->substream) {460 spin_unlock(&chip->reg_lock);461 snd_pcm_period_elapsed(ichdev->substream);462 spin_lock(&chip->reg_lock);463 }464 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);465}466 467static irqreturn_t snd_intel8x0m_interrupt(int irq, void *dev_id)468{469 struct intel8x0m *chip = dev_id;470 struct ichdev *ichdev;471 unsigned int status;472 unsigned int i;473 474 spin_lock(&chip->reg_lock);475 status = igetdword(chip, chip->int_sta_reg);476 if (status == 0xffffffff) { /* we are not yet resumed */477 spin_unlock(&chip->reg_lock);478 return IRQ_NONE;479 }480 if ((status & chip->int_sta_mask) == 0) {481 if (status)482 iputdword(chip, chip->int_sta_reg, status);483 spin_unlock(&chip->reg_lock);484 return IRQ_NONE;485 }486 487 for (i = 0; i < chip->bdbars_count; i++) {488 ichdev = &chip->ichd[i];489 if (status & ichdev->int_sta_mask)490 snd_intel8x0m_update(chip, ichdev);491 }492 493 /* ack them */494 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);495 spin_unlock(&chip->reg_lock);496 497 return IRQ_HANDLED;498}499 500/*501 * PCM part502 */503 504static int snd_intel8x0m_pcm_trigger(struct snd_pcm_substream *substream, int cmd)505{506 struct intel8x0m *chip = snd_pcm_substream_chip(substream);507 struct ichdev *ichdev = get_ichdev(substream);508 unsigned char val = 0;509 unsigned long port = ichdev->reg_offset;510 511 switch (cmd) {512 case SNDRV_PCM_TRIGGER_START:513 case SNDRV_PCM_TRIGGER_RESUME:514 val = ICH_IOCE | ICH_STARTBM;515 break;516 case SNDRV_PCM_TRIGGER_STOP:517 case SNDRV_PCM_TRIGGER_SUSPEND:518 val = 0;519 break;520 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:521 val = ICH_IOCE;522 break;523 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:524 val = ICH_IOCE | ICH_STARTBM;525 break;526 default:527 return -EINVAL;528 }529 iputbyte(chip, port + ICH_REG_OFF_CR, val);530 if (cmd == SNDRV_PCM_TRIGGER_STOP) {531 /* wait until DMA stopped */532 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;533 /* reset whole DMA things */534 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);535 }536 return 0;537}538 539static snd_pcm_uframes_t snd_intel8x0m_pcm_pointer(struct snd_pcm_substream *substream)540{541 struct intel8x0m *chip = snd_pcm_substream_chip(substream);542 struct ichdev *ichdev = get_ichdev(substream);543 size_t ptr1, ptr;544 545 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;546 if (ptr1 != 0)547 ptr = ichdev->fragsize1 - ptr1;548 else549 ptr = 0;550 ptr += ichdev->position;551 if (ptr >= ichdev->size)552 return 0;553 return bytes_to_frames(substream->runtime, ptr);554}555 556static int snd_intel8x0m_pcm_prepare(struct snd_pcm_substream *substream)557{558 struct intel8x0m *chip = snd_pcm_substream_chip(substream);559 struct snd_pcm_runtime *runtime = substream->runtime;560 struct ichdev *ichdev = get_ichdev(substream);561 562 ichdev->physbuf = runtime->dma_addr;563 ichdev->size = snd_pcm_lib_buffer_bytes(substream);564 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);565 snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate);566 snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0);567 snd_intel8x0m_setup_periods(chip, ichdev);568 return 0;569}570 571static const struct snd_pcm_hardware snd_intel8x0m_stream =572{573 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |574 SNDRV_PCM_INFO_BLOCK_TRANSFER |575 SNDRV_PCM_INFO_MMAP_VALID |576 SNDRV_PCM_INFO_PAUSE |577 SNDRV_PCM_INFO_RESUME),578 .formats = SNDRV_PCM_FMTBIT_S16_LE,579 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT,580 .rate_min = 8000,581 .rate_max = 16000,582 .channels_min = 1,583 .channels_max = 1,584 .buffer_bytes_max = 64 * 1024,585 .period_bytes_min = 32,586 .period_bytes_max = 64 * 1024,587 .periods_min = 1,588 .periods_max = 1024,589 .fifo_size = 0,590};591 592 593static int snd_intel8x0m_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)594{595 static const unsigned int rates[] = { 8000, 9600, 12000, 16000 };596 static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {597 .count = ARRAY_SIZE(rates),598 .list = rates,599 .mask = 0,600 };601 struct snd_pcm_runtime *runtime = substream->runtime;602 int err;603 604 ichdev->substream = substream;605 runtime->hw = snd_intel8x0m_stream;606 err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,607 &hw_constraints_rates);608 if ( err < 0 )609 return err;610 runtime->private_data = ichdev;611 return 0;612}613 614static int snd_intel8x0m_playback_open(struct snd_pcm_substream *substream)615{616 struct intel8x0m *chip = snd_pcm_substream_chip(substream);617 618 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]);619}620 621static int snd_intel8x0m_playback_close(struct snd_pcm_substream *substream)622{623 struct intel8x0m *chip = snd_pcm_substream_chip(substream);624 625 chip->ichd[ICHD_MDMOUT].substream = NULL;626 return 0;627}628 629static int snd_intel8x0m_capture_open(struct snd_pcm_substream *substream)630{631 struct intel8x0m *chip = snd_pcm_substream_chip(substream);632 633 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]);634}635 636static int snd_intel8x0m_capture_close(struct snd_pcm_substream *substream)637{638 struct intel8x0m *chip = snd_pcm_substream_chip(substream);639 640 chip->ichd[ICHD_MDMIN].substream = NULL;641 return 0;642}643 644 645static const struct snd_pcm_ops snd_intel8x0m_playback_ops = {646 .open = snd_intel8x0m_playback_open,647 .close = snd_intel8x0m_playback_close,648 .prepare = snd_intel8x0m_pcm_prepare,649 .trigger = snd_intel8x0m_pcm_trigger,650 .pointer = snd_intel8x0m_pcm_pointer,651};652 653static const struct snd_pcm_ops snd_intel8x0m_capture_ops = {654 .open = snd_intel8x0m_capture_open,655 .close = snd_intel8x0m_capture_close,656 .prepare = snd_intel8x0m_pcm_prepare,657 .trigger = snd_intel8x0m_pcm_trigger,658 .pointer = snd_intel8x0m_pcm_pointer,659};660 661 662struct ich_pcm_table {663 char *suffix;664 const struct snd_pcm_ops *playback_ops;665 const struct snd_pcm_ops *capture_ops;666 size_t prealloc_size;667 size_t prealloc_max_size;668 int ac97_idx;669};670 671static int snd_intel8x0m_pcm1(struct intel8x0m *chip, int device,672 const struct ich_pcm_table *rec)673{674 struct snd_pcm *pcm;675 int err;676 char name[32];677 678 if (rec->suffix)679 sprintf(name, "Intel ICH - %s", rec->suffix);680 else681 strcpy(name, "Intel ICH");682 err = snd_pcm_new(chip->card, name, device,683 rec->playback_ops ? 1 : 0,684 rec->capture_ops ? 1 : 0, &pcm);685 if (err < 0)686 return err;687 688 if (rec->playback_ops)689 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);690 if (rec->capture_ops)691 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);692 693 pcm->private_data = chip;694 pcm->info_flags = 0;695 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;696 if (rec->suffix)697 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);698 else699 strcpy(pcm->name, chip->card->shortname);700 chip->pcm[device] = pcm;701 702 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,703 &chip->pci->dev,704 rec->prealloc_size,705 rec->prealloc_max_size);706 707 return 0;708}709 710static const struct ich_pcm_table intel_pcms[] = {711 {712 .suffix = "Modem",713 .playback_ops = &snd_intel8x0m_playback_ops,714 .capture_ops = &snd_intel8x0m_capture_ops,715 .prealloc_size = 32 * 1024,716 .prealloc_max_size = 64 * 1024,717 },718};719 720static int snd_intel8x0m_pcm(struct intel8x0m *chip)721{722 int i, tblsize, device, err;723 const struct ich_pcm_table *tbl, *rec;724 725#if 1726 tbl = intel_pcms;727 tblsize = 1;728#else729 switch (chip->device_type) {730 case DEVICE_NFORCE:731 tbl = nforce_pcms;732 tblsize = ARRAY_SIZE(nforce_pcms);733 break;734 case DEVICE_ALI:735 tbl = ali_pcms;736 tblsize = ARRAY_SIZE(ali_pcms);737 break;738 default:739 tbl = intel_pcms;740 tblsize = 2;741 break;742 }743#endif744 device = 0;745 for (i = 0; i < tblsize; i++) {746 rec = tbl + i;747 if (i > 0 && rec->ac97_idx) {748 /* activate PCM only when associated AC'97 codec */749 if (! chip->ichd[rec->ac97_idx].ac97)750 continue;751 }752 err = snd_intel8x0m_pcm1(chip, device, rec);753 if (err < 0)754 return err;755 device++;756 }757 758 chip->pcm_devs = device;759 return 0;760}761 762 763/*764 * Mixer part765 */766 767static void snd_intel8x0m_mixer_free_ac97_bus(struct snd_ac97_bus *bus)768{769 struct intel8x0m *chip = bus->private_data;770 chip->ac97_bus = NULL;771}772 773static void snd_intel8x0m_mixer_free_ac97(struct snd_ac97 *ac97)774{775 struct intel8x0m *chip = ac97->private_data;776 chip->ac97 = NULL;777}778 779 780static int snd_intel8x0m_mixer(struct intel8x0m *chip, int ac97_clock)781{782 struct snd_ac97_bus *pbus;783 struct snd_ac97_template ac97;784 struct snd_ac97 *x97;785 int err;786 unsigned int glob_sta = 0;787 static const struct snd_ac97_bus_ops ops = {788 .write = snd_intel8x0m_codec_write,789 .read = snd_intel8x0m_codec_read,790 };791 792 chip->in_ac97_init = 1;793 794 memset(&ac97, 0, sizeof(ac97));795 ac97.private_data = chip;796 ac97.private_free = snd_intel8x0m_mixer_free_ac97;797 ac97.scaps = AC97_SCAP_SKIP_AUDIO | AC97_SCAP_POWER_SAVE;798 799 glob_sta = igetdword(chip, ICHREG(GLOB_STA));800 801 err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus);802 if (err < 0)803 goto __err;804 pbus->private_free = snd_intel8x0m_mixer_free_ac97_bus;805 if (ac97_clock >= 8000 && ac97_clock <= 48000)806 pbus->clock = ac97_clock;807 chip->ac97_bus = pbus;808 809 ac97.pci = chip->pci;810 ac97.num = glob_sta & ICH_SCR ? 1 : 0;811 err = snd_ac97_mixer(pbus, &ac97, &x97);812 if (err < 0) {813 dev_err(chip->card->dev,814 "Unable to initialize codec #%d\n", ac97.num);815 if (ac97.num == 0)816 goto __err;817 return err;818 }819 chip->ac97 = x97;820 if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97) {821 chip->ichd[ICHD_MDMIN].ac97 = x97;822 chip->ichd[ICHD_MDMOUT].ac97 = x97;823 }824 825 chip->in_ac97_init = 0;826 return 0;827 828 __err:829 /* clear the cold-reset bit for the next chance */830 if (chip->device_type != DEVICE_ALI)831 iputdword(chip, ICHREG(GLOB_CNT),832 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);833 return err;834}835 836 837/*838 *839 */840 841static int snd_intel8x0m_ich_chip_init(struct intel8x0m *chip, int probing)842{843 unsigned long end_time;844 unsigned int cnt, status, nstatus;845 846 /* put logic to right state */847 /* first clear status bits */848 status = ICH_RCS | ICH_MIINT | ICH_MOINT;849 cnt = igetdword(chip, ICHREG(GLOB_STA));850 iputdword(chip, ICHREG(GLOB_STA), cnt & status);851 852 /* ACLink on, 2 channels */853 cnt = igetdword(chip, ICHREG(GLOB_CNT));854 cnt &= ~(ICH_ACLINK);855 /* finish cold or do warm reset */856 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;857 iputdword(chip, ICHREG(GLOB_CNT), cnt);858 usleep_range(500, 1000); /* give warm reset some time */859 end_time = jiffies + HZ / 4;860 do {861 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)862 goto __ok;863 schedule_timeout_uninterruptible(1);864 } while (time_after_eq(end_time, jiffies));865 dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",866 igetdword(chip, ICHREG(GLOB_CNT)));867 return -EIO;868 869 __ok:870 if (probing) {871 /* wait for any codec ready status.872 * Once it becomes ready it should remain ready873 * as long as we do not disable the ac97 link.874 */875 end_time = jiffies + HZ;876 do {877 status = igetdword(chip, ICHREG(GLOB_STA)) &878 (ICH_PCR | ICH_SCR | ICH_TCR);879 if (status)880 break;881 schedule_timeout_uninterruptible(1);882 } while (time_after_eq(end_time, jiffies));883 if (! status) {884 /* no codec is found */885 dev_err(chip->card->dev,886 "codec_ready: codec is not ready [0x%x]\n",887 igetdword(chip, ICHREG(GLOB_STA)));888 return -EIO;889 }890 891 /* up to two codecs (modem cannot be tertiary with ICH4) */892 nstatus = ICH_PCR | ICH_SCR;893 894 /* wait for other codecs ready status. */895 end_time = jiffies + HZ / 4;896 while (status != nstatus && time_after_eq(end_time, jiffies)) {897 schedule_timeout_uninterruptible(1);898 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;899 }900 901 } else {902 /* resume phase */903 status = 0;904 if (chip->ac97)905 status |= get_ich_codec_bit(chip, chip->ac97->num);906 /* wait until all the probed codecs are ready */907 end_time = jiffies + HZ;908 do {909 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &910 (ICH_PCR | ICH_SCR | ICH_TCR);911 if (status == nstatus)912 break;913 schedule_timeout_uninterruptible(1);914 } while (time_after_eq(end_time, jiffies));915 }916 917 if (chip->device_type == DEVICE_SIS) {918 /* unmute the output on SIS7013 */919 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);920 }921 922 return 0;923}924 925static int snd_intel8x0m_chip_init(struct intel8x0m *chip, int probing)926{927 unsigned int i;928 int err;929 930 err = snd_intel8x0m_ich_chip_init(chip, probing);931 if (err < 0)932 return err;933 iagetword(chip, 0); /* clear semaphore flag */934 935 /* disable interrupts */936 for (i = 0; i < chip->bdbars_count; i++)937 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);938 /* reset channels */939 for (i = 0; i < chip->bdbars_count; i++)940 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);941 /* initialize Buffer Descriptor Lists */942 for (i = 0; i < chip->bdbars_count; i++)943 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);944 return 0;945}946 947static void snd_intel8x0m_free(struct snd_card *card)948{949 struct intel8x0m *chip = card->private_data;950 unsigned int i;951 952 if (chip->irq < 0)953 goto __hw_end;954 /* disable interrupts */955 for (i = 0; i < chip->bdbars_count; i++)956 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);957 /* reset channels */958 for (i = 0; i < chip->bdbars_count; i++)959 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);960 __hw_end:961 if (chip->irq >= 0)962 free_irq(chip->irq, chip);963}964 965/*966 * power management967 */968static int intel8x0m_suspend(struct device *dev)969{970 struct snd_card *card = dev_get_drvdata(dev);971 struct intel8x0m *chip = card->private_data;972 973 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);974 snd_ac97_suspend(chip->ac97);975 if (chip->irq >= 0) {976 free_irq(chip->irq, chip);977 chip->irq = -1;978 card->sync_irq = -1;979 }980 return 0;981}982 983static int intel8x0m_resume(struct device *dev)984{985 struct pci_dev *pci = to_pci_dev(dev);986 struct snd_card *card = dev_get_drvdata(dev);987 struct intel8x0m *chip = card->private_data;988 989 if (request_irq(pci->irq, snd_intel8x0m_interrupt,990 IRQF_SHARED, KBUILD_MODNAME, chip)) {991 dev_err(dev, "unable to grab IRQ %d, disabling device\n",992 pci->irq);993 snd_card_disconnect(card);994 return -EIO;995 }996 chip->irq = pci->irq;997 card->sync_irq = chip->irq;998 snd_intel8x0m_chip_init(chip, 0);999 snd_ac97_resume(chip->ac97);1000 1001 snd_power_change_state(card, SNDRV_CTL_POWER_D0);1002 return 0;1003}1004 1005static DEFINE_SIMPLE_DEV_PM_OPS(intel8x0m_pm, intel8x0m_suspend, intel8x0m_resume);1006 1007static void snd_intel8x0m_proc_read(struct snd_info_entry * entry,1008 struct snd_info_buffer *buffer)1009{1010 struct intel8x0m *chip = entry->private_data;1011 unsigned int tmp;1012 1013 snd_iprintf(buffer, "Intel8x0m\n\n");1014 if (chip->device_type == DEVICE_ALI)1015 return;1016 tmp = igetdword(chip, ICHREG(GLOB_STA));1017 snd_iprintf(buffer, "Global control : 0x%08x\n",1018 igetdword(chip, ICHREG(GLOB_CNT)));1019 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);1020 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",1021 tmp & ICH_PCR ? " primary" : "",1022 tmp & ICH_SCR ? " secondary" : "",1023 tmp & ICH_TCR ? " tertiary" : "",1024 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");1025}1026 1027static void snd_intel8x0m_proc_init(struct intel8x0m *chip)1028{1029 snd_card_ro_proc_new(chip->card, "intel8x0m", chip,1030 snd_intel8x0m_proc_read);1031}1032 1033struct ich_reg_info {1034 unsigned int int_sta_mask;1035 unsigned int offset;1036};1037 1038static int snd_intel8x0m_init(struct snd_card *card,1039 struct pci_dev *pci,1040 unsigned long device_type)1041{1042 struct intel8x0m *chip = card->private_data;1043 int err;1044 unsigned int i;1045 unsigned int int_sta_masks;1046 struct ichdev *ichdev;1047 static const struct ich_reg_info intel_regs[2] = {1048 { ICH_MIINT, 0 },1049 { ICH_MOINT, 0x10 },1050 };1051 const struct ich_reg_info *tbl;1052 1053 err = pcim_enable_device(pci);1054 if (err < 0)1055 return err;1056 1057 spin_lock_init(&chip->reg_lock);1058 chip->device_type = device_type;1059 chip->card = card;1060 chip->pci = pci;1061 chip->irq = -1;1062 1063 err = pci_request_regions(pci, card->shortname);1064 if (err < 0)1065 return err;1066 1067 if (device_type == DEVICE_ALI) {1068 /* ALI5455 has no ac97 region */1069 chip->bmaddr = pcim_iomap(pci, 0, 0);1070 } else {1071 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */1072 chip->addr = pcim_iomap(pci, 2, 0);1073 else1074 chip->addr = pcim_iomap(pci, 0, 0);1075 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */1076 chip->bmaddr = pcim_iomap(pci, 3, 0);1077 else1078 chip->bmaddr = pcim_iomap(pci, 1, 0);1079 }1080 1081 /* initialize offsets */1082 chip->bdbars_count = 2;1083 tbl = intel_regs;1084 1085 for (i = 0; i < chip->bdbars_count; i++) {1086 ichdev = &chip->ichd[i];1087 ichdev->ichd = i;1088 ichdev->reg_offset = tbl[i].offset;1089 ichdev->int_sta_mask = tbl[i].int_sta_mask;1090 if (device_type == DEVICE_SIS) {1091 /* SiS 7013 swaps the registers */1092 ichdev->roff_sr = ICH_REG_OFF_PICB;1093 ichdev->roff_picb = ICH_REG_OFF_SR;1094 } else {1095 ichdev->roff_sr = ICH_REG_OFF_SR;1096 ichdev->roff_picb = ICH_REG_OFF_PICB;1097 }1098 if (device_type == DEVICE_ALI)1099 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;1100 }1101 /* SIS7013 handles the pcm data in bytes, others are in words */1102 chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;1103 1104 /* allocate buffer descriptor lists */1105 /* the start of each lists must be aligned to 8 bytes */1106 chip->bdbars = snd_devm_alloc_pages(&pci->dev, SNDRV_DMA_TYPE_DEV,1107 chip->bdbars_count * sizeof(u32) *1108 ICH_MAX_FRAGS * 2);1109 if (!chip->bdbars)1110 return -ENOMEM;1111 1112 /* tables must be aligned to 8 bytes here, but the kernel pages1113 are much bigger, so we don't care (on i386) */1114 int_sta_masks = 0;1115 for (i = 0; i < chip->bdbars_count; i++) {1116 ichdev = &chip->ichd[i];1117 ichdev->bdbar = ((__le32 *)chip->bdbars->area) + (i * ICH_MAX_FRAGS * 2);1118 ichdev->bdbar_addr = chip->bdbars->addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);1119 int_sta_masks |= ichdev->int_sta_mask;1120 }1121 chip->int_sta_reg = ICH_REG_GLOB_STA;1122 chip->int_sta_mask = int_sta_masks;1123 1124 pci_set_master(pci);1125 1126 err = snd_intel8x0m_chip_init(chip, 1);1127 if (err < 0)1128 return err;1129 1130 /* NOTE: we don't use devm version here since it's released /1131 * re-acquired in PM callbacks.1132 * It's released explicitly in snd_intel8x0m_free(), too.1133 */1134 if (request_irq(pci->irq, snd_intel8x0m_interrupt, IRQF_SHARED,1135 KBUILD_MODNAME, chip)) {1136 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);1137 return -EBUSY;1138 }1139 chip->irq = pci->irq;1140 card->sync_irq = chip->irq;1141 1142 card->private_free = snd_intel8x0m_free;1143 1144 return 0;1145}1146 1147static struct shortname_table {1148 unsigned int id;1149 const char *s;1150} shortnames[] = {1151 { PCI_DEVICE_ID_INTEL_82801AA_6, "Intel 82801AA-ICH" },1152 { PCI_DEVICE_ID_INTEL_82801AB_6, "Intel 82901AB-ICH0" },1153 { PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" },1154 { PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" },1155 { PCI_DEVICE_ID_INTEL_82801CA_6, "Intel 82801CA-ICH3" },1156 { PCI_DEVICE_ID_INTEL_82801DB_6, "Intel 82801DB-ICH4" },1157 { PCI_DEVICE_ID_INTEL_82801EB_6, "Intel ICH5" },1158 { PCI_DEVICE_ID_INTEL_ICH6_17, "Intel ICH6" },1159 { PCI_DEVICE_ID_INTEL_ICH7_19, "Intel ICH7" },1160 { 0x7446, "AMD AMD768" },1161 { PCI_DEVICE_ID_SI_7013, "SiS SI7013" },1162 { PCI_DEVICE_ID_NVIDIA_MCP1_MODEM, "NVidia nForce" },1163 { PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" },1164 { PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" },1165 { PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" },1166 { 0x746e, "AMD AMD8111" },1167#if 01168 { 0x5455, "ALi M5455" },1169#endif1170 { 0 },1171};1172 1173static int __snd_intel8x0m_probe(struct pci_dev *pci,1174 const struct pci_device_id *pci_id)1175{1176 struct snd_card *card;1177 struct intel8x0m *chip;1178 int err;1179 struct shortname_table *name;1180 1181 err = snd_devm_card_new(&pci->dev, index, id, THIS_MODULE,1182 sizeof(*chip), &card);1183 if (err < 0)1184 return err;1185 chip = card->private_data;1186 1187 strcpy(card->driver, "ICH-MODEM");1188 strcpy(card->shortname, "Intel ICH");1189 for (name = shortnames; name->id; name++) {1190 if (pci->device == name->id) {1191 strcpy(card->shortname, name->s);1192 break;1193 }1194 }1195 strcat(card->shortname," Modem");1196 1197 err = snd_intel8x0m_init(card, pci, pci_id->driver_data);1198 if (err < 0)1199 return err;1200 1201 err = snd_intel8x0m_mixer(chip, ac97_clock);1202 if (err < 0)1203 return err;1204 err = snd_intel8x0m_pcm(chip);1205 if (err < 0)1206 return err;1207 1208 snd_intel8x0m_proc_init(chip);1209 1210 sprintf(card->longname, "%s at irq %i",1211 card->shortname, chip->irq);1212 1213 err = snd_card_register(card);1214 if (err < 0)1215 return err;1216 pci_set_drvdata(pci, card);1217 return 0;1218}1219 1220static int snd_intel8x0m_probe(struct pci_dev *pci,1221 const struct pci_device_id *pci_id)1222{1223 return snd_card_free_on_error(&pci->dev, __snd_intel8x0m_probe(pci, pci_id));1224}1225 1226static struct pci_driver intel8x0m_driver = {1227 .name = KBUILD_MODNAME,1228 .id_table = snd_intel8x0m_ids,1229 .probe = snd_intel8x0m_probe,1230 .driver = {1231 .pm = &intel8x0m_pm,1232 },1233};1234 1235module_pci_driver(intel8x0m_driver);1236