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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/* -*- linux-c -*- *3 *4 * ALSA driver for the digigram lx6464es interface5 * adapted upstream headers6 *7 * Copyright (c) 2009 Tim Blechmann <tim@klingt.org>8 */9 10#ifndef LX_DEFS_H11#define LX_DEFS_H12 13/* code adapted from ethersound.h */14#define XES_FREQ_COUNT8_MASK 0x00001FFF /* compteur 25MHz entre 8 ech. */15#define XES_FREQ_COUNT8_44_MIN 0x00001288 /* 25M /16 * [ 44k - ( 44.1k + 48k ) / 2 ]17 * * 8 */18#define XES_FREQ_COUNT8_44_MAX 0x000010F0 /* 25M / [ ( 44.1k + 48k ) / 2 ]19 * * 8 */20#define XES_FREQ_COUNT8_48_MAX 0x00000F08 /* 25M /21 * [ 48k + ( 44.1k + 48k ) / 2 ]22 * * 8 */23 24/* code adapted from LXES_registers.h */25 26#define IOCR_OUTPUTS_OFFSET 0 /* (rw) offset for the number of OUTs in the27 * ConfES register. */28#define IOCR_INPUTS_OFFSET 8 /* (rw) offset for the number of INs in the29 * ConfES register. */30#define FREQ_RATIO_OFFSET 19 /* (rw) offset for frequency ratio in the31 * ConfES register. */32#define FREQ_RATIO_SINGLE_MODE 0x01 /* value for single mode frequency ratio:33 * sample rate = frequency rate. */34 35#define CONFES_READ_PART_MASK 0x0007000036#define CONFES_WRITE_PART_MASK 0x00F8000037 38/* code adapted from if_drv_mb.h */39 40#define MASK_SYS_STATUS_ERROR (1L << 31) /* events that lead to a PCI irq if41 * not yet pending */42#define MASK_SYS_STATUS_URUN (1L << 30)43#define MASK_SYS_STATUS_ORUN (1L << 29)44#define MASK_SYS_STATUS_EOBO (1L << 28)45#define MASK_SYS_STATUS_EOBI (1L << 27)46#define MASK_SYS_STATUS_FREQ (1L << 26)47#define MASK_SYS_STATUS_ESA (1L << 25) /* reserved, this is set by the48 * XES */49#define MASK_SYS_STATUS_TIMER (1L << 24)50 51#define MASK_SYS_ASYNC_EVENTS (MASK_SYS_STATUS_ERROR | \52 MASK_SYS_STATUS_URUN | \53 MASK_SYS_STATUS_ORUN | \54 MASK_SYS_STATUS_EOBO | \55 MASK_SYS_STATUS_EOBI | \56 MASK_SYS_STATUS_FREQ | \57 MASK_SYS_STATUS_ESA)58 59#define MASK_SYS_PCI_EVENTS (MASK_SYS_ASYNC_EVENTS | \60 MASK_SYS_STATUS_TIMER)61 62#define MASK_SYS_TIMER_COUNT 0x0000FFFF63 64#define MASK_SYS_STATUS_EOT_PLX (1L << 22) /* event that remains65 * internal: reserved fo end66 * of plx dma */67#define MASK_SYS_STATUS_XES (1L << 21) /* event that remains68 * internal: pending XES69 * IRQ */70#define MASK_SYS_STATUS_CMD_DONE (1L << 20) /* alternate command71 * management: notify driver72 * instead of polling */73 74 75#define MAX_STREAM_BUFFER 5 /* max amount of stream buffers. */76 77#define MICROBLAZE_IBL_MIN 3278#define MICROBLAZE_IBL_DEFAULT 12879#define MICROBLAZE_IBL_MAX 51280/* #define MASK_GRANULARITY (2*MICROBLAZE_IBL_MAX-1) */81 82 83 84/* command opcodes, see reference for details */85 86/*87 the capture bit position in the object_id field in driver commands88 depends upon the number of managed channels. For now, 64 IN + 64 OUT are89 supported. HOwever, the communication protocol forsees 1024 channels, hence90 bit 10 indicates a capture (input) object).91*/92#define ID_IS_CAPTURE (1L << 10)93#define ID_OFFSET 13 /* object ID is at the 13th bit in the94 * 1st command word.*/95#define ID_CH_MASK 0x3F96#define OPCODE_OFFSET 24 /* offset of the command opcode in the first97 * command word.*/98 99enum cmd_mb_opcodes {100 CMD_00_INFO_DEBUG = 0x00,101 CMD_01_GET_SYS_CFG = 0x01,102 CMD_02_SET_GRANULARITY = 0x02,103 CMD_03_SET_TIMER_IRQ = 0x03,104 CMD_04_GET_EVENT = 0x04,105 CMD_05_GET_PIPES = 0x05,106 107 CMD_06_ALLOCATE_PIPE = 0x06,108 CMD_07_RELEASE_PIPE = 0x07,109 CMD_08_ASK_BUFFERS = 0x08,110 CMD_09_STOP_PIPE = 0x09,111 CMD_0A_GET_PIPE_SPL_COUNT = 0x0a,112 CMD_0B_TOGGLE_PIPE_STATE = 0x0b,113 114 CMD_0C_DEF_STREAM = 0x0c,115 CMD_0D_SET_MUTE = 0x0d,116 CMD_0E_GET_STREAM_SPL_COUNT = 0x0e,117 CMD_0F_UPDATE_BUFFER = 0x0f,118 CMD_10_GET_BUFFER = 0x10,119 CMD_11_CANCEL_BUFFER = 0x11,120 CMD_12_GET_PEAK = 0x12,121 CMD_13_SET_STREAM_STATE = 0x13,122 CMD_14_INVALID = 0x14,123};124 125/* pipe states */126enum pipe_state_t {127 PSTATE_IDLE = 0, /* the pipe is not processed in the XES_IRQ128 * (free or stopped, or paused). */129 PSTATE_RUN = 1, /* sustained play/record state. */130 PSTATE_PURGE = 2, /* the ES channels are now off, render pipes do131 * not DMA, record pipe do a last DMA. */132 PSTATE_ACQUIRE = 3, /* the ES channels are now on, render pipes do133 * not yet increase their sample count, record134 * pipes do not DMA. */135 PSTATE_CLOSING = 4, /* the pipe is releasing, and may not yet136 * receive an "alloc" command. */137};138 139/* stream states */140enum stream_state_t {141 SSTATE_STOP = 0x00, /* setting to stop resets the stream spl142 * count.*/143 SSTATE_RUN = (0x01 << 0), /* start DMA and spl count handling. */144 SSTATE_PAUSE = (0x01 << 1), /* pause DMA and spl count handling. */145};146 147/* buffer flags */148enum buffer_flags {149 BF_VALID = 0x80, /* set if the buffer is valid, clear if free.*/150 BF_CURRENT = 0x40, /* set if this is the current buffer (there is151 * always a current buffer).*/152 BF_NOTIFY_EOB = 0x20, /* set if this buffer must cause a PCI event153 * when finished.*/154 BF_CIRCULAR = 0x10, /* set if buffer[1] must be copied to buffer[0]155 * by the end of this buffer.*/156 BF_64BITS_ADR = 0x08, /* set if the hi part of the address is valid.*/157 BF_xx = 0x04, /* future extension.*/158 BF_EOB = 0x02, /* set if finished, but not yet free.*/159 BF_PAUSE = 0x01, /* pause stream at buffer end.*/160 BF_ZERO = 0x00, /* no flags (init).*/161};162 163/*164* Stream Flags definitions165*/166enum stream_flags {167 SF_ZERO = 0x00000000, /* no flags (stream invalid). */168 SF_VALID = 0x10000000, /* the stream has a valid DMA_conf169 * info (setstreamformat). */170 SF_XRUN = 0x20000000, /* the stream is un x-run state. */171 SF_START = 0x40000000, /* the DMA is running.*/172 SF_ASIO = 0x80000000, /* ASIO.*/173};174 175 176#define MASK_SPL_COUNT_HI 0x00FFFFFF /* 4 MSBits are status bits */177#define PSTATE_OFFSET 28 /* 4 MSBits are status bits */178 179 180#define MASK_STREAM_HAS_MAPPING (1L << 12)181#define MASK_STREAM_IS_ASIO (1L << 9)182#define STREAM_FMT_OFFSET 10 /* the stream fmt bits start at the 10th183 * bit in the command word. */184 185#define STREAM_FMT_16b 0x02186#define STREAM_FMT_intel 0x01187 188#define FREQ_FIELD_OFFSET 15 /* offset of the freq field in the response189 * word */190 191#define BUFF_FLAGS_OFFSET 24 /* offset of the buffer flags in the192 * response word. */193#define MASK_DATA_SIZE 0x00FFFFFF /* this must match the field size of194 * datasize in the buffer_t structure. */195 196#define MASK_BUFFER_ID 0xFF /* the cancel command awaits a buffer ID,197 * may be 0xFF for "current". */198 199 200/* code adapted from PcxErr_e.h */201 202/* Bits masks */203 204#define ERROR_MASK 0x8000205 206#define SOURCE_MASK 0x7800207 208#define E_SOURCE_BOARD 0x4000 /* 8 >> 1 */209#define E_SOURCE_DRV 0x2000 /* 4 >> 1 */210#define E_SOURCE_API 0x1000 /* 2 >> 1 */211/* Error tools */212#define E_SOURCE_TOOLS 0x0800 /* 1 >> 1 */213/* Error pcxaudio */214#define E_SOURCE_AUDIO 0x1800 /* 3 >> 1 */215/* Error virtual pcx */216#define E_SOURCE_VPCX 0x2800 /* 5 >> 1 */217/* Error dispatcher */218#define E_SOURCE_DISPATCHER 0x3000 /* 6 >> 1 */219/* Error from CobraNet firmware */220#define E_SOURCE_COBRANET 0x3800 /* 7 >> 1 */221 222#define E_SOURCE_USER 0x7800223 224#define CLASS_MASK 0x0700225 226#define CODE_MASK 0x00FF227 228/* Bits values */229 230/* Values for the error/warning bit */231#define ERROR_VALUE 0x8000232#define WARNING_VALUE 0x0000233 234/* Class values */235#define E_CLASS_GENERAL 0x0000236#define E_CLASS_INVALID_CMD 0x0100237#define E_CLASS_INVALID_STD_OBJECT 0x0200238#define E_CLASS_RSRC_IMPOSSIBLE 0x0300239#define E_CLASS_WRONG_CONTEXT 0x0400240#define E_CLASS_BAD_SPECIFIC_PARAMETER 0x0500241#define E_CLASS_REAL_TIME_ERROR 0x0600242#define E_CLASS_DIRECTSHOW 0x0700243#define E_CLASS_FREE 0x0700244 245 246/* Complete DRV error code for the general class */247#define ED_GN (ERROR_VALUE | E_SOURCE_DRV | E_CLASS_GENERAL)248#define ED_CONCURRENCY (ED_GN | 0x01)249#define ED_DSP_CRASHED (ED_GN | 0x02)250#define ED_UNKNOWN_BOARD (ED_GN | 0x03)251#define ED_NOT_INSTALLED (ED_GN | 0x04)252#define ED_CANNOT_OPEN_SVC_MANAGER (ED_GN | 0x05)253#define ED_CANNOT_READ_REGISTRY (ED_GN | 0x06)254#define ED_DSP_VERSION_MISMATCH (ED_GN | 0x07)255#define ED_UNAVAILABLE_FEATURE (ED_GN | 0x08)256#define ED_CANCELLED (ED_GN | 0x09)257#define ED_NO_RESPONSE_AT_IRQA (ED_GN | 0x10)258#define ED_INVALID_ADDRESS (ED_GN | 0x11)259#define ED_DSP_CORRUPTED (ED_GN | 0x12)260#define ED_PENDING_OPERATION (ED_GN | 0x13)261#define ED_NET_ALLOCATE_MEMORY_IMPOSSIBLE (ED_GN | 0x14)262#define ED_NET_REGISTER_ERROR (ED_GN | 0x15)263#define ED_NET_THREAD_ERROR (ED_GN | 0x16)264#define ED_NET_OPEN_ERROR (ED_GN | 0x17)265#define ED_NET_CLOSE_ERROR (ED_GN | 0x18)266#define ED_NET_NO_MORE_PACKET (ED_GN | 0x19)267#define ED_NET_NO_MORE_BUFFER (ED_GN | 0x1A)268#define ED_NET_SEND_ERROR (ED_GN | 0x1B)269#define ED_NET_RECEIVE_ERROR (ED_GN | 0x1C)270#define ED_NET_WRONG_MSG_SIZE (ED_GN | 0x1D)271#define ED_NET_WAIT_ERROR (ED_GN | 0x1E)272#define ED_NET_EEPROM_ERROR (ED_GN | 0x1F)273#define ED_INVALID_RS232_COM_NUMBER (ED_GN | 0x20)274#define ED_INVALID_RS232_INIT (ED_GN | 0x21)275#define ED_FILE_ERROR (ED_GN | 0x22)276#define ED_INVALID_GPIO_CMD (ED_GN | 0x23)277#define ED_RS232_ALREADY_OPENED (ED_GN | 0x24)278#define ED_RS232_NOT_OPENED (ED_GN | 0x25)279#define ED_GPIO_ALREADY_OPENED (ED_GN | 0x26)280#define ED_GPIO_NOT_OPENED (ED_GN | 0x27)281#define ED_REGISTRY_ERROR (ED_GN | 0x28) /* <- NCX */282#define ED_INVALID_SERVICE (ED_GN | 0x29) /* <- NCX */283 284#define ED_READ_FILE_ALREADY_OPENED (ED_GN | 0x2a) /* <- Decalage285 * pour RCX286 * (old 0x28)287 * */288#define ED_READ_FILE_INVALID_COMMAND (ED_GN | 0x2b) /* ~ */289#define ED_READ_FILE_INVALID_PARAMETER (ED_GN | 0x2c) /* ~ */290#define ED_READ_FILE_ALREADY_CLOSED (ED_GN | 0x2d) /* ~ */291#define ED_READ_FILE_NO_INFORMATION (ED_GN | 0x2e) /* ~ */292#define ED_READ_FILE_INVALID_HANDLE (ED_GN | 0x2f) /* ~ */293#define ED_READ_FILE_END_OF_FILE (ED_GN | 0x30) /* ~ */294#define ED_READ_FILE_ERROR (ED_GN | 0x31) /* ~ */295 296#define ED_DSP_CRASHED_EXC_DSPSTACK_OVERFLOW (ED_GN | 0x32) /* <- Decalage pour297 * PCX (old 0x14) */298#define ED_DSP_CRASHED_EXC_SYSSTACK_OVERFLOW (ED_GN | 0x33) /* ~ */299#define ED_DSP_CRASHED_EXC_ILLEGAL (ED_GN | 0x34) /* ~ */300#define ED_DSP_CRASHED_EXC_TIMER_REENTRY (ED_GN | 0x35) /* ~ */301#define ED_DSP_CRASHED_EXC_FATAL_ERROR (ED_GN | 0x36) /* ~ */302 303#define ED_FLASH_PCCARD_NOT_PRESENT (ED_GN | 0x37)304 305#define ED_NO_CURRENT_CLOCK (ED_GN | 0x38)306 307/* Complete DRV error code for real time class */308#define ED_RT (ERROR_VALUE | E_SOURCE_DRV | E_CLASS_REAL_TIME_ERROR)309#define ED_DSP_TIMED_OUT (ED_RT | 0x01)310#define ED_DSP_CHK_TIMED_OUT (ED_RT | 0x02)311#define ED_STREAM_OVERRUN (ED_RT | 0x03)312#define ED_DSP_BUSY (ED_RT | 0x04)313#define ED_DSP_SEMAPHORE_TIME_OUT (ED_RT | 0x05)314#define ED_BOARD_TIME_OUT (ED_RT | 0x06)315#define ED_XILINX_ERROR (ED_RT | 0x07)316#define ED_COBRANET_ITF_NOT_RESPONDING (ED_RT | 0x08)317 318/* Complete BOARD error code for the invaid standard object class */319#define EB_ISO (ERROR_VALUE | E_SOURCE_BOARD | \320 E_CLASS_INVALID_STD_OBJECT)321#define EB_INVALID_EFFECT (EB_ISO | 0x00)322#define EB_INVALID_PIPE (EB_ISO | 0x40)323#define EB_INVALID_STREAM (EB_ISO | 0x80)324#define EB_INVALID_AUDIO (EB_ISO | 0xC0)325 326/* Complete BOARD error code for impossible resource allocation class */327#define EB_RI (ERROR_VALUE | E_SOURCE_BOARD | E_CLASS_RSRC_IMPOSSIBLE)328#define EB_ALLOCATE_ALL_STREAM_TRANSFERT_BUFFERS_IMPOSSIBLE (EB_RI | 0x01)329#define EB_ALLOCATE_PIPE_SAMPLE_BUFFER_IMPOSSIBLE (EB_RI | 0x02)330 331#define EB_ALLOCATE_MEM_STREAM_IMPOSSIBLE \332 EB_ALLOCATE_ALL_STREAM_TRANSFERT_BUFFERS_IMPOSSIBLE333#define EB_ALLOCATE_MEM_PIPE_IMPOSSIBLE \334 EB_ALLOCATE_PIPE_SAMPLE_BUFFER_IMPOSSIBLE335 336#define EB_ALLOCATE_DIFFERED_CMD_IMPOSSIBLE (EB_RI | 0x03)337#define EB_TOO_MANY_DIFFERED_CMD (EB_RI | 0x04)338#define EB_RBUFFERS_TABLE_OVERFLOW (EB_RI | 0x05)339#define EB_ALLOCATE_EFFECTS_IMPOSSIBLE (EB_RI | 0x08)340#define EB_ALLOCATE_EFFECT_POS_IMPOSSIBLE (EB_RI | 0x09)341#define EB_RBUFFER_NOT_AVAILABLE (EB_RI | 0x0A)342#define EB_ALLOCATE_CONTEXT_LIII_IMPOSSIBLE (EB_RI | 0x0B)343#define EB_STATUS_DIALOG_IMPOSSIBLE (EB_RI | 0x1D)344#define EB_CONTROL_CMD_IMPOSSIBLE (EB_RI | 0x1E)345#define EB_STATUS_SEND_IMPOSSIBLE (EB_RI | 0x1F)346#define EB_ALLOCATE_PIPE_IMPOSSIBLE (EB_RI | 0x40)347#define EB_ALLOCATE_STREAM_IMPOSSIBLE (EB_RI | 0x80)348#define EB_ALLOCATE_AUDIO_IMPOSSIBLE (EB_RI | 0xC0)349 350/* Complete BOARD error code for wrong call context class */351#define EB_WCC (ERROR_VALUE | E_SOURCE_BOARD | E_CLASS_WRONG_CONTEXT)352#define EB_CMD_REFUSED (EB_WCC | 0x00)353#define EB_START_STREAM_REFUSED (EB_WCC | 0xFC)354#define EB_SPC_REFUSED (EB_WCC | 0xFD)355#define EB_CSN_REFUSED (EB_WCC | 0xFE)356#define EB_CSE_REFUSED (EB_WCC | 0xFF)357 358 359 360 361#endif /* LX_DEFS_H */362