112 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2#define CS4245_CHIP_ID 0x013#define CS4245_POWER_CTRL 0x024#define CS4245_DAC_CTRL_1 0x035#define CS4245_ADC_CTRL 0x046#define CS4245_MCLK_FREQ 0x057#define CS4245_SIGNAL_SEL 0x068#define CS4245_PGA_B_CTRL 0x079#define CS4245_PGA_A_CTRL 0x0810#define CS4245_ANALOG_IN 0x0911#define CS4245_DAC_A_CTRL 0x0a12#define CS4245_DAC_B_CTRL 0x0b13#define CS4245_DAC_CTRL_2 0x0c14#define CS4245_INT_STATUS 0x0d15#define CS4245_INT_MASK 0x0e16#define CS4245_INT_MODE_MSB 0x0f17#define CS4245_INT_MODE_LSB 0x1018 19/* Chip ID */20#define CS4245_CHIP_PART_MASK 0xf021#define CS4245_CHIP_REV_MASK 0x0f22 23/* Power Control */24#define CS4245_FREEZE 0x8025#define CS4245_PDN_MIC 0x0826#define CS4245_PDN_ADC 0x0427#define CS4245_PDN_DAC 0x0228#define CS4245_PDN 0x0129 30/* DAC Control */31#define CS4245_DAC_FM_MASK 0xc032#define CS4245_DAC_FM_SINGLE 0x0033#define CS4245_DAC_FM_DOUBLE 0x4034#define CS4245_DAC_FM_QUAD 0x8035#define CS4245_DAC_DIF_MASK 0x3036#define CS4245_DAC_DIF_LJUST 0x0037#define CS4245_DAC_DIF_I2S 0x1038#define CS4245_DAC_DIF_RJUST_16 0x2039#define CS4245_DAC_DIF_RJUST_24 0x3040#define CS4245_RESERVED_1 0x0841#define CS4245_MUTE_DAC 0x0442#define CS4245_DEEMPH 0x0243#define CS4245_DAC_MASTER 0x0144 45/* ADC Control */46#define CS4245_ADC_FM_MASK 0xc047#define CS4245_ADC_FM_SINGLE 0x0048#define CS4245_ADC_FM_DOUBLE 0x4049#define CS4245_ADC_FM_QUAD 0x8050#define CS4245_ADC_DIF_MASK 0x1051#define CS4245_ADC_DIF_LJUST 0x0052#define CS4245_ADC_DIF_I2S 0x1053#define CS4245_MUTE_ADC 0x0454#define CS4245_HPF_FREEZE 0x0255#define CS4245_ADC_MASTER 0x0156 57/* MCLK Frequency */58#define CS4245_MCLK1_MASK 0x7059#define CS4245_MCLK1_SHIFT 460#define CS4245_MCLK2_MASK 0x0761#define CS4245_MCLK2_SHIFT 062#define CS4245_MCLK_1 063#define CS4245_MCLK_1_5 164#define CS4245_MCLK_2 265#define CS4245_MCLK_3 366#define CS4245_MCLK_4 467 68/* Signal Selection */69#define CS4245_A_OUT_SEL_MASK 0x6070#define CS4245_A_OUT_SEL_HIZ 0x0071#define CS4245_A_OUT_SEL_DAC 0x2072#define CS4245_A_OUT_SEL_PGA 0x4073#define CS4245_LOOP 0x0274#define CS4245_ASYNCH 0x0175 76/* Channel B/A PGA Control */77#define CS4245_PGA_GAIN_MASK 0x3f78 79/* ADC Input Control */80#define CS4245_PGA_SOFT 0x1081#define CS4245_PGA_ZERO 0x0882#define CS4245_SEL_MASK 0x0783#define CS4245_SEL_MIC 0x0084#define CS4245_SEL_INPUT_1 0x0185#define CS4245_SEL_INPUT_2 0x0286#define CS4245_SEL_INPUT_3 0x0387#define CS4245_SEL_INPUT_4 0x0488#define CS4245_SEL_INPUT_5 0x0589#define CS4245_SEL_INPUT_6 0x0690 91/* DAC Channel A/B Volume Control */92#define CS4245_VOL_MASK 0xff93 94/* DAC Control 2 */95#define CS4245_DAC_SOFT 0x8096#define CS4245_DAC_ZERO 0x4097#define CS4245_INVERT_DAC 0x2098#define CS4245_INT_ACTIVE_HIGH 0x0199 100/* Interrupt Status/Mask/Mode */101#define CS4245_ADC_CLK_ERR 0x08102#define CS4245_DAC_CLK_ERR 0x04103#define CS4245_ADC_OVFL 0x02104#define CS4245_ADC_UNDRFL 0x01105 106#define CS4245_SPI_ADDRESS_S (0x9e << 16)107#define CS4245_SPI_WRITE_S (0 << 16)108 109#define CS4245_SPI_ADDRESS 0x9e110#define CS4245_SPI_WRITE 0111#define CS4245_SPI_READ 1112